Jason Cong | Academic Influence

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Jason Cong

Computer Science

#2308

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#2405

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Computer Architecture

#18

World Rank

#18

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Database

#687

World Rank

#721

Historical Rank

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Computer Science

Jason Cong's Degrees

Bachelors Computer Science Tsinghua University

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Why Is Jason Cong Influential?

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According to Wikipedia, Jingsheng Jason Cong is a Chinese-born American computer scientist, educator, and serial entrepreneur. He received his B.S. degree in computer science from Peking University in 1985, his M.S. and Ph. D. degrees in computer science from the University of Illinois at Urbana-Champaign in 1987 and 1990, respectively. He has been on the faculty in the Computer Science Department at the University of California, Los Angeles since 1990. Currently, he is a Distinguished Chancellor’s Professor and the director of Center for Domain-Specific Computing .

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Jason Cong's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks (2015) (1681)
High-Level Synthesis for FPGAs: From Prototyping to Deployment (2011) (707)
An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs (1992) (682)
A thermal-driven floorplanning algorithm for 3D ICs (2004) (419)
Caffeine: Towards uniformed representation and acceleration for deep convolutional neural networks (2016) (343)
Automated systolic array architecture synthesis for high throughput CNN inference on FPGAs (2017) (323)
Performance optimization of VLSI interconnect layout (1996) (315)
Minimizing Computation in Convolutional Neural Networks (2014) (313)
CMP network-on-chip overlaid with multi-band RF-interconnect (2008) (280)
Scaling for edge inference of deep neural networks (2018) (266)
Application-specific instruction generation for configurable processor architectures (2004) (243)
FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates (2017) (231)
A scalable micro wireless interconnect structure for CMPs (2009) (223)
Provably good performance-driven global routing (1992) (209)
An interconnect-centric design flow for nanometer technologies (1999) (202)
Interconnect design for deep submicron ICs (1997) (198)
On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping (1993) (197)
Architecture evaluation for power-efficient FPGAs (2003) (195)
Performance-Driven Interconnect Design Based on Distributed RC Delay Model (1993) (193)
Multilevel generalized force-directed method for circuit placement (2005) (191)
mPL6: enhanced multilevel mixed-size placement (2006) (188)
FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs (2009) (179)
Cut ranking and pruning: enabling a general and efficient FPGA mapping solution (1999) (178)
A Parallel Bottom-up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design (1993) (176)
Thermal via planning for 3-D ICs (2005) (173)
Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics (2004) (173)
Energy-Efficient CNN Implementation on a Deeply Pipelined FPGA Cluster (2016) (168)
An efficient design and implementation of LSM-tree based key-value store on open-channel SSD (2014) (162)
Polyhedral-based data reuse optimization for configurable computing (2013) (161)
An efficient and versatile scheduling algorithm based on SDC formulation (2006) (158)
DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs (2004) (154)
FPGA Design Automation: A Survey (2006) (152)
Power modeling and characteristics of field programmable gate arrays (2005) (152)
Thermal-Aware 3D IC Placement Via Transformation (2007) (152)
Buffer block planning for interconnect-driven floorplanning (1999) (150)
Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks (2019) (145)
FPGA-based accelerator for long short-term memory recurrent neural networks (2017) (143)
Multilevel optimization for large-scale circuit placement (2000) (142)
mrFPGA: A novel FPGA architecture with memristor-based reconfiguration (2011) (142)
DAG-Map: graph-based FPGA technology mapping for delay optimization (1992) (140)
Buffered Steiner tree construction with wire sizing for interconnect layout optimization (1996) (140)
High-performance clock routing based on recursive geometric matching (1991) (138)
Improved crosstalk modeling for noise constrained interconnect optimization (2001) (136)
Bounded-skew clock and Steiner routing (1998) (133)
AutoPilot: A Platform-Based ESL Synthesis System (2008) (133)
Combinational logic synthesis for LUT based field programmable gate arrays (1996) (130)
Challenges and Opportunities for Design Innovations in Nanometer Technologies (1998) (124)
A quantitative analysis on microarchitectures of modern CPU-FPGA platforms (2016) (124)
Optimal wiresizing under Elmore delay model (1995) (124)
Optimal wiresizing under the distributed Elmore delay model (1993) (114)
Routability-driven placement and white space allocation (2004) (114)
Simultaneous Driver And Wire Sizing For Performance And Power Optimization* (1994) (113)
Low-power high-level synthesis for FPGA architectures (2003) (111)
Optimality and scalability study of existing placement algorithms (2003) (111)
SACNN: Self-Attention Convolutional Neural Network for Low-Dose CT Denoising With Self-Supervised Perceptual Loss Network (2020) (110)
RASP: A General Logic Synthesis System for SRAM-Based FPGAs (1996) (108)
Architecture support for accelerator-rich CMPs (2012) (107)
Customizable Domain-Specific Computing (2009) (106)
Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping (1995) (99)
Efficient algorithms for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design (1998) (97)
Thermal-driven multilevel routing for 3-D ICs (2005) (94)
An automated lung segmentation approach using bidirectional chain codes to improve nodule detection accuracy (2015) (93)
CHARM: a composable heterogeneous accelerator-rich microprocessor (2012) (92)
Intellectual property protection by watermarking combinational logic synthesis solutions (1998) (88)
Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design (2012) (88)
Edge separability-based circuit clustering with application to multilevel circuit partitioning (2004) (88)
Simultaneous buffer and wire sizing for performance and power optimization (1996) (87)
Accelerator-rich architectures: Opportunities and progresses (2014) (86)
Optimality Study of Logic Synthesis for LUT-Based FPGAs (2006) (84)
Multiway partitioning with pairwise movement (1998) (84)
Over-the-cell channel routing (1988) (84)
FPGA-RPI: A Novel FPGA Architecture With RRAM-Based Programmable Interconnects (2014) (83)
Improving high level synthesis optimization opportunity through polyhedral transformations (2013) (83)
Automatic memory partitioning and scheduling for throughput and power optimization (2011) (82)
Large scale circuit partitioning with loose/stable net removal and signal flow based clustering (1997) (81)
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing (2019) (81)
Register binding and port assignment for multiplexer optimization (2004) (80)
Programming and Runtime Support to Blaze FPGA Accelerator Deployment at Datacenter Scale (2016) (80)
Memory partitioning for multidimensional arrays in high-level synthesis (2013) (79)
Edge separability based circuit clustering with application to circuit partitioning (2000) (79)
Atlas: Baidu's key-value storage system for cloud data (2015) (78)
Interconnect performance estimation models for design planning (2001) (78)
Understanding Performance Differences of FPGAs and GPUs (2018) (77)
Pattern-based behavior synthesis for FPGA resource reduction (2008) (77)
Energy-efficient scheduling on heterogeneous multi-core architectures (2012) (77)
Platform-Based Behavior-Level and System-Level Synthesis (2006) (77)
Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures (2009) (76)
Fast floorplanning by look-ahead enabled recursive bipartitioning (2005) (75)
Architecture and synthesis for on-chip multicycle communication (2004) (75)
Optimal wiresizing for interconnects with multiple sources (1995) (75)
Theory and algorithm for generalized memory partitioning in high-level synthesis (2014) (74)
Thermal-driven multilevel routing for 3D ICs (2005) (73)
Optimality, scalability and stability study of partitioning and placement algorithms (2003) (73)
Multi-level placement for large-scale mixed-size IC designs (2003) (72)
Power reduction of CMP communication networks via RF-interconnects (2008) (71)
Incremental physical design (2000) (70)
Matching-based methods for high-performance clock routing (1993) (70)
Technology mapping for FPGAs with embedded memory blocks (1998) (70)
Acyclic Multi-Way Partitioning of Boolean Networks (1994) (69)
PolySA: Polyhedral-Based Systolic Array Auto-Compilation (2018) (68)
Large-scale circuit placement (2005) (67)
A Fully Pipelined and Dynamically Composable Architecture of CGRA (2014) (67)
Thermal-aware cell and through-silicon-via co-placement for 3D ICs (2011) (67)
An enhanced multilevel algorithm for circuit placement (2003) (66)
SODA: Stencil with Optimized Dataflow Architecture (2018) (66)
An Efficient Multilayer MCM Router Based on Four-Via Routing (1993) (65)
Multilevel approach to full-chip gridless routing (2001) (65)
INSIDER: Designing In-Storage Computing System for Emerging High-Performance Drive (2019) (64)
Optimal Layout Synthesis for Quantum Computing (2020) (64)
Instruction set extension with shadow registers for configurable processors (2005) (64)
A multilevel analytical placement for 3D ICs (2009) (64)
Net partitions yield better module partitions (1992) (63)
Physical planning with retiming (2000) (62)
An enhanced multilevel routing system (2002) (62)
Minimum-cost bounded-skew clock routing (1995) (61)
A new algorithm for standard cell global routing (1988) (60)
Optimizing memory hierarchy allocation with loop transformations for high-level synthesis (2012) (60)
An implicit connection graph maze routing algorithm for ECO routing (1999) (59)
Microarchitecture evaluation with physical planning (2003) (59)
RF interconnects for communications on-chip (2008) (59)
MARS-a multilevel full-chip gridless routing system (2005) (59)
High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs (2007) (59)
Interconnect delay estimation models for synthesis and design planning (1999) (59)
Supporting Address Translation for Accelerator-Centric Architectures (2017) (58)
Boolean matching for LUT-based logic blocks with applications toarchitecture evaluation and technology mapping (2001) (58)
Bounded-skew clock and Steiner routing under Elmore delay (1995) (56)
Three Dimensional Integrated Circuit Design (2010) (55)
Performance-driven mapping for CPLD architectures (2001) (55)
Performance driven multi-layer general area routing for PCB/MCM designs (1998) (55)
A Novel High-Throughput Acceleration Engine for Read Alignment (2015) (55)
Interconnect sizing and spacing with consideration of couplingcapacitance (1997) (54)
General models and algorithms for over-the-cell routing in standard cell design (1990) (54)
Routing tree construction under fixed buffer locations (2000) (54)
Physical hierarchy generation with routing congestion control (2002) (54)
TGPA: Tile-Grained Pipeline Architecture for Low Latency CNN Inference (2018) (54)
High-Speed mm-Wave Data-Link Based on Hollow Plastic Cable and CMOS Transceiver (2013) (53)
Low-power technology mapping for FPGA architectures with dual supply voltages (2004) (53)
AutoSA: A Polyhedral Compiler for High-Performance Systolic Arrays on FPGA (2021) (52)
An energy-efficient adaptive hybrid cache (2011) (52)
An automated design flow for 3D microarchitecture evaluation (2006) (52)
Multilevel global placement with congestion control (2003) (52)
Mapping a data-flow programming model onto heterogeneous platforms (2012) (52)
Improving polyhedral code generation for high-level synthesis (2013) (51)
Energy efficient multiprocessor task scheduling under input-dependent variation (2009) (50)
Performance driven multi-level and multiway partitioning with retiming (2000) (49)
A new approach to three- or four-layer channel routing (1988) (48)
An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers (2014) (48)
Incremental CAD (2000) (47)
Optimality Study of Existing Quantum Computing Layout Synthesis Tools (2020) (47)
Automated Accelerator Generation and Optimization with Composable, Parallel and Pipeline Architecture (2018) (47)
xPilot: A Platform-Based Behavioral Synthesis System (2005) (47)
Synthesis for FPGAs with embedded memory blocks (2000) (46)
Modern Circuit Placement, Best Practices and Results (2007) (46)
An Analytical Placement Framework for 3-D ICs and Its Extension on Thermal Awareness (2013) (46)
An efficient approach to multilayer layer assignment with anapplication to via minimization (1999) (46)
Simultaneous Timing Driven Clustering and Placement for FPGAs (2004) (46)
Pin assignment with global routing for general cell designs (1991) (45)
Multilevel Optimization in VLSICAD (2003) (45)
Multilevel Granularity Parallelism Synthesis on FPGAs (2011) (45)
Assuring application-level correctness against soft errors (2011) (45)
PARADE: A cycle-accurate full-system simulation Platform for Accelerator-Rich Architectural Design and Exploration (2015) (45)
LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization (2010) (45)
Simultaneous FU and Register Binding Based on Network Flow Method (2008) (44)
Bitwidth-aware scheduling and binding in high-level synthesis (2005) (44)
DUNE: a multi-layer gridless routing system with wire planning (2000) (44)
Bandwidth optimization through on-chip memory restructuring for HLS (2017) (43)
Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs (2016) (43)
Performance-driven global routing for cell based ICs (1991) (43)
Protecting Combinational Logic Synthesis Solutions (2006) (43)
Hardware Acceleration of Long Read Pairwise Overlapping in Genome Sequencing: A Race Between FPGA and GPU (2019) (43)
FPGA-Based Hardware Acceleration of Lithographic Aerial Image Simulation (2009) (42)
A robust detailed placement for mixed-size IC designs (2006) (42)
Random walks for circuit clustering (1991) (42)
A Robust Mixed-Size Legalization and Detailed Placement Algorithm (2008) (41)
Global interconnect sizing and spacing with consideration of coupling capacitance (1997) (41)
Multi-way VLSI Circuit Partitioning Based On Dual Net Representation (1994) (41)
Overcoming Data Transfer Bottlenecks in FPGA-based DNN Accelerators via Layer Conscious Memory Management (2019) (41)
When Spark Meets FPGAs: A Case Study for Next-Generation DNA Sequencing Acceleration (2016) (41)
Optimal simultaneous mapping and clustering for FPGA delay optimization (2006) (40)
Interconnect estimation and planning for deep submicron designs (1999) (40)
Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs (1993) (40)
A fast multilayer general area router for MCM designs (1992) (39)
Static and dynamic co-optimizations for blocks mapping in hybrid caches (2012) (39)
Highly Efficient Gradient Computation for Density-Constrained Analytical Placement (2008) (39)
High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA Platforms (2018) (38)
Simultaneous circuit partitioning/clustering with retiming for performance optimization (1999) (38)
Source-to-Source Optimization for HLS (2016) (37)
An interconnect energy model considering coupling effects (2001) (37)
Technology mapping and architecture evalution for k/m-macrocell-based FPGAs (2005) (37)
Interconnect layout optimization under higher-order RLC model (1997) (37)
MC-Sim: An efficient simulation tool for MPSoC designs (2008) (37)
A reuse-aware prefetching scheme for scratchpad memory (2011) (37)
An integrated and automated memory optimization flow for FPGA behavioral synthesis (2012) (37)
When apache spark meets FPGAs: a case study for next-generation DNA sequencing acceleration (2016) (36)
The SMEM Seeding Acceleration for DNA Sequence Alignment (2016) (36)
AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs (2021) (36)
Improved SAT-based Boolean matching using implicants for LUT-based FPGAs (2007) (36)
Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization (2009) (36)
Interconnect Layout Optimization by Simultaneous Steiner Tree Construction and Buffer Insertion (1996) (36)
DUNE-a multilayer gridless routing system (2001) (36)
Composable accelerator-rich microprocessor enhanced for adaptivity and longevity (2013) (35)
Optimal FPGA mapping and retiming with efficient initial state computation (1998) (34)
Parallel multi-level analytical global placement on graphics processing units (2009) (34)
Delay-optimal technology mapping for FPGAs with heterogeneous LUTs (1998) (34)
HBM Connect: High-Performance HLS Interconnect for FPGA HBM (2021) (34)
Performance-driven multi-level clustering with application to hierarchical FPGA mapping (2001) (34)
mPL6: a robust multilevel mixed-size placement engine (2005) (34)
An efficient and flexible host-FPGA PCIe communication library (2014) (34)
On the k-layer planar subset and topological via minimization problems (1991) (34)
Platform-Based Resource Binding Using a Distributed Register-File Microarchitecture (2006) (34)
HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration (2020) (33)
Simultaneous timing-driven placement and duplication (2005) (33)
Buffer block planning for interconnect planning and prediction (2001) (33)
Combining computation and communication optimizations in system synthesis for streaming applications (2014) (33)
Accelerator-rich CMPs: From concept to real hardware (2013) (33)
Resource-Aware Throughput Optimization for High-Level Synthesis (2015) (33)
Memory partitioning and scheduling co-optimization in behavioral synthesis (2012) (32)
Synthesis of an application-specific soft multiprocessor system (2007) (32)
A provably good multilayer topological planar routing algorithm in IC layout designs (1993) (32)
Placement-driven technology mapping for LUT-based FPGAs (2003) (32)
S2FA: An Accelerator Automation Framework for Heterogeneous Computing in Datacenters (2018) (32)
Architecture-level synthesis for automatic interconnect pipelining (2004) (32)
LP based white space redistribution for thermal via planning and performance optimization in 3D ICs (2008) (31)
System Light-Loading Technology for mHealth: Manifold-Learning-Based Medical Data Cleansing and Clinical Trials in WE-CARE Project (2014) (31)
SPFD-based global rewiring (2002) (31)
Wire width planning for interconnect performance optimization (2002) (31)
The new line in IC design (1997) (30)
Combining module selection and replication for throughput-driven streaming programs (2012) (30)
An efficient approach to simultaneous transistor and interconnect sizing (1996) (29)
Fine grain 3D integration for microarchitecture design through cube packing exploration (2007) (29)
Bonsai: High-Performance Adaptive Merge Tree Sorting (2020) (29)
Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing (1999) (29)
HLScope+,: Fast and accurate performance estimation for FPGA HLS (2017) (29)
Bit-level optimization for high-level synthesis and FPGA-based acceleration (2010) (29)
End-to-End Optimization of Deep Learning Applications (2020) (29)
Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA design (1996) (29)
On-chip interconnection network for accelerator-rich architectures (2015) (29)
Optimality and scalability study of existing placement algorithms (2003) (29)
Performance-driven technology mapping for heterogeneous FPGAs (2000) (29)
Architecture and synthesis for multi-cycle communication (2003) (28)
Platform characterization for Domain-Specific Computing (2012) (28)
Performance driven global routing for standard cell design (1997) (28)
Extending High-Level Synthesis for Task-Parallel Programs (2020) (27)
Software Infrastructure for Enabling FPGA-Based Accelerations in Data Centers: Invited Paper (2016) (27)
Pseudo pin assignment with crosstalk noise control (2000) (27)
Robust mixed-size placement under tight white-space constraints (2005) (26)
Simultaneous logic decomposition with technology mapping in FPGA designs (2001) (26)
Automatic memory partitioning and scheduling for throughput and power optimization (2009) (26)
Oscillatory neurocomputing with ring attractors: a network architecture for mapping locations in space onto patterns of neural synchrony (2014) (25)
In-Depth Analysis on Microarchitectures of Modern Heterogeneous CPU-FPGA Platforms (2019) (25)
Scheduling with soft constraints (2009) (25)
HLScope: High-Level Performance Debugging for FPGA Designs (2017) (25)
Designing scratchpad memory architecture with emerging STT-RAM memory technologies (2013) (25)
Optimality study of resource binding with multi-Vdds (2006) (25)
BiN: a buffer-in-NUCA scheme for accelerator-rich CMPs (2012) (25)
Scheduling with integer time budgeting for low-power optimization (2008) (25)
Invited: Heterogeneous datacenters: Options and opportunities (2016) (24)
Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture (2009) (24)
ACES: Application-specific cycle elimination and splitting for deadlock-free routing on irregular Network-on-Chip (2010) (24)
Delay optimal low-power circuit clustering for FPGAs with dual supply voltages (2004) (24)
FPGA-accelerated 3D reconstruction using compressive sensing (2012) (24)
Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs (2000) (23)
Microarchitecture evaluation with floorplanning and interconnect pipelining (2005) (23)
A 60GHz on-chip RF-Interconnect with λ/4 coupler for 5Gbps bi-directional communication and multi-drop arbitration (2012) (23)
Optimality and stability study of timing-driven placement algorithms (2003) (23)
Logic-on-logic 3D integration and placement (2010) (23)
The DIMM tree architecture: A high bandwidth and scalable memory system (2011) (23)
Multilevel global placement with retiming (2003) (23)
Fpga Synthesis With Retiming And Pipelining For Clock Period Minimization Of Sequential Circuits (1997) (23)
Efficient compilation of CUDA kernels for high-performance computing on FPGAs (2013) (23)
RF-Interconnect for Future Network-On-Chip (2011) (23)
Pseudopin assignment with crosstalk noise control (2001) (23)
LUT-based FPGA technology mapping for reliability (2010) (22)
Optimal simultaneous module and multivoltage assignment for low power (2006) (22)
Optimal module and voltage assignment for low-power (2005) (22)
Analysis of Noncoherent ASK Modulation-Based RF-Interconnect for Memory Interface (2012) (22)
Accelerating Fluid Registration Algorithm on Multi-FPGA Platforms (2011) (22)
Via Minimization by Layout Modification (1989) (22)
Optimizing routability in large-scale mixed-size placement (2013) (22)
Performance driven multiway partitioning (2000) (22)
Lithographic aerial image simulation with FPGA-based hardwareacceleration (2008) (22)
Frequency Improvement of Systolic Array-Based CNNs on FPGAs (2019) (21)
Large-scale circuit placement: gap and promise (2003) (21)
Acceleration of EM-Based 3D CT Reconstruction Using FPGA (2016) (21)
Logic synthesis for better than worst-case designs (2009) (21)
Delay-oriented technology mapping for heterogeneous FPGAs with bounded resources (1998) (21)
An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using simultaneous bidirectional Dual (Base+RF) band signaling (2011) (21)
TENET: A Framework for Modeling Tensor Dataflow Based on Relation-centric Notation (2021) (21)
Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency (2020) (21)
Combined loop transformation and hierarchy allocation for data reuse optimization (2011) (21)
Timing closure based on physical hierarchy (2002) (21)
Provably good algorithms for performance-driven global routing (1992) (21)
Performance-driven routing with multiple sources (1997) (21)
A new enhanced SPFD rewiring algorithm (2002) (20)
Pin assignment with global routing (1989) (20)
ATree-based topology synthesis for on-chip network (2011) (20)
AXR-CMP : Architecture Support in Accelerator-Rich CMPs (2011) (20)
SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs (2020) (20)
An Efficient Approach To Multi-layer Layer Assignment With Application To Via Minimization (1997) (19)
Doppio: I/O-Aware Performance Analysis, Modeling and Optimization for In-memory Computing Framework (2018) (19)
Best-Effort FPGA Programming: A Few Steps Can Go a Long Way (2018) (19)
Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages (2010) (19)
CMOST: A system-level FPGA compilation framework (2015) (19)
Multi-way partitioning using bi-partition heuristics (2000) (19)
LUT-based FPGA technology mapping under arbitrary net-delay models (1994) (19)
An efficient technique for device and interconnect optimization in deep submicron designs (1998) (19)
Architecture Support for Domain-Specific Accelerator-Rich CMPs (2014) (19)
A Hybrid Architecture for Compressive Sensing 3-D CT Reconstruction (2012) (19)
Synthesis of reconfigurable high-performance multicore systems (2009) (19)
On High-Speed VLSI Interconnects: Analysis and Design (1992) (18)
Boolean matching for complex PLBs in LUT-based FPGAs with application to architecture evaluation (1998) (18)
Optimization of interconnects between accelerators and shared memories in dark silicon (2013) (18)
A Study on the Impact of Compiler Optimizations on High-Level Synthesis (2012) (18)
AutoDSE: Enabling Software Programmers Design Efficient FPGA Accelerators (2020) (18)
ST-Accel: A High-Level Programming Platform for Streaming Applications on FPGA (2018) (18)
Routability-driven placement and white space allocation (2007) (18)
Architectural synthesis Integrated with global placement for multi-cycle communication (2003) (18)
Towards layout-friendly high-level synthesis (2012) (18)
HLS-Based Optimization and Design Space Exploration for Applications with Variable Loop Bounds (2018) (18)
A 3D physical design flow based on Open Access (2009) (18)
An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression (2012) (18)
Communication Optimization on GPU: A Case Study of Sequence Alignment Algorithms (2017) (17)
CS-BWAMEM : A fast and scalable read aligner at the cloud scale for whole genome sequencing (2015) (17)
Architecture and compilation for data bandwidth improvement in configurable embedded processors (2005) (17)
Via design rule consideration in multilayer maze routing algorithms (2000) (17)
High-performance CUDA kernel execution on FPGAs (2009) (17)
HC-Sim: A fast and exact L1 cache simulator with scratchpad memory co-simulation support (2011) (17)
Accelerating Sequential Applications on CMPs Using Core Spilling (2007) (17)
Technology mapping for k/m-macrocell based FPGAs (2000) (17)
Latte: Locality Aware Transformation for High-Level Synthesis (2018) (17)
Coordinated resource optimization in behavioral synthesis (2010) (17)
Relaxed simulated tempering for VLSI floorplan designs (1999) (17)
Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication (2021) (17)
A scalable, high-performance customized priority queue (2014) (17)
On the k-layer planar subset and via minimization problems (1990) (16)
Throughput Optimization for High-Level Synthesis Using Resource Constraints (2014) (16)
Throughput optimization for streaming applications on CPU-FPGA heterogeneous systems (2017) (16)
Computed Tomography Image Enhancement using 3D Convolutional Neural Network (2018) (16)
NSF Workshop on EDA: Past, Present, and Future (Part 2) (2010) (16)
Exploiting signal flow and logic dependency in standard cell placement (1995) (16)
Interconnect-Driven Floorplanning with Fast Global Wiring Planning and Optimization (2001) (16)
An efficient algorithm for performance-optimal FPGA technology mapping with retiming (1998) (15)
An area-optimality study of floorplanning (2004) (15)
Physical models and efficient algorithms for over-the-cell routing in standard cell design (1993) (15)
SuSy (2020) (15)
On Nominal Delay Minimization in LUT-Based FPGA Technology Mapping (1994) (15)
Energy-efficient computing using adaptive table lookup based on nonvolatile memories (2013) (15)
A layout modification approach to via minimization (1991) (15)
An improved algorithm for performance optimal technology mapping with retiming in LUT-based FPGA design (1996) (15)
Behavior and communication co-optimization for systems with sequential communication media (2006) (15)
Global clustering-based performance-driven circuit partitioning (2002) (15)
AIM: accelerating computational genomics through scalable and noninvasive accelerator-interposed memory (2017) (14)
Simultaneous placement with clustering and duplication (2004) (14)
A rigorous framework for convergent net weighting schemes in timing-driven placement (2009) (14)
CPU-FPGA Coscheduling for Big Data Applications (2018) (14)
Partially-dependent functional decomposition with applications in FPGA synthesis and mapping (1997) (14)
A generalized control-flow-aware pattern recognition algorithm for behavioral synthesis (2010) (14)
Multiscale Optimization in VLSI Physical Design Automation (2006) (13)
BLINK: bit-sparse LSTM inference kernel enabling efficient calcium trace extraction for neurofeedback devices (2020) (13)
EM+TV Based Reconstruction for Cone-Beam CT with Reduced Radiation (2011) (13)
Accelerating Monte Carlo based SSTA using FPGA (2010) (13)
Architecture and Compiler Optimizations for Data Bandwidth Improvement in Configurable Processors (2006) (13)
RC-NVM: Enabling Symmetric Row and Column Memory Accesses for In-memory Databases (2018) (13)
Utilizing Radio-Frequency Interconnect for a Many-DIMM DRAM System (2012) (13)
An improved graph-based FPGA technology mapping algorithm for delay optimization (1992) (13)
When HLS Meets FPGA HBM: Benchmarking and Bandwidth Optimization (2020) (13)
A new generation of C-base synthesis tool and domain-specific computing (2008) (13)
LANMC: LSTM-Assisted Non-Rigid Motion Correction on FPGA for Calcium Image Stabilization (2019) (12)
General convergent expectation maximization (EM)-type algorithms for image reconstruction (2013) (12)
Stream arbitration: Towards efficient bandwidth utilization for emerging on-chip interconnects (2013) (12)
CLINK: Compact LSTM Inference Kernel for Energy Efficient Neurofeedback Devices (2018) (12)
Fault tolerant placement and defect reconfiguration for nano-FPGAs (2008) (12)
Wiresizing with Driver Sizing for Performance and Power Optimization (1994) (12)
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning (2007) (12)
FANS: FPGA-Accelerated Near-Storage Sorting (2021) (12)
BLINK (2020) (12)
Interconnect Performance Estimation Models For Synthesis And Design Planning (1998) (12)
FPGA HLS Today: Successes, Challenges, and Opportunities (2022) (11)
Retiming-based timing analysis with an application to mincut-based global placement (2004) (11)
Domain-specific processor with 3D integration for medical image processing (2011) (11)
3D recursive Gaussian IIR on GPU and FPGAs — A case for accelerating bandwidth-bounded applications (2011) (11)
An FPGA-Based BWT Accelerator for Bzip2 Data Compression (2019) (11)
SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for Genome Sequencing (2018) (11)
Robust gate sizing via mean excess delay minimization (2008) (11)
Optimal Qubit Mapping with Simultaneous Gate Absorption (2021) (11)
Mapping for better than worst-case delays in LUT-based FPGA designs (2008) (11)
Tutorial and Survey Paper Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays (1996) (11)
RapidStream: Parallel Physical Implementation of FPGA HLS Designs (2022) (11)
Layout optimization (1997) (11)
Parallel logic level simulation of VLSI circuits (1994) (11)
Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis (2010) (11)
Constrained floorplan design for flexible blocks (1989) (11)
Behavior-level observability don't-cares and application to low-power behavioral synthesis (2009) (11)
Performance driven routing with multiple sources (1995) (11)
FPGA Implementation of EM Algorithm for 3D CT Reconstruction (2014) (10)
A scalable communication-aware compilation flow for programmable accelerators (2016) (10)
AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators (2022) (10)
Accelerating SSSP for Power-Law Graphs (2022) (10)
Investigating the effects of fine-grain three-dimensional integration on microarchitecture design (2008) (10)
Accelerating vision and navigation applications on a customizable platform (2011) (10)
Customizable Computing—From Single Chip to Datacenters (2019) (10)
The Supercomputer Supernet: A Scalable Distributed Terabit Network (1995) (10)
An analytical placer for mixed-size 3D placement (2010) (10)
Compilation and architecture support for customized vector instruction extension (2012) (10)
Serpens: a high bandwidth memory based accelerator for general-purpose sparse matrix-vector multiplication (2021) (9)
NSF Workshop on EDA: Past, Present, and Future (Part 1) (2010) (9)
Modern Circuit Placement (2008) (9)
An Optimal Performance-Driven Technology Mapping Algorithm For Lut-Based Fpgas Under Arbitrary Net-D (1993) (9)
FLASH: Fast, Parallel, and Accurate Simulator for HLS (2020) (9)
RC-NVM: Dual-Addressing Non-Volatile Memory Architecture Supporting Both Row and Column Memory Accesses (2019) (9)
Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs (2011) (9)
Throughput-oriented kernel porting onto FPGAs (2013) (9)
Thermal-Aware 3D Floorplan (2010) (9)
GRT: A Reconfigurable SDR Platform with High Performance and Usability (2014) (9)
Placement and placement driven technology mapping for FPGA synthesis (1993) (9)
Synthesis Algorithm for Application-Specific Homogeneous Processor Networks (2009) (9)
Thermal-Aware Physical Design Flow for 3-D ICs (2006) (9)
Multiband RF-interconnect for reconfigurable network-on-chip communications (2009) (9)
Depth optimal incremental mapping for field programmable gate arrays (2000) (8)
On clock routing for general cell layouts (1991) (8)
FPGA acceleration by asynchronous parallelization for simultaneous image reconstruction and segmentation based on the Mumford-Shah regularization (2015) (8)
Understanding the energy efficiency of SMT and CMP with multiclustering (2005) (8)
A 20Gb/s 79.5mW 127GHz CMOS transceiver with digitally pre-distorted PAM-4 modulation for contactless communications (2018) (8)
Evaluating Statistical Power Optimization (2010) (8)
Understanding Performance Differences of FPGAs and GPUs: (Abtract Only) (2018) (8)
Rapid Cycle-Accurate Simulator for High-Level Synthesis (2018) (8)
Efficient heuristics for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design (1997) (8)
A variation-tolerant scheduler for better than worst-case behavioral synthesis (2009) (8)
Exploiting Computation Reuse for Stencil Accelerators (2020) (8)
Overcoming Data Transfer Bottlenecks in DNN Accelerators via Layer-Conscious Memory Managment (2019) (8)
A Millimeter-Wave CMOS Transceiver With Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications (2019) (7)
Crane: Mitigating Accelerator Under-utilization Caused by Sparsity Irregularities in CNNs (2020) (7)
Theory and Algorithm for SPFD-Based Global Rewiring (2001) (7)
MOCHA: Multinode Cost Optimization in Heterogeneous Clouds with Accelerators (2021) (7)
A Distributed Clustered Architecture to Tackle Delay Variations in Datapath Synthesis (2016) (7)
Report for the NSF Workshop on Cross ‐ layer Power Optimization and Management (2012) (7)
A fast four-via multilayer MCM router (1993) (7)
Modeling and layout optimization of VLSI devices and interconnects in deep submicron design (1997) (7)
Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA (2008) (7)
Advances and Challenges in 3D Physical Design (2010) (7)
Synthesis challenges for next-generation high-performance and high-density PLDs (2000) (7)
Multilevel Circuit Placement (2003) (7)
A metric for layout-friendly microarchitecture optimization in high-level synthesis (2012) (7)
From JVM to FPGA: Bridging Abstraction Hierarchy via Optimized Deep Pipelining (2018) (7)
Maximal reduction of lookup-table based FPGAs (1992) (6)
ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architectures (2016) (6)
Pattern-Mining for Behavioral Synthesis (2011) (6)
ARACompiler: a prototyping flow and evaluation framework for accelerator-rich architectures (2015) (6)
PolySA (2018) (6)
IEEE Journal on Emerging and Selected Topics in Circuits and Systems information for authors (2018) (6)
A provable near-optimal algorithm for the channel pin assignment problem (1991) (6)
Enabling Automated FPGA Accelerator Optimization Using Graph Neural Networks (2021) (6)
Thermal-Aware 3D Placement (2010) (6)
Algorithm-Hardware Co-design for BQSR Acceleration in Genome Analysis ToolKit (2020) (6)
A new enhanced SPFD rewiring algorithm [logic IC layout] (2002) (6)
FPGA Acceleration for Simultaneous Medical Image Reconstruction and Segmentation (2014) (6)
A 125GHz transceiver in 65nm CMOS assembled with FR4 PCB antenna for contactless wave-connectors (2017) (6)
HeteroCL (2019) (6)
Energy Efficiency of Full Pipelining: A Case Study for Matrix Multiplication (2016) (6)
Utilizing RF-I and intelligent scheduling for better throughput/watt in a mobile GPU memory system (2012) (6)
Using Data Compression for Optimizing FPGA-Based Convolutional Neural Network Accelerators (2017) (6)
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, FPGA 1998, Monterey, CA, USA, February 22-24, 1998 (1998) (5)
Architecture support for custom instructions with memory operations (2013) (5)
A New Approach to Three Layer Channel Routing (1987) (5)
Fault covering problems in reconfigurable VLSI systems (1992) (5)
FCUDA-HB: Hierarchical and Scalable Bus Architecture Generation on FPGAs With the FCUDA Flow (2016) (5)
HeteroRefactor: Refactoring for Heterogeneous Computing with FPGA (2020) (5)
AutoSA (2021) (5)
Customizable Computing (2015) (5)
A new formulation of yield enhancement problems for reconfigurable chips (1988) (5)
Defect tolerance in nanodevice-based programmable interconnects: Utilization beyond avoidance (2013) (5)
Automated Accelerator Optimization Aided by Graph Neural Networks (2022) (5)
A-QED Verification of Hardware Accelerators (2020) (5)
Revisiting FPGA Acceleration of Molecular Dynamics Simulation with Dynamic Data Flow Behavior in High-Level Synthesis (2016) (5)
Dynamic weighting Monte Carlo for constrained floorplan designs in mixed signal application (2000) (5)
Architecture and synthesis for multi-cycle on-chip communication (2003) (5)
Interconnect synthesis of heterogeneous accelerators in a shared memory architecture (2015) (5)
EPEE: an efficient PCIe communication library with easy-host-integration property for FPGA accelerators (abstract only) (2014) (5)
VIA design rule consideration in multi-layer maze routing algorithms (1999) (5)
Moore's Law: Another casualty of the financial meltdown? (2009) (5)
EM+TV for Reconstruction of Cone-beam CT with Curved Detectors using GPU (2011) (5)
Better-Than-Worst-Case Design: Progress and Opportunities (2014) (5)
Technology mapping for FPGAs with nonuniform pin delays and fast interconnections (1999) (5)
SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for DNA Sequencing (2018) (5)
Improved Crosstalk Modeling with Applications to Noise Constrained Interconnect Optimization (2000) (5)
On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor (1997) (4)
OverGen: Improving FPGA Usability through Domain-specific Overlay Generation (2022) (4)
On Acceleration of Logic Synthesis Algorithms using FPGA-based Reconfigurable Coprocessors (1997) (4)
FPGA-based LSTM Acceleration for Real-Time EEG Signal Processing: (Abstract Only) (2018) (4)
Gradual relaxation techniques with applications to behavioral synthesis (2003) (4)
From design to design automation (2014) (4)
Supercomputer Supernet (SSN): a high-speed electro-optic campus and metropolitan network (1996) (4)
Matching-Based Methods for High-Performance (1993) (4)
FPGA Simulation Engine for Customized Construction of Neural Microcircuit (2013) (4)
Vlsi interconnect layout optimization (1998) (4)
CLINK (2018) (4)
On the futility of statistical power optimization (2009) (4)
Quantitative Studies of Impact of 3 D IC Design on Repeater Usage (2008) (4)
FPGA simulation engine for customized construction of neural microcircuits (2013) (4)
High efficiency VLSI implementation of an edge-directed video up-scaler using high level synthesis (2015) (4)
An 8M Polygons/s 3-D Graphics SoC With Full Hardware Geometric and Rendering Engine for Mobile Applications (2011) (4)
Impact of loop transformations on software reliability (2015) (4)
Lower-bound estimation for multi-bitwidth scheduling (2005) (4)
A High-throughput Architecture for Lossless Decompression on FPGA Designed Using HLS (Abstract Only) (2016) (4)
An E cient Approach to Multi-layer Layer Assignment with Application to Via Minimization 1 (1997) (3)
Simultaneous Buffer and Wire Sizing for Performaince and Power (1996) (3)
3D Architecture Modeling and Exploration (2006) (3)
FPGA Acceleration for Simultaneous Image Reconstruction and Segmentation based on the Mumford-Shah Regularization (Abstract Only) (2015) (3)
Advanced Routing Techniques for Nanometer IC Designs (2006) (3)
Analyzing and Modeling In-Storage Computing Workloads On EISC — An FPGA-Based System-Level Emulation Platform (2019) (3)
CPU-FPGA Co-Optimization for Big Data Applications: A Case Study of In-Memory Samtool Sorting (Abstract Only) (2017) (3)
A unified optimization framework for simultaneous gate sizing and placement under density constraints (2011) (3)
ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architecture (Abstact Only) (2016) (3)
Architecture Evaluation for FPGAs with Embedded Memory Blocks (1998) (3)
Scaling Up Physical Design: Challenges and Opportunities (2016) (3)
The Last Byte: The HLS tipping point (2009) (3)
An Integer Linear Programming Approach to General Fault Covering Problems (1990) (3)
TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-based FPGAs (2022) (3)
3 D Recursive Gaussian IIR on GPUs and FPGAs A Case Study for Accelerating Bandwidth-Bounded Applications (2011) (3)
Synthesis for high-density and high-performance fpgas (2000) (3)
FPGA Technology Mapping (2008) (3)
Dataflow Systolic Array Implementations of Matrix Decomposition Using High Level Synthesis (2019) (3)
Performance driven circuit partitioning (2000) (3)
StreamGCN: Accelerating Graph Convolutional Networks with Streaming Processing (2022) (3)
Indoor Map Construction via Mobile Crowdsensing (2018) (2)
Era of customization and specialization (2011) (2)
On the Minimum Density Interconnection Tree Problem (1994) (2)
Locality and Utilization in Placement Suboptimality (2007) (2)
Convergent Net Weighting Schemes in Hypergraph-based Optimization ∗ (2009) (2)
A cache-based bandwidth optimized motion compensation architecture for video decoder (2017) (2)
CROSSTALK NOISE CONTROL IN GRIDLESS GENERAL-AREA ROUTING (1998) (2)
HeteroHalide (2020) (2)
Impulse response analysis of carrier-modulated multiband RF-interconnect (MRFI) (2017) (2)
From Parallelization to Customization – Challenges and Opportunities (2021) (2)
LANMC (2019) (2)
A General Model for Fault Covering Problems in Reconfigurable Arrays (1989) (2)
Nosie and signal integrity in deep submicron design (panel) (1997) (2)
An Optimal Microarchitecture for Stencil Computation with Data Reuse and Fine-Grained Parallelism: (Abstract Only) (2018) (2)
Accelerator-rich architectures — from single-chip to datacenters (2014) (2)
Pilot – A Platform-Based HW / SW Synthesis System for FPSoC * (2002) (2)
A Comparative Study on the Architecture Templates for Dynamic Nested Loops (2010) (2)
Understanding Performance Gains of Accelerator-Rich Architectures (2019) (2)
Automated accelerator optimization aided by graph neural networks (2022) (2)
A Theory on Partially-Dependent Functional Decomposition with Application in LUT-based FPGA (1995) (2)
Overview of Center for Domain-Specific Computing (2011) (2)
Global SPFD Based Rewiring (2000) (2)
Customizable and High Performance Matrix Multiplication Kernel on FPGA (Abstract Only) (2015) (2)
Robust Mixed-Size Placement by Recursive Legalized Bipartitioning ⁄ (2005) (2)
Design, Implementation, and Evaluation of "FRiTrace" (2005) (2)
Cubic Packing with Various Candidates for 3D IC Design (2006) (2)
Enhanced robustness in multilevel mixed-size placement (2005) (2)
InterFS: An Interplanted Distributed File System to Improve Storage Utilization (2015) (2)
The survivability of design-specific spare placement in FPGA architectures with high defect rates (2013) (2)
Interconnect synthesis and planning for high-performance ic designs (2000) (2)
Improving GNN-based accelerator design automation with meta learning (2022) (2)
Transformations for throughput optimization in high-level synthesis (abstract only) (2014) (2)
Conclusion and Challenges (2007) (1)
Characterization and acceleration for genomic sequencing and analysis (2017) (1)
FPGA Acceleration of Probabilistic Sentential Decision Diagrams with High-Level Synthesis (2022) (1)
S2FA (2018) (1)
Democratizing Domain-Specific Computing (2022) (1)
ICCAD : U : Optimizing GPU Shared Memory Allocation in Automated Cto-CUDA Compilation (2018) (1)
A Communication-Centric Approach To Instruction Steering For Future Clustered Processors (1)
Advances and Challenges in 3D Physical Design (IPSJ Transactions on System LSI Design Methodology Vol.3) (2010) (1)
FPGA-RR: an enhanced FPGA architecture with RRAM-based reconfigurable interconnects (abstract only) (2012) (1)
Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs (2012) (1)
Novel techniques for large-scale circuit placement (2002) (1)
Logic synthesis for lookup-table based field-programmable gate arrays (1999) (1)
Domain-Specific Quantum Architecture Optimization (2022) (1)
Design and synthesis for low-power fpgas (2005) (1)
LUT-based FPGA technology mapping for reliability (abstract only) (2010) (1)
Impulse response analysis of coherent waveguide communication (2017) (1)
Minimum density interconnection trees (1993) (1)
RASP : A Performance-Driven General Logic Synthesis System for SRAM-based FPGAs (1998) (1)
System Synthesis and Automated Verification : Design Demands for IoT Devices (2016) (1)
TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical Design (2022) (1)
Live Demonstration: Real-Time Calcium Trace Extraction from Large-Field-of-View Miniscope (2021) (1)
K-Flow: A Programming and Scheduling Framework to Optimize Dataflow Execution on CPU-FPGA Platforms: (Abstract Only) (2018) (1)
Proceedings of the First International Workshop on Post Moore ' s Era Supercomputing (2016) (1)
A Versatile Systolic Array for Transposed and Dilated Convolution on FPGA (2022) (1)
AutoBridge (2021) (1)
CHARM: Composing Heterogeneous AcceleRators for Matrix Multiply on Versal ACAP Architecture (2023) (1)
Automatic Interior I/O Elimination in Systolic Array Architecture (2018) (1)
High-performance vlsi global routing (1998) (1)
CANSEE: Customized Accelerator for Neural Signal Enhancement and Extraction from the Calcium Image in Real Time (2020) (1)
SPA-GCN: Efficient and Flexible GCN Accelerator with Application for Graph Similarity Computation (2021) (1)
Chapter 13 – Technology Mapping (2008) (1)
Search for Optimal Systolic Arrays: A Comprehensive Automated Exploration Framework and Lessons Learned (2021) (1)
Modeling and optimization of vlsi interconnects (1999) (1)
D. Minimum Cost Minimum Diameter A-tree Heuristic Iii. Minimum Diameter A-tree Algorithm for Pd-msr Problem A. Review of A-tree Algorithm Performance Driven Routing with Multiple Sources (1995) (0)
Accel TLB Main Memory IOMMUMMU Core TLB MMU Core Accel Interconnect Scratchpad Accel Datapath (2017) (0)
Growing a Healthy FPGA Ecosystem (2015) (0)
HeteroRefactor (2020) (0)
Reorder Buffer Deflate Core Deflate Core Deflate Core FIFO FIFO Accelerator Function Unit FPGA Interface Unit Processor Reorder Buffer Reorder Buffer QPI + PCIe Arbiter ( Write ) FIFO Write Queue Arbiter (2018) (0)
FlexCNN: An End-to-End Framework for Composing CNN Accelerators on FPGA (2022) (0)
Parallelization, Customization and Automation (2012) (0)
The A 3 D Physical Design Flow Based on OpenAccess (0)
Fault Covers in Rectangular Arrays (1992) (0)
Are FPGAs suffering from the innovator's dilemna? (2013) (0)
Optimal Qubit Mapping with Simultaneous Gate Absorption ICCAD Special Session Paper (2021) (0)
Large-Scale Circuit Placement : Gap and Progress (2003) (0)
Lower-Bound Estimation for Multi-Bitwidth Time-Constrained Scheduling (2005) (0)
How will CAD handle billion-transistor systems? (panel) (1998) (0)
ARA simulator PARADE [ ICCAD ' 15 ] is open source Accel TLB Shared TLB Accel TLB Accel TLB Accel (2018) (0)
Automatic multidimensional memory partitioning for FPGA-based accelerators (abstract only) (2013) (0)
Bit-Level Transformation and Optimization for Hardware Synthesis of Algorithmic Descriptions (2009) (0)
Platform-based synthesis for field-programmable SOCs (2005) (0)
Multilevel routing for a higher degree of circuit integration (2006) (0)
Are we ready for system-level synthesis? [Panel II] (2005) (0)
Introduction of Indoor Map Construction (2018) (0)
Task-Level Data Model for Hardware Synthesis Based on Concurrent Collections (2012) (0)
A Fast Multila er General Area Router for hCM Designs (1992) (0)
Automatic design planning and exploration of vlsi systems (2005) (0)
TARO: Automatic Optimization for Free-Running Kernels in FPGA High-Level Synthesis (2022) (0)
Automated Generation of High-Performance Large-Scale Matrix Multiplication Accelerator on FPGA (2016) (0)
Thee Supercomputerr Supernet: Aa Scalablee Distributedd Terabitt Network (1995) (0)
Accelerator-Rich Architectures — Computing Beyond Processors (2015) (0)
A Provably Good Algorithm for k-Layer Topological Planar Routing Problems (1993) (0)
Tance and Unit Wire Resistance. 3 (1993) (0)
Efficient system-level mapping from streaming applications to FPGAs (abstract only) (2013) (0)
Smartphone-Based Indoor Map Construction (2018) (0)
Enhancing Placement with Multilevel Techniques (2008) (0)
Resolving implicit barrier synchronizations in FPGA HLS (abstract only) (2011) (0)
Session details: Synthesis, Verification and Test (2002) (0)
Client RM AM NM NM Container Container Job submission Note status Application status Resource request (2016) (0)
Fault Covers in Heterogeneous and General Arrays (1992) (0)
Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs (2011) (0)
Re-form : FPGA-powered true codesign flow for high-performance computing in the post-Moore era (2016) (0)
Qubit Mapping for Reconfigurable Atom Arrays (2022) (0)
General Formulation of Fault Covering Problems (1992) (0)
5 Conclusions and Directions for Future Work 4 Experimental Results (1998) (0)
Placement and design planning for three-dimensional integrated circuits (2011) (0)
From milliwatts to megawatts : System level power challenge (2009) (0)
Minimum Density Interconneciton Trees (1993) (0)
Layout optimization and planning in deep sub-micron vlsi designs (2002) (0)
Host FPGA Disk Host Fetch Data FPGA Return Result Host O ffl oad Data FPGA Return Result FPGA (2018) (0)
State of the Journal (2016) (0)
PYXIS: An Open-Source Performance Dataset Of Sparse Accelerators (2021) (0)
On the Construction of Optimal or Near-optimal Rectilinear Steiner Arborescence (1994) (0)
for Delay Optimization (1992) (0)
Energy-Efficient Computing Using Adaptive Table Lookup (2013) (0)
Enhanced SPFD Rewiring on Improving Rewiring Ability (2002) (0)
4 Near-optimal Routing Trees (1993) (0)
RapidStream 2.0: Automated Parallel Implementation of Latency Insensitive FPGA Designs Through Partial Reconfiguration (2023) (0)
Session details: Session 9C: Advances in placement (2001) (0)
Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition (2021) (0)
Coupling Of Synthesis And Layout: Challenges And Solutions (1998) (0)
"High-level synthesis and beyond - From datacenters to IoTs" (2015) (0)
Authors' Draft: Ieee Transactions on Computer-aided Design of Integrated Circuits and Systems, 2001 Pseudo Pin Assignment with Crosstalk Noise Control (2001) (0)
Incremental Indoor Map Construction with a Single User (2018) (0)
Defect recovery in nanodevice-based programmable interconnects (abstract only) (2013) (0)
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999, San Diego, California, USA, August 16-17, 1999 (1999) (0)
Physical synthesis techniques for fpga optimization (2006) (0)
Session details: Evening panel: are FPGAs suffering from the innovator's dilemna? (2013) (0)
2 Locality and Utilization in Placement Suboptimality (0)
Interconnect oriented microarchitectures and resource binding in behavioral synthesis (2006) (0)
Large-Scale Global Placement (2018) (0)
Session details: Physical design (2008) (0)
NSF Workshop on Micro/Nano Circuits and Systems Design and Design Automation: Challenges and Opportunities (2021) (0)
SRC 1091.001 Final Deliverable Report for Oct 2006: Highly Scalable Multilevel Placement Algorithm for Mixed-size with Complex Constraints (2006) (0)
Revisiting bitwidth optimizations (2009) (0)
A New Approach to Three- or (1988) (0)
Session details: New CAD techniques and methods (2005) (0)
Multilevel VLSI Routing (2003) (0)
CLinput Queue CLoutput Queue Compute DMALoad Load Queue DMAStore Store Queue ... Pack Send Queue Send Unpack Recv Queue Recv Input Java Objects Output Java Objects Pack Send Queue Send Unpack Recv Queue Recv (2018) (0)
4.1 Comparing Cost and Radius (2007) (0)
Unified synthesis techniques for high performance fpga designs (2005) (0)
Multi-layer general area gridless detailed routing (2001) (0)
Compiler transformations for electronic system level synthesis (2009) (0)
Are we ready for system-level synthesis? (2005) (0)
Session details: Breaking out of EDA: how to apply EDA techniques to broader applications (2012) (0)
TGPA (2018) (0)
Better-Than-Worst-Case Design: Progress and Opportunities (2014) (0)
Logic synthesis for nanometer ic technologies (2010) (0)
Session details: Floorplanning (2004) (0)
Large Scale Circuit Partitioning With Loose/Stable Net Removal And Signal Flow Based Hierarchical Cl (1997) (0)
Understanding Performance Gains of Accelerator-Rich Architectures ( Invited Paper ) (2019) (0)
2019 DAC Roundtable (2020) (0)
Session details: Heterogeneous Computing in Data Centers for Energy Efficiency (2016) (0)
Editorial: Special issue on 3D integrated circuits and microarchitectures (2008) (0)
3D Physical Design (2011) (0)
Performance-driven fpga synthesis for sequential circuits (1999) (0)
Multi-level coarse placement for physical hierarchy generation (2003) (0)
Automating customized computing (2014) (0)
Further Studies on Placement Optimality (0)
Fast Optimal Algorithms for the Minimum Rectilinear SteinerArborescence (1997) (0)
Modeling and Mapping for Customizable Domain-Specific Computing (2010) (0)
Transformation from ad hoc EDA to algorithmic EDA (2012) (0)
Synthesis techniques for application-specific processor-based design (2007) (0)
Physical Synthesis for Power under Process Variation (2006) (0)
A Go-to-FPGA Compilation Framework for Streaming Applications (2017) (0)
Serpens (2022) (0)
HMLib: Efficient Data Transfer for HLS Using Host Memory (2023) (0)
MOCHA (2021) (0)
RapidStream (2022) (0)
Session details: Machine Learning (2017) (0)
Session details: Session 10: Regular Circuit Fabrics (invited) (2003) (0)
Recut: a Concurrent Framework for Sparse Reconstruction of Neuronal Morphology (2021) (0)
Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver (2022) (0)
Challenges and Solutions for Nanometer SOC Designs (2004) (0)
The Impact Of Compiler Optimizations On High-Level Synthesis (2012) (0)
Comparison Results on Fu and Register Counts Accurately Handle Don't-care Conditions in High-level Designs and Application for Reducing Initialized Registers Chou Et Al.: Accurately Handle Don't-care Conditions in High-level Designs and Application for Reducing Initialized Registers 647 (0)
D. Minimum Cost Minimum Diameter A-tree Heuristic Iii. Minimum Diameter A-tree Algorithm for Pd-msr Problem A. Review of A-tree Algorithm Performance Driven Routing with Multiple Sources (1995) (0)

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