Jean-Loup Baer | Academic Influence

Jean-Loup Baer's AcademicInfluence.com Rankings

Jean-Loup Baer

Engineering

#2862

World Rank

#3851

Historical Rank

Electrical Engineering

#951

World Rank

#1026

Historical Rank

engineering Degrees

Jean-Loup Baer

Computer Science

#4692

World Rank

#4953

Historical Rank

Computer Architecture

#54

World Rank

#56

Historical Rank

Database

#7706

World Rank

#8009

Historical Rank

computer-science Degrees

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Engineering
Computer Science

Jean-Loup Baer's Degrees

PhD Computer Science University of California, Berkeley
Masters Electrical Engineering Stanford University
Bachelors Electrical Engineering Stanford University

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Why Is Jean-Loup Baer Influential?

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According to Wikipedia, Jean-Loup Baer is a computer scientist and Professor Emeritus at the University of Washington. Biography Jean-Loup Baer received the Diplome d'Ingénieur in Electrical Engineering and the Doctorat 3e cycle in Computer Science from the University of Grenoble and the Ph.D. from UCLA in 1968 under the supervision of Gerald Estrin.

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Jean-Loup Baer's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Cache coherence protocols: evaluation using a multiprocessor simulation model (1986) (666)
Effective Hardware Based Data Prefetching for High-Performance Processors (1995) (552)
An effective on-chip preloading scheme to reduce data access penalty (1991) (463)
Reducing memory latency via non-blocking and prefetching caches (1992) (261)
On the inclusion properties for multi-level cache hierarchies (1988) (244)
A performance study of software and hardware data prefetching schemes (1994) (241)
An economical solution to the cache coherence problem (1984) (150)
Modified LRU policies for improving second-level cache behavior (2000) (148)
A Survey of Some Theoretical Aspects of Multiprocessing (1973) (146)
Execution characteristics of desktop applications on Windows NT (1998) (144)
Computer systems architecture (1980) (126)
Organization And Performance Of A Two-level Virtual-real Cache Hierarchy (1989) (109)
The structure and performance of interpreters (1996) (107)
Efficient trace-driven simulation methods for cache performance analysis (1991) (81)
Characterizing processor architectures for programmable network interfaces (2000) (77)
A Performance Study of Memory Consistency Models (1992) (71)
A Timestamp-based Cache Coherence Scheme (1989) (68)
Design and Analysis of a Scalable Cache Coherence Scheme Based on Clocks and Timestamps (1992) (63)
Dynamic Improvement of Locality in Virtual Memory Systems (1976) (62)
Characterizing processor architectures for programmable network interfaces (2000) (60)
Don't say yes when you want to say no (1981) (54)
Efficient trace-driven simulation method for cache performance analysis (1990) (46)
Model, Design, and Evaluation of a Compiler for a Parallel Processing Environment (1977) (46)
Compilation of arithmetic expressions for parallel computations (1968) (46)
Multiprocessing Systems (1976) (44)
Introducing Memory Into The Switch Elements Of Multiprocessor Interconnection Networks (1989) (44)
A comparison of tree-balancing algorithms (1977) (44)
Don't Say Yes When You Want to Say No: How Assertiveness Training Can Change Your Life (1975) (42)
A Modeling Framework for Network Processor Systems (2003) (40)
Microprocessor Architecture: From Simple Pipelines to Chip Multiprocessors (2009) (39)
Multilevel Cache Hierarchies: Organizations, Protocols, and Performance (1989) (35)
Architectural Choices for Multi-level Cache Hierarchies (1987) (34)
Conservative parallel simulation for systems with no lookahead prediction (1990) (31)
Extending the Memory Hierarchy into Multiprocessor Interconnection Networks: A Performance Analysis (1989) (29)
Pursuing the performance potential of dynamic cache line sizes (1999) (28)
On the Minimization of the Width of the Control Memory of Microprogrammed Processors (1979) (28)
Legality and Other Properties of Graph Models of Computations (1970) (27)
Proceedings of the 39th Annual International Symposium on Computer Architecture (1983) (27)
Two techniques for improving performance on bus-based multiprocessors (1995) (26)
Workloads for Programmable Network Interfaces (2000) (26)
On the use of trace sampling for architectural studies of desktop applications (1998) (25)
Instruction cache fetch policies for speculative execution (1995) (25)
Memory hierarchy design for a multiprocessor look-up engine (2003) (23)
The I/O Performance of Multiway Mergesort and Tag Sort (1985) (23)
Worst-Case Execution Time Estimation for Hardware-Assisted Multithreaded Processors (2004) (23)
A Performance Comparison of Directory-based and Timestamp-based Cache Coherence Schemes (1990) (22)
Mutual exclusion (2003) (19)
Reducing startup latency in web and desktop applications (1999) (18)
How to be an assertive, not aggressive, woman in life, in love, and on the job : a total guide to self-assertiveness (1976) (17)
Improving Quicksort Performance with a Codewort Data Structure (1989) (16)
Cost-effective compiler directed memory prefetching and bypassing (2002) (16)
On the Performance of Multithreaded Architectures for Network Processors (2000) (16)
Graph models of computations in computer systems (1968) (15)
A performance evaluation of cluster architectures (1997) (14)
Trace Sampling for Desktop Applications on Windows NT (2000) (14)
Bounds for Maxium Parallelism in a Bilogic Graph Model of Computations (1969) (13)
Multilevel cache hierarchies (1989) (11)
On the use and performance of explicit communication primitives in cache-coherent multiprocessor systems (1997) (9)
A multi-level hierarchical cache coherence protocol for multiprocessors (1993) (9)
Binary Search in a Multiprocessing Environment (1983) (8)
Measurement and Improvement of Program Behavior under Paging Systems (1972) (8)
The two-step commitment protocol: Modeling, specification and proof methodology (1981) (8)
An efficient caching support for critical sections in large-scale shared-memory multiprocessors (1990) (7)
Memory hierarchy management schemes in large-scale shared memory multiprocessors (1989) (7)
Modelling Architectural Features with Petri Nets (1986) (7)
A comparative study of conservative and optimistic trace-driven simulations (1995) (7)
2K Papers on Caches by Y2K: Do We Need More? (2000) (7)
Models for the design, simulation, and performance of distributed-function architecture (1974) (6)
Improving performance of bus-based multiprocessors (1995) (5)
The Impact of Timeliness for Hardware-based Prefetching from Main Memory (1997) (5)
On the inclusion properties for multi-level cache hierarchies (1988) (4)
A Performance Evaluation of Cluster-Based Architectures (1997) (4)
Scaling shared-bus multiprocessors with multiple buses and shared caches: a performance study (1992) (4)
Cache coherence in MIMD systems: a Petri net model for a minimal state solution (1989) (4)
A notation for describing multiple views of VLSI circuits (1988) (4)
A model of interference in a shared resource multiprocessor (1976) (4)
On Synchronization Patterns in Parallel Programs (1991) (3)
Workload Characterization: Methodology and Case Studies. Based on the First Workshop on Workload Characterization (1998) (3)
On the Performance Potential of Dynamic Cache Line Sizes (1999) (3)
The second wife : how to live happily with a man who has been married before (1972) (2)
A Parallel Trace-driven Simulator: Implementation and Performance (1994) (2)
Software control and program design issues for alterable architectures (1978) (2)
Optimizing Software Cache-coherent Cluster Architectures (1998) (2)
Query costs in HB(1) trees versus 2–3 trees (1981) (2)
On the Efficiency of Some List Marketing Algorithms (1977) (2)
On the Performance of Interleaved Memories with Non-Uniform Access Probabilities (1983) (2)
Parallel Tag-Distribution Sort (1985) (2)
Software versus hardware coherence: performance versus cost (1994) (2)
An Evaluation of Hardware and Software Data Prefetching (1994) (2)
Computer Architecture (1984) (1)
Software versus Hardware Coherence: Performance versus Cos (1994) (1)
Trends in High-Performance Computer Architecture (1995) (1)
The self-chosen : "our crowd" is dead, long live our crowd (1982) (1)
Simulation of Large Parallel Systems: Modelling of Tasks (1977) (1)
Extending memory hierarchy into multiprocessor interconnection networks (1988) (1)
Modelling and scheduling of computer programs for parallel processing systems (1968) (1)
On the E ectiveness of Code Reordering Algorithms for theAlpha and IA32 Architectures (1997) (1)
On Program Placement in a Directly Executable Hierarchy of Memories (1974) (1)
Optimistic Trace-driven Simulation (1994) (1)
TRANSACTIONS ON SOFTWAREENGINEERING: Carefully refereed, archival papersonall aspectsofthespecification, development, management, test, maintenance, anddocumentation of (1984) (0)
Parameter Estimation UsingMicroprocessors and Adaptive RandomSearch Optimization (1984) (0)
Extendable Vehicular Camouflage Paulin (1974) (0)
The Formal Definition of Semantics by String Automata (1975) (0)
On the Performance of a Bus-based Multiprocessor Cluster Architecture Craig Anderson and Jean-Loup Baer Department of Computer Science and Engineering (1995) (0)
Proceedings of the 23rd Annual International Symposium on Computer Architecture, Philadelphia, PA, USA, May 22-24, 1996 (1996) (0)
8. Conclusion Availability 7.3. Block Tour Information 7.4. Block Reuse Information (1998) (0)
CONFERENCE DIGESTS ANDPROCEEDINGS: Records ofmany conferences, symposia, andworkshops, including theuseful Digests fortheSociety-sponsored TRANSACTIONSON COMPtJTPTRS: Carefully refereed, archival papers inallfields ofcomputation, information processing, applications, andcomputer systems research and (1983) (0)
Future directions of parallel computer architectures (1985) (0)
Microprocessor Architecture: Bibliography (2009) (0)
Etude critique et données de compilation du langage Cobol. (Study critical and compilation data of the language COBOL) (1963) (0)
Embedded-Java takes off with X86 architecture (1997) (0)
Microprocessor Architecture: Multiprocessors (2009) (0)
Network processor memory hierarchy designs for ip packet classification (2005) (0)
A Hybrid Framework for Network Processor System Analysis (2002) (0)
A Packet Classification Algorithm for Multiple Look-up Engines (0)
Microprocessor Architecture: Front-End: Branch Prediction, Instruction Fetching, and Register Renaming (2009) (0)
TRANSACTIONS ONPATTERNANALYSIS ANDMACHINEINTELLIGENCE: Carefully refereed, archival papers onall aspects ofpattern recognition, image processing, artificial intelligence, and their applications. Published bimonthly. (1985) (0)
On ProgramPlacement ina Directly Executable Hierarchy ofMemories (1974) (0)
Microprocessor Architecture: Back-End: Instruction Scheduling, Memory Access Instructions, and Clusters (2009) (0)
TRANSACTIONS ONCOMPUTERS: Carefully refereed, archival papers onall fields of computation, information processing, applications, andcomputer systems research anddesign. Published monthly. TRANSACTIONS ONSOFTWAREENGINEERING: Carefully refereed, archival papers onall aspects ofthespecification, develo (1983) (0)
Reducing Startup Latency in Web and Desktop (1999) (0)
Execution characteristics and optimization of modern commercial applications (1999) (0)
Microprocessor Architecture: Multithreading and (Chip) Multiprocessing (2009) (0)
Techniques utilizing memory reference characteristics for improved performance (2002) (0)
7. Validation 6. User Interface 5. Timing and the Global Event Ordering Problem 4. Implementation Platforms Parallel Simulation Instruction-driven Simulation Execution-driven Simulation (1994) (0)
Cache-Based Data Distribution Constrained Scheduling (1994) (0)
Proceedings of the 1977 International Conference on Parallel Processing : papers presented on August 23-26, 1977 (1977) (0)
Microprocessor Architecture: The Cache Hierarchy (2009) (0)

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