Jonathan Scott Rose
#154,689
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Jonathan Scott Roseengineering Degrees
Engineering
#6408
World Rank
#7736
Historical Rank
Electrical Engineering
#1904
World Rank
#2006
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Engineering
Jonathan Scott Rose's Degrees
- PhD Electrical Engineering Stanford University
- Masters Electrical Engineering Stanford University
- Bachelors Electrical Engineering Stanford University
Why Is Jonathan Scott Rose Influential?
(Suggest an Edit or Addition)Jonathan Scott Rose's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- Measuring the Gap Between FPGAs and ASICs (2006) (1354)
- Architecture and CAD for Deep-Submicron FPGAS (1999) (1322)
- VPR: A new packing, placement and routing tool for FPGA research (1997) (1157)
- FPGA Architecture: Survey and Challenges (2008) (528)
- FPGA and CPLD Architectures: A Tutorial (1996) (379)
- Architecture of field-programmable gate arrays (1993) (352)
- VTR 7.0: Next Generation Architecture and CAD System for FPGAs (2014) (326)
- Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency (1990) (303)
- The VTR project: architecture and CAD for FPGAs from verilog to routing (2012) (289)
- Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density (1999) (279)
- Timing-driven placement for FPGAs (2000) (271)
- Chortle-crf: fast technology mapping for lookup table-based FPGAs (1991) (270)
- Flexibility of interconnection structures for field-programmable gate arrays (1991) (255)
- VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling (2011) (224)
- The Stratix II logic and routing architecture (2005) (222)
- Architectures and algorithms for field-programmable gate arrays with embedded memory (1997) (193)
- A detailed router for field-programmable gate arrays (1990) (181)
- Chortle: a technology mapping program for lookup table-based field programmable gate arrays (1990) (172)
- FPGA routing architecture: segmentation and buffering to optimize speed and density (1999) (166)
- Next-generation acceleration and code optimization for light transport in turbid media using GPUs (2010) (165)
- Cluster-based logic blocks for FPGAs: area-efficiency vs. input sharing and size (1997) (165)
- The stratixπ routing and logic architecture (2003) (156)
- Video-rate stereo depth measurement on programmable hardware (2003) (145)
- A fast routability-driven router for FPGAs (1998) (138)
- Technology mapping of lookup table-based FPGAs for performance (1991) (136)
- VESPA: portable, scalable, and flexible FPGA-based vector processors (2008) (129)
- Comparing FPGA vs. custom cmos and the impact on processor microarchitecture (2011) (123)
- Field-Programmable Gate Arrays (1992) (118)
- Trading quality for compile time: ultra-fast placement for FPGAs (1999) (111)
- The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout (1999) (106)
- The effect of logic block architecture on FPGA performance (1992) (105)
- The microarchitecture of FPGA-based soft processors (2005) (104)
- The design of an SRAM-based field-programmable gate array. I. Architecture (1999) (100)
- How Much Logic Should Go in an FPGA Logic Block? (1998) (100)
- Application-specific customization of soft processor microarchitecture (2006) (89)
- VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling (2009) (88)
- Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect (2011) (83)
- LocusRoute: a parallel global router for standard cells (1988) (83)
- Directional bias and non-uniformity in FPGA global routing architectures (1996) (81)
- Exploration and Customization of FPGA-Based Soft Processors (2007) (80)
- Parallel global routing for standard cells (1990) (77)
- Parallel standard cell placement algorithms with quality equivalent to simulated annealing (1988) (76)
- Area and delay trade-offs in the circuit and architecture design of FPGAs (2008) (72)
- A stochastic model to predict the routability of field-programmable gate arrays (1993) (71)
- Speed and area tradeoffs in cluster-based FPGA architectures (2000) (68)
- Temperature measurement and equilibrium dynamics of simulated annealing placements (1990) (65)
- Characterization and parameterized random generation of digital circuits (1996) (63)
- Portable and scalable FPGA-based acceleration of a direct linear system solver (2008) (61)
- The Design of an SRAM-Based Field-Programmable Gate Array — Part I : Architecture (1999) (57)
- Design, layout and verification of an FPGA using automated tools (2005) (55)
- Synthesis methods for field programmable gate arrays (1993) (54)
- Circuit design, transistor sizing and wire layout of FPGA interconnect (1999) (54)
- Using bus-based connections to improve field-programmable gate-array density for implementing datapath circuits (2006) (54)
- The Transmogrifier-2: a 1 million gate rapid prototyping system (1997) (52)
- Characterization and parameterized generation of synthetic combinational benchmark circuits (1998) (51)
- Reconfigurable hardware implementation of a phase-correlation stereoalgorithm (2006) (51)
- Automatic generation of FPGA routing architectures from high-level descriptions (2000) (51)
- Modeling routing demand for early-stage FPGA architecture development (2008) (49)
- Quantifying and Exploring the Gap Between FPGAs and ASICs (2009) (46)
- Architecture of Centralized Field-Configurable Memory (1995) (45)
- Patient Willingness to Consent to Mobile Phone Data Collection for Mental Health Apps: Structured Questionnaire (2018) (44)
- The Transmogrifier-2: a 1 million gate rapid-prototyping system (1998) (44)
- Optimization of field-programmable gate array logic block architecture for speed (1991) (43)
- A Verilog RTL synthesis tool for heterogeneous FPGAs (2005) (43)
- Architectural and physical design challenges for one-million gate FPGAs and beyond (1997) (43)
- A high-speed ray tracing engine built on a field-programmable system (2003) (42)
- Automatic generation of synthetic sequential benchmark circuits (2002) (42)
- Synthesis method for field programmable gate arrays (1993) (42)
- Automatic transistor and physical design of FPGA tiles from an architectural specification (2003) (42)
- Definition And Solution Of The Memory Packing Problem For Field-programmable Systems (1994) (40)
- The effect of logic block complexity on area of programmable gate arrays (1989) (40)
- Advantages of heterogeneous logic block architecture for FPGAs (1993) (40)
- Fine-grain performance scaling of soft vector processors (2009) (39)
- An SRAM-programmable field-configurable memory (1995) (38)
- Enhancing the area-efficiency of FPGAs with hard circuits using shadow clusters (2006) (38)
- A hybrid complete-graph partial-crossbar routing architecture for multi-FPGA systems (1998) (37)
- Mixing buffers and pass transistors in FPGA routing architectures (2001) (36)
- Effect of the prefabricated routing track distribution on FPGA area-efficiency (1998) (35)
- Portable, Flexible, and Scalable Soft Vector Processors (2012) (34)
- A parameterized automatic cache generator for FPGAs (2003) (34)
- Synthetic circuit generation using clustering and iteration (2003) (32)
- Generation of synthetic sequential benchmark circuits (1997) (31)
- Automated transistor sizing for FPGA architecture exploration (2008) (31)
- The effect of switch box flexibility on routability of field programmable gate arrays (1990) (29)
- Hybrid Eye-Tracking on a Smartphone with CNN Feature Extraction and an Infrared 3D Model (2020) (28)
- The memory/logic interface in FPGAs with large embedded memory arrays (1999) (28)
- FPGA Architecture (2008) (28)
- Exploring Area and Delay Tradeoffs in FPGAs With Architecture and Automated Transistor Design (2011) (27)
- FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy (2009) (27)
- On Hard Adders and Carry Chains in FPGAs (2014) (26)
- Partial Reconfiguration of FPGA Mapped Designs with Applications to Fault Tolerance and Yield Enhancement (1997) (25)
- GPU-accelerated Monte Carlo simulation for photodynamic therapy treatment planning (2009) (25)
- Architecture of datapath-oriented coarse-grain logic and routing for FPGAs (2003) (24)
- Technology Mapping for Heterogeneous FPGAs (1994) (23)
- A novel and efficient routing architecture for multi-FPGA systems (2000) (23)
- Hard vs. soft: the central question of pre-fabricated silicon (2004) (22)
- A new, fast algorithm for detecting protein coevolution using maximum compatible cliques (2011) (21)
- Towards interconnect-adaptive packing for FPGAs (2014) (21)
- The supersmall soft processor (2010) (21)
- TEMPT: technology mapping for the exploration of FPGA architectures with hard-wired connections (1992) (20)
- Improving FPGA routing architectures using architecture and CAD interactions (1992) (20)
- Enhancing the Area Efficiency of FPGAs With Hard Circuits Using Shadow Clusters (2010) (19)
- Data parallel FPGA workloads: Software versus hardware (2009) (19)
- An energy-efficient, fast FPGA hardware architecture for OpenCV-Compatible object detection (2012) (18)
- The Relationship Between Smartphone-Recorded Environmental Audio and Symptomatology of Anxiety and Depression: Exploratory Study (2020) (16)
- The Transmogrifier-4: an FPGA-based hardware development system with multi-gigabyte memory capacity and high host and memory bandwidth (2005) (16)
- Using multi-bit logic blocks and automated packing to improve field-programmable gate array density for implementing datapath circuits (2004) (16)
- Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural Design (2014) (16)
- Mapping multiplexers onto hard multipliers in FPGAs (2005) (15)
- Memory/logic interconnect flexibility in FPGAs with large embedded memory arrays (1996) (15)
- Nearest neighbour interconnect architecture in deep submicron FPGAs (2002) (15)
- Memory-to-memory connection structures in FPGAs with embedded memory arrays (1997) (14)
- Synthesizing datapath circuits for FPGAs with emphasis on area minimization (2002) (14)
- Field-programmable gate array architectures and algorithms optimized for implementing datapath circuits (2004) (13)
- Experimental Ev alua-tion of Mesh and Partial Crossbar Routing Architec-tures for Multi-FPGA Systems (1997) (12)
- On Biased and Non-Uniform Global Routing Architectures and CAD Tools for FPGAs (1996) (12)
- Using Architectural "Families" to Increase FPGA Speed and Density (1995) (12)
- The Effect of Fixed I/O Pin Positioning on The Routability and Speed of FPGAs (1995) (12)
- Automated Screening for Social Anxiety, Generalized Anxiety, and Depression From Objective Smartphone-Collected Data: Cross-sectional Study (2021) (12)
- Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits (2005) (11)
- Panel: (When) Will FPGAs Kill ASICs? (2001) (11)
- Architecting Hard Crossbars on FPGAs and Increasing their Area Efficiency with Shadow Clusters (2007) (11)
- A Detailed Router for Field-Programmable Gate (1992) (10)
- Structural analysis and generation of synthetic digital circuits with memory (2001) (10)
- Temperature measurement of simulated annealing placements (1988) (9)
- Hardware Accelerated Novel Protein Identification (2004) (9)
- A high-speed FPGA using programmable mini-tiles (1993) (9)
- Efficient methods for out-of-order load/store execution for high-performance soft processors (2013) (8)
- Advantages of Heterogeneous Logic Block Architectures for (1993) (8)
- Taking the tester out of the SDMT: A proof of concept fully automated approach to assessing processing speed in people with MS (2018) (8)
- On the difficulty of pin-to-wire routing in FPGAs (2012) (8)
- SmartEye: An Accurate Infrared Eye Tracking System for Smartphones (2018) (8)
- Smartphone-Detected Ambient Speech and Self-Reported Measures of Anxiety and Depression: Exploratory Observational Study (2021) (8)
- High Performance Instruction Scheduling Circuits for Out-of-Order Soft Processors (2016) (8)
- Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory System (2016) (7)
- Real-time, frame-rate face detection on a configurable hardware system (poster abstract) (2000) (7)
- The parallel decomposition and implementation of an integrated circuit global router (1988) (7)
- Introduction to FPGAs (1992) (7)
- Optimizing FPGA Logic Block Architectures for Arithmetic (2020) (7)
- Fine-Grained Interconnect Synthesis (2016) (7)
- The Nineteenth-Century Information Revolution (1999) (7)
- EVE: a CAD tool for manual placement and pipelining assistance of FPGA circuits (2002) (6)
- (When) will FPGAs kill ASICs? (panel session) (2001) (6)
- Routing for FPGAs (1992) (5)
- Measuring and utilizing the correlation between signal connectivity and signal positioning for FPGAs containing multi-bit building blocks (2005) (5)
- “Vespa” (2018) (4)
- Temperature dependence and pressure dependence of the vibrational properties of corannulene (2008) (4)
- High-Performance Instruction Scheduling Circuits for Superscalar Out-of-Order Soft Processors (2018) (4)
- Detection and Correspondence Matching of Corneal Reflections for Eye Tracking Using Deep Learning (2021) (4)
- Equivalence classes of clone circuits for physical-design benchmarking (1999) (4)
- Energy efficient object detection on the mobile GP-GPU (2017) (4)
- Applications of clone circuits to issues in physical-design (1999) (4)
- Synthesis methods for field programmable gate arrays : Field programmable gate arrays (1993) (4)
- Architecture of field-programmable gate arrays : Field programmable gate arrays (1993) (4)
- Automatic FPGA system and interconnect construction with multicast and customizable topology (2015) (4)
- FERMTOR: A Tunable Multiprocessor Architecture (1985) (4)
- Routing and Logic Architecture (2003) (3)
- Acoustic and Linguistic Features of Impromptu Speech and Their Association With Anxiety: Validation Study (2022) (3)
- Synchronization Constraints for Interconnect Synthesis (2017) (3)
- Improving Memory System Performance for Soft Vector Processors (2008) (3)
- Film Condensation of Steam on a HorizontalWire-Wrapped Tube (2002) (3)
- Hardwired-Clusters Partial-Crossbar: A Hierarchical Routing Architecture for Multi-FPGA Systems (1999) (3)
- Report on FPGA '94: the second ACM international workshop on Field-Programmable Gate Arrays (1994) (2)
- Performance characterization of mobile GP-GPUs (2015) (2)
- Screening for Generalized Anxiety Disorder From Acoustic and Linguistic Features of Impromptu Speech: Prediction Model Evaluation Study (2022) (2)
- A synthesis oriented omniscient manual editor (2004) (2)
- CAD Tools: Packing and Placement (1999) (2)
- The Design of an SRAM-BasedField-Programmable Gate Array , Part I : (2007) (2)
- Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays (1995) (1)
- Fine-Grained Interconnect Synthesis (2015) (1)
- Invited Keynote 1: Closing the gap between FPGAs and ASICs (2006) (1)
- Detailed Routing Architecture (1999) (1)
- Routing Tools and Routing Architecture Generation (1999) (1)
- Flexibility of FPGA Routing Architectures (1992) (1)
- Technology Mapping for FPGAs (1992) (1)
- Automatic Topology Optimization for FPGA Interconnect Synthesis (2018) (1)
- Cluster-Based Logic Blocks (1999) (1)
- Logic emulation (panel): a niche or a future standard for design verification? (1993) (1)
- Logic Block Architecture (1992) (1)
- Measuring the Gap (2010) (0)
- Architecture and Circuit-Level Design of anSRAM-Based Field-Programmable Gate (1999) (0)
- Logic Emulation: A Niche or a Future Standard for Design Verification? (Panel Abstract). (1993) (0)
- SPREE : Microarchitectural Exploration on FPGAs (0)
- ModelingRoutingDemandforEarly-StageFPGA ArchitectureDevelopment (2008) (0)
- The Relationship Between Smartphone-Recorded Environmental Audio and Symptomatology of Anxiety and Depression: Exploratory Study (Preprint) (2020) (0)
- Session details: Workshop (2001) (0)
- A Theoretical Model for FPGA Routing (1992) (0)
- Session details: Technical Session 3: Architecture 1 (2015) (0)
- 8−input, 1−output Memory Inputs Output Inputs Output Figure 3: Mapping a Circuit to a 8-input, 1-output Memory Block (0)
- Session details: Technical Session 5: Architecture and Tools (2016) (0)
- Workshop reports: FPGA'92: First International ACM/SIGDA Workshop on Field-Programmable Gate Arrays (1993) (0)
- Background and Previous Work (1999) (0)
- Structural analysis and generation of synthetic digital circuits with memory : Reconfigurable and Adaptive VLSI Systems (2001) (0)
- Will the Field-Programmable Gata Array Replace the Mask-Programmable Gate Array? (Panel Abstract) (1991) (0)
- Faster coevolution detection of proteins using maximum similar cliques (2010) (0)
- Global Routing Architecture (1999) (0)
- Navigating the Gap Using Architecture and Process Technology Scaling (2010) (0)
- The evolution of architecture exploration of programmable devices (2009) (0)
- Report on FPGA '95: the third ACM international symposium on field-programmable gate arrays (1995) (0)
- The Parallel Decomposition and Implementationo TIC N 4 of an Integrated Circuit Global Router ELECTEI (0)
- Panel: Attack of the killer gate arrays (2003) (0)
- Smartphone-Detected Ambient Speech and Self-Reported Measures of Anxiety and Depression: Exploratory Observational Study (Preprint) (2020) (0)
- Automated Screening for Social Anxiety, Generalized Anxiety, and Depression From Objective Smartphone-Collected Data: Cross-sectional Study (Preprint) (0)
- Portable, Flexible, and Scalable Soft (2012) (0)
- Navigating the Gap using Transistor Sizing (2010) (0)
- Automated Transistor Sizing for FPGAs (2010) (0)
- Predicting Generalized Anxiety Disorder From Impromptu Speech Transcripts Using Context-Aware Transformer-Based Neural Networks: Model Evaluation Study (2022) (0)
- Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays (1996) (0)
- Transistor grouping and metal layer trade-offs in automatic tile layout of FPGAs (2004) (0)
- EFFECT OF THERMAL TONDUCTTyTTY OF TUBE MATERIAL ON CONDENSATION HEAT TRANSFER TOR INTEGRAL-PIN TUBES (1994) (0)
- Trading Quality f or Compile Time : Ultra-F ast Placement f or FPGAs (0)
- Constraints from hell; how to tell makes a good FPGA (panel) (1998) (0)
- Session details: Advances in FPGA CAD (2005) (0)
- The role of FPGAs in a converged future with heterogeneous programmable processors: pre-conference workshop (2011) (0)
- Soft vector processors vs FPGA custom hardware: measuring and reducing the gap (2009) (0)
- Commercially Available FPGAs (1992) (0)
- Session details: Physical design (2014) (0)
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