John Kim
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Engineering Computer Science
John Kim's Degrees
- PhD Computer Science Stanford University
- Masters Electrical Engineering Stanford University
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(Suggest an Edit or Addition)John Kim's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- Technology-Driven, Highly-Scalable Dragonfly Topology (2008) (630)
- A detailed and flexible cycle-accurate Network-on-Chip simulator (2013) (609)
- Flattened butterfly: a cost-efficient topology for high-radix networks (2007) (460)
- Flattened Butterfly Topology for On-Chip Networks (2007) (445)
- Firefly: illuminating future network-on-chip with nanophotonics (2009) (417)
- FlexiShare: Channel sharing for an energy-efficient nanophotonic crossbar (2010) (196)
- The BlackWidow High-Radix Clos Network (2006) (190)
- Microarchitecture of a high radix router (2005) (188)
- Low-cost router microarchitecture for on-chip networks (2009) (171)
- Achieving predictable performance through better memory controller placement in many-core CMPs (2009) (162)
- Improving GPGPU resource utilization through alternative thread block scheduling (2014) (154)
- Throughput-Effective On-Chip Networks for Manycore Accelerators (2010) (151)
- Memory-centric system interconnect design with Hybrid Memory Cubes (2013) (130)
- Indirect adaptive routing on large scale interconnection networks (2009) (118)
- HPCCD: Hybrid Parallel Continuous Collision Detection using CPUs and GPUs (2009) (92)
- Cost-Efficient Dragonfly Topology for Large-Scale Systems (2009) (72)
- FlexiBuffer: Reducing leakage power in on-chip network routers (2011) (71)
- Adaptive Routing in High-Radix Clos Network (2006) (70)
- High Performance Datacenter Networks: Architectures, Algorithms, and Opportunities (2011) (66)
- Microarchitecture of a High-Radix Router (2005) (57)
- Exploring concentration and channel slicing in on-chip network router (2009) (56)
- Router microarchitecture and scalability of ring topology in on-chip networks (2009) (53)
- Overcoming far-end congestion in large-scale networks (2015) (51)
- Galaxy: a high-performance energy-efficient multi-chip architecture using photonic interconnects (2014) (50)
- Probabilistic Distance-Based Arbitration: Providing Equality of Service for Many-Core CMPs (2010) (47)
- MGPUSim: Enabling Multi-GPU Performance Modeling and Optimization (2019) (42)
- Exploiting New Interconnect Technologies in On-Chip Communication (2012) (38)
- Multi-GPU System Design with Memory Networks (2014) (37)
- Accelerating linked-list traversal through near-data processing (2016) (35)
- Providing cost-effective on-chip network bandwidth in GPGPUs (2012) (35)
- Clumsy Flow Control for High-Throughput Bufferless On-Chip Networks (2013) (31)
- FeatherWeight: Low-cost optical arbitration with QoS support (2011) (31)
- Profiling DNN Workloads on a Volta-based DGX-1 System (2018) (30)
- BTS: an accelerator for bootstrappable fully homomorphic encryption (2021) (28)
- UMH: A Hardware-Based Unified Memory Hierarchy for Systems with Multiple Discrete GPUs (2016) (24)
- iPAWS: Instruction-issue pattern-based adaptive warp scheduling for GPGPUs (2016) (24)
- Network within a network approach to create a scalable high-radix router microarchitecture (2012) (23)
- Griffin: Hardware-Software Support for Efficient Page Migration in Multi-GPU Systems (2020) (22)
- Microbank: Architecting Through-Silicon Interposer-Based Main Memory Systems (2014) (21)
- Automatically exploiting implicit Pipeline Parallelism from multiple dependent kernels for GPUs (2016) (17)
- Footprint: Regulating routing adaptiveness in Networks-on-Chip (2017) (17)
- Contention-based congestion management in large-scale networks (2016) (17)
- Transportation-network-inspired network-on-chip (2014) (16)
- GNNMark: A Benchmark Suite to Characterize Graph Neural Network Training on GPUs (2021) (16)
- NeuMMU: Architectural Support for Efficient Address Translations in Neural Processing Units (2019) (15)
- Design of Interconnection Networks (2007) (15)
- High-radix interconnection networks (2008) (15)
- Low-Overhead Network-on-Chip Support for Location-Oblivious Task Placement (2014) (13)
- Energy-efficient scheduling for memory-intensive GPGPU workloads (2014) (13)
- Analyzing the impact of on-chip network traffic on program phases for CMPs (2009) (13)
- Leveraging torus topology with deadlock recovery for cost-efficient on-chip network (2011) (13)
- PIkit: A New Kernel-Independent Processor-Interconnect Rootkit (2016) (13)
- Designing on-chip networks for throughput accelerators (2013) (12)
- Multi-dimensional Parallel Training of Winograd Layer on Memory-Centric Architecture (2018) (11)
- Valkyrie: Leveraging Inter-TLB Locality to Enhance GPU Performance (2020) (10)
- On-Chip Network Evaluation Framework (2010) (10)
- ARK: Fully Homomorphic Encryption Accelerator with Runtime Data Generation and Inter-Operation Key Reuse (2022) (9)
- Scalable high-radix router microarchitecture using a network switch organization (2013) (9)
- Scheduling in Heterogeneous Computing Environments for Proximity Queries (2013) (9)
- Security Vulnerability in Processor-Interconnect Router Design (2014) (9)
- An Alternative Memory Access Scheduling in Manycore Accelerators (2011) (9)
- Evaluation of Performance Unfairness in NUMA System Architecture (2017) (8)
- MGSim + MGMark: A Framework for Multi-GPU System Research (2018) (8)
- Extending bufferless on-chip networks to high-throughput workloads (2014) (8)
- SuperSim: Extensible Flit-Level Simulation of Large-Scale Interconnection Networks (2018) (7)
- Mutually Aware Prefetcher and On-Chip Network Designs for Multi-Cores (2014) (7)
- Tuning Nanophotonic On-Chip Network Designs for Improving Memory Traffic (7)
- Design and Analysis of Hybrid Flow Control for Hierarchical Ring Network-on-Chip (2016) (7)
- On-chip network design considerations for compute accelerators (2010) (6)
- Efficient topologies for large-scale cluster networks (2010) (6)
- History-Based Arbitration for Fairness in Processor-Interconnect of NUMA Servers (2017) (6)
- A software-defined tensor streaming multiprocessor for large-scale machine learning (2022) (6)
- Approximating age-based arbitration in on-chip networks (2010) (6)
- Exploiting Mutual Awareness between Prefetchers and On-chip Networks in Multi-cores (2011) (6)
- Practical and efficient incremental adaptive routing for HyperX networks (2019) (5)
- Memory Network : Enabling Technology for Scalable Near-Data Computing (2014) (5)
- TCEP: Traffic Consolidation for Energy-Proportional High-Radix Networks (2018) (5)
- Trident: A Hybrid Correlation-Collision GPU Cache Timing Attack for AES Key Recovery (2021) (5)
- Exploring Benefits and Designs of Optically-Connected Disintegrated Processor Architecture (2010) (4)
- SpotMe effective co-optimization of design and defect inspection for fast yield ramp (2013) (4)
- A Novel Covert Channel Attack Using Memory Encryption Engine Cache (2019) (4)
- Network-on-Chip Microarchitecture-based Covert Channel in GPUs (2021) (4)
- Scheduling in heterogeneous computing environments for proximity queries. (2013) (4)
- BoomGate: Deadlock Avoidance in Non-Minimal Routing for High-Radix Networks (2021) (4)
- DeepHiR: improving high-radix router throughput with deep hybrid memory buffer microarchitecture (2019) (4)
- Cost-efficient dragonfly topology for large-scale systems (2009) (3)
- MGPUSim (2019) (3)
- MGPU-TSM: A Multi-GPU System with Truly Shared Memory (2020) (3)
- Scalable on-chip network in power constrained manycore processors (2012) (3)
- UMH (2016) (3)
- Adaptive and flexible key-value stores through soft data partitioning (2016) (2)
- The Groq Software-defined Scale-out Tensor Streaming Multiprocessor : From chips-to-systems architectural overview (2022) (2)
- Decoupled SSD: Reducing Data Movement on NAND-Based Flash SSD (2021) (2)
- Enforcing Last-Level Cache Partitioning through Memory Virtual Channels (2019) (2)
- Improving GPGPU Resource Utilization and Performance Through Alternative Cooperative Thread Array Scheduling (2014) (2)
- Accelerating Polynomial Multiplication for Homomorphic Encryption on GPUs (2022) (2)
- HALCONE : A Hardware-Level Timestamp-based Cache Coherence Scheme for Multi-GPU systems (2020) (2)
- Challenges/Opportunities to Enable Dependable Scale-out System with Groq Deterministic Tensor-Streaming Processors (2022) (1)
- The Case for Dynamic Bias in Global Adaptive Routing (2021) (1)
- Dynamic global adaptive routing in high-radix networks (2022) (1)
- Hybrid Memory Buffer Microarchitecture for High-Radix Routers (2022) (1)
- Accelerating Finite Field Arithmetic for Homomorphic Encryption on GPUs (2023) (1)
- A Case for Software-Based Adaptive Routing in NUMA Systems (2019) (1)
- Ee482c: Advanced Computer Organization Project Presentation (2) On-chip Support for Ilp, Dlp, and Tlp in an Imagine-like Stream Processor (0)
- COST-EFFICIENT DRAGONFLY TOPOLOGY FOR LARGE-SCALE (2009) (0)
- AchievingPredictablePerformancethroughBetterMemory ControllerPlacementinMany-CoreCMPs (2009) (0)
- Guest Editorial New Interconnect Technologies in On-Chip Communication (2012) (0)
- Networked SSD: Flash Memory Interconnection Network for High-Bandwidth SSD (2022) (0)
- Logical/Physical Topology-Aware Collective Communication in Deep Learning Training (2023) (0)
- Evaluation of Volta-based DGX-1 System Using DNN Workloads (2019) (0)
- Energy-Efficient Scheduling for Memory-Intensive GPGPU (2014) (0)
- Partitioning Register File to Reduce Access Time (2003) (0)
- Energy-Aware On-Chip Networks (2011) (0)
- DeepHiR (2019) (0)
- EE 482 c Final Project : Stream Programs on Legacy Architectures (0)
- Hybrid Parallel Computation for Proximity Queries (2012) (0)
- VVQ: Virtualizing Virtual Channel for Cost-Efficient Protocol Deadlock Avoidance (2023) (0)
- Panel: The Future of NoCs: Challenges and Opportunities (2022) (0)
- NeuMMU (2020) (0)
- Valkyrie (2020) (0)
- Performance Analysis of Overcoming Far-end Congestion in Large-Scale Networks (2018) (0)
- NaviSim: A Highly Accurate GPU Simulator for AMD RDNA GPUs (2022) (0)
- Ghost Routing to Enable Oblivious Computation on Memory-centric Networks (2021) (0)
- Bandwidth Bottleneck in Network-on-Chip for High-Throughput Processors (2020) (0)
- Answer Fast: Accelerating BERT on the Tensor Streaming Processor (2022) (0)
- Ghost routers: energy-efficient asymmetric multicore processors with symmetric NoCs (2019) (0)
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