John P. Hayes | Academic Influence

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John P. Hayes

Computer Science

#2341

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#2441

Historical Rank

#1042

USA Rank

Database

#2247

World Rank

#2362

Historical Rank

#513

USA Rank

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Computer Science

John P. Hayes's Degrees

PhD Computer Science Stanford University
Masters Computer Science Stanford University
Bachelors Computer Science Stanford University

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Why Is John P. Hayes Influential?

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According to Wikipedia, John Patrick Hayes is an Irish-American computer scientist and electrical engineer, the Claude E. Shannon Chair of Engineering Science at the University of Michigan. He supervised over 35 doctoral students, coauthored seven books and over 340 peer-reviewed publications. His Erdös number is 2.

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John P. Hayes's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Synthesis of reversible logic circuits (2003) (518)
Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering (1999) (479)
Survey of Stochastic Computing (2013) (442)
A survey of the theory of hypercube graphs (1988) (364)
Accurate reliability evaluation and enhancement via probabilistic transfer matrices (2005) (283)
A Graph Model for Fault-Tolerant Computing Systems (1976) (232)
Stochastic circuits for real-time image-processing applications (2013) (218)
Architecture of a Hypercube Supercomputer (1986) (193)
Hierarchical test generation using precomputed tests for modules (1990) (187)
Reversible logic circuit synthesis (2002) (167)
Low-cost on-line fault detection using control flow assertions (2003) (160)
A Microprocessor-based Hypercube Supercomputer (1986) (158)
A Fault-Tolerant Communication Scheme for Hypercube Computers (1992) (156)
Fault testing for reversible circuits (2003) (140)
Probabilistic transfer matrices in symbolic reliability analysis of logic circuits (2008) (139)
A Family of Logical Fault Models for Reversible Circuits (2005) (132)
Optimal synthesis of linear reversible circuits (2008) (130)
A Fully Integrated Auto-Calibrated Super-Regenerative Receiver in 0.13-$\mu{\hbox {m}}$ CMOS (2007) (129)
The Promise and Challenge of Stochastic Computing (2018) (127)
Exploiting correlation in stochastic circuit design (2013) (125)
Hypercube supercomputers (1989) (123)
Transition Count Testing of Combinational Logic Circuits (1976) (120)
Multiple Bus Architectures (1987) (116)
Testing for missing-gate faults in reversible circuits (2004) (109)
Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models (2003) (106)
Testing Memories for Single-Cell Pattern-Sensitive Faults (1980) (105)
Detection oF Pattern-Sensitive Faults in Random-Access Memories (1975) (104)
Testing ICs: Getting to the Core of the Problem (1996) (100)
Design of Easily Testable Bit-Sliced Systems (1981) (98)
Fast and accurate computation using stochastic circuits (2014) (97)
Hierarchical test generation using precomputed testsd for modules (1988) (95)
A unified switching theory with applications to VLSI design (1982) (95)
Transparent recovery from intermittent faults in time-triggered distributed systems (2003) (93)
Introduction to Digital Logic Design (1993) (91)
Exact and Heuristic Approaches to Input Vector Control for Leakage Power Reduction (2004) (90)
Improving Gate-Level Simulation of Quantum Circuits (2003) (90)
Quantum Circuit Simulation (2009) (88)
On-line sensing for healthier FPGA systems (2010) (87)
Self-optimization in computer systems via on-line control: application to power management (2004) (85)
Online BIST for Embedded Systems (1998) (85)
Energy-efficient hybrid stochastic-binary neural networks for near-sensor computing (2017) (83)
Edge fault tolerance in graphs (1993) (82)
Analysis of Multiple-Bus Interconnection Networks (1986) (82)
Data structures and algorithms for simplifying reversible circuits (2006) (78)
Checking equivalence of quantum circuits and states (2007) (78)
Enhancing design robustness with reliability-aware resynthesis and logic simulation (2007) (77)
Properties of the input pattern fault model (1997) (76)
Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems (2012) (75)
Signature-Based SER Analysis and Design of Logic Circuits (2009) (75)
Designing Fault-Tolerant System Using Automorphisms (1991) (74)
A Functional Approach to Testing Bit-Sliced Microprocessors (1981) (73)
Subcube Allocation in Hypercube Computers (1991) (73)
Gate-level simulation of quantum circuits (2002) (71)
Dependable communication synthesis for distributed embedded systems (2003) (71)
A Nand Model ror Fault Diagnosis in Combinational Logic Networks (1971) (71)
On Modifying Logic Networks to Improve Their Diagnosability (1974) (68)
Some practical issues in the design of fault-tolerant multiprocessors (1991) (66)
An Analysis Framework for Transient-Error Tolerance (2007) (65)
High-level test generation using physically-induced faults (1995) (63)
On randomly interleaved memories (1990) (61)
Fault testing for reversible circuits (2004) (60)
Test response compaction using multiplexed parity trees (1996) (59)
On Designing and Reconfiguring k-Fault-Tolerant Tree Architectures (1990) (58)
Digital Simulation with Multiple Logic Values (1986) (57)
Graph-based simulation of quantum computation in the density matrix representation (2004) (57)
Layout optimization of static CMOS functional cells (1990) (57)
Pseudo-Boolean Logic Circuits (1986) (56)
A Self-Testing Dynamic RAM Chip (1985) (55)
Fault-Tolerance of Dynamic-Full-Access Interconnection Networks (1984) (54)
Layout Optimization of CMOS Functional Cells (1987) (53)
On Realizations of Boolean Functions Requiring a Minimal or Near-Minimal Number of Tests (1971) (51)
Selective Hardening: Toward Cost-Effective Error Tolerance (2011) (50)
Routing and broadcasting in faulty hypercube computers (1988) (50)
Impact of mobility on connection in ad hoc networks (2005) (49)
Optimal Zero-Aliasing Space Compaction of Test Responses (1998) (49)
Introduction to stochastic computing and its challenges (2015) (48)
Layout Minimization of CMOS Cells (1991) (48)
High-performance QuIDD-based simulation of quantum circuits (2004) (48)
High-level design verification of microprocessors via error modeling (1998) (47)
High-level test generation for design verification of pipelined microprocessors (1999) (47)
An Introduction to Switch-Level Modeling (1987) (46)
A spectral transform approach to stochastic circuits (2012) (45)
Fault Modeling for Digital MOS Integrated Circuits (1984) (44)
Distributed Recovery in Fault-Tolerant Multiprocessor Networks (1986) (43)
Modeling and Mitigating Transient Errors in Logic Circuits (2011) (43)
STRAUSS: Spectral Transform Use in Stochastic Circuit Synthesis (2015) (43)
An Experimental MOS Fault Simulation Program CSASIM (1984) (42)
Contactless testing: Possibility or pipe-dream? (2009) (42)
Design verification via simulation and automatic test pattern generation (1995) (42)
Hierarchical timing analysis using conditional delays (1995) (41)
On the role of timing masking in reliable logic circuit design (2008) (39)
Collection and Analysis of Microprocessor Design Errors (2000) (39)
The Fanout Structure of Switching Functions (1975) (39)
Design of Division Circuits for Stochastic Computing (2016) (39)
Stochastic Logic Realization of Matrix Operations (2014) (39)
An automorphic approach to the design of fault-tolerant multiprocessors (1989) (36)
Is quantum search practical? (2004) (36)
Efficient Synthesis of Linear Reversible Circuits (2003) (34)
Analyzing and controlling accuracy in stochastic circuits (2014) (34)
Isolation-based decorrelation of stochastic circuits (2016) (32)
On allocating subcubes in a hypercube multiprocessor (1988) (32)
A hierarchical test generation methodology for digital circuits (1990) (31)
Transient fault characterization in dynamic noisy environments (2005) (30)
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages (2005) (30)
Test Propagation Through Modules and Circuits (1991) (29)
Time-constrained failure diagnosis in distributed embedded systems: application to actuator diagnosis (2005) (29)
Node fault tolerance in graphs (1996) (29)
On the Properties of Irredundant Logic Networks (1976) (28)
Efficient test response compression for multiple-output circuits (1994) (28)
Advanced modeling of faults in Reversible circuits (2010) (27)
TESTING BIT-SLICED MICROPROCESSORS. (1979) (27)
Identification of Equivalent Faults in Logic Networks (1980) (27)
Tracking Uncertainty with Probabilistic Logic Circuit Testing (2007) (26)
Optimal space compaction of test responses (1995) (26)
Optimal 2-D cell layout with integrated transistor folding (1998) (26)
Realization-independent ATPG for designs with unimplemented blocks (2001) (25)
High-coverage ATPG for datapath circuits with unimplemented blocks (1998) (25)
Logic circuit testing for transient faults (2005) (25)
Width minimization of two-dimensional CMOS cells using integer programming (1996) (25)
CHECK SUM METHODS FOR TEST DATA COMPRESSION. (1976) (25)
Design for Robustness (2013) (25)
Testability of Convergent Tree Circuits (1996) (24)
An approximate timing analysis method for datapath circuits (1996) (24)
ILP-based optimization of sequential circuits for low power (2003) (23)
Exact width and height minimization of CMOS cells (1991) (23)
XPRESS: a cell layout generator with integrated transistor folding (1996) (23)
Testability Considerotions in Microprocessor-Based Design (1980) (23)
Test-set preserving logic transformations (1992) (22)
High-level test generation using symbolic scheduling (1995) (21)
Logic simulation on vector processors (1988) (21)
Design, Analysis and Test of Logic Circuits Under Uncertainty (2012) (20)
Scalable Test Generators for High-Speed Datapath Circuits (1998) (20)
On the Functions Realized by Stochastic Computing Circuits (2015) (20)
A Fault Simulation Methodology for VLSI (1982) (20)
Clip: An Optimizing Layout Generator For Two-dimensional Cmos Cells (1997) (19)
Building a Better Random Number Generator for Stochastic Computing (2017) (19)
Tolerating transient faults in statically scheduled safety-critical embedded systems (1999) (19)
Event propagation conditions in circuit delay computation (1997) (18)
Fault tolerance of a class of connecting networks (1980) (18)
Behavior of stochastic circuits under severe error conditions (2014) (17)
Reducing Inerference Among Vector Accesses in Interleaved Memories (1993) (17)
Zero-aliasing space compaction of test responses using multiple parity signatures (1998) (17)
Tomographic Testing and Validation of Probabilistic Circuits (2011) (17)
A fault model for function and delay testing (2001) (16)
HIGH-LEVEL TEST GENERATION USING BUS FAULTS. (1985) (16)
Digital system design and microprocessors (1984) (16)
Technology mapping for field-programmable gate arrays using integer programming (1995) (16)
Equivalence among stochastic logic circuits and its application (2015) (16)
The Coupling Model for Function and Delay Faults (2005) (15)
S-box-based random number generation for stochastic computing (2018) (15)
Detection and diagnosis of faulty quantum circuits (2012) (15)
Framework for quantifying and managing accuracy in stochastic circuit design (2017) (15)
Optimally edge fault-tolerant trees (1996) (14)
Cumulative balance testing of logic circuits (1995) (14)
A Logic Design Theory for VLSI (1981) (14)
Scalable and accurate estimation of probabilistic behavior in sequential circuits (2010) (14)
A 3.6mW 2.4-GHz multi-channel super-regenerative receiver in 130nm CMOS (2005) (13)
Gate Sizing and Vt Assignment for Active-Mode Leakage Power Reduction (2006) (13)
Uncertainty, Energy, and Multiple-Valued Logics (1986) (13)
Accuracy of magnitude-class calculations in switch-level modeling (1992) (13)
On the Role of Sequential Circuits in Stochastic Computing (2017) (12)
Dimension reduction in statistical simulation of digital circuits (2015) (12)
Design of a fast, easily testable ALU (1996) (12)
Generation of Optimal Transition Count Tests (1978) (12)
CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells (2000) (12)
Logic Design Validation via Simulation and Automatic Test Pattern Generation (2000) (12)
Eliminating a hidden error source in stochastic circuits (2017) (12)
High-level test generation for VLSI (1989) (11)
Hierarchical Modeling for VLSI Circuit Testing (1989) (11)
Approximate simulation of circuits with probabilistic behavior (2013) (11)
Design of stochastic Viterbi decoders for convolutional codes (2013) (11)
Balanced Boolean functions (1998) (11)
Enumeration of Fanout-Free Boolean Functions (1976) (11)
SYSTEMATIC APPROACH TO MULTIVALUED DIGITAL SIMULATION. (1984) (10)
Trigonometric method to handle realistic error probabilities in logic circuits (2011) (10)
Optimizing stochastic circuits for accuracy-energy tradeoffs (2015) (10)
Systematic Design of Fault-Tolerant Multiprocessors with Shared Buses (1997) (10)
Time-constrained failure diagnosis in distributed embedded systems (2002) (10)
Scalable Simplification of Reversible Circuits (10)
Implementation of VLSI self-testing by regularization (1988) (10)
Trading Accuracy for Energy in Stochastic Circuit Design (2017) (10)
Achieving progressive precision in stochastic computing (2017) (10)
Design of Totally Fault Locatable Combinational Networks (1980) (9)
Fast and Accurate Timing Characterization Using Functional Information (2001) (9)
ESIM: a multimodel design error and fault simulator for logic circuits (2000) (9)
High-level delay test generation for modular circuits (2006) (9)
Wireless wafer-level testing of integrated circuits via capacitively-coupled channels (2011) (9)
Improving testability and soft-error resilience through retiming (2009) (9)
On the quality of accumulator-based compaction of test responses (1997) (9)
Design and Reconfiguration Strategies for Near-Optimal k-fault-tolerant Tree Architectures (1988) (8)
FAULT RECOVERY IN MULTIPROCESSOR NETWORKS. (1978) (8)
An Online Control Framework for Designing Self-Optimizing Computing Systems: Application to Power Management (2005) (8)
Task Scheduling Algorithms for Fault Tolerance in Real-Time Embedded Systems (2000) (8)
Balance testing and balance-testable design of logic circuits (1996) (8)
High-level vulnerability over space and time to insidious soft errors (2008) (8)
Magnitude classes in switch-level modeling (1989) (8)
Designing for high-level test generation (1990) (8)
Connective Fault Tolerance in Multiple-Bus Systems (1997) (8)
Quantum Approaches to Logic Circuit Synthesis and Testing (2006) (8)
Efficient testing of tree circuits (1993) (7)
CALCULUS FOR TESTING COMPLEX DIGITAL SYSTEMS. (1980) (7)
Analysis and Simulation of a PN Synchronization System (1970) (7)
FAST AND EASILY TESTABLE IMPLEMENTATION OF ARITHMETIC FUNCTIONS. (1986) (7)
A hierarchical technique for minimum-width layout of two-dimensional CMOS cells (1997) (7)
An Array Layout Methodology for VLSI Circuits (1986) (6)
When are Multiple Gate Errors Significant in Logic Circuits ? (2006) (6)
On the design of fast, easily testable ALU's (2000) (6)
An advanced timing characterization method using mode dependency (2001) (6)
Design of accurate stochastic number generators with noisy emerging devices for stochastic computing (2017) (6)
Power-Aware Link Maintenance (PALM) for Mobile Ad Hoc Networks (2007) (6)
Delay fault testing of designs with embedded IP cores (1999) (6)
On the maximum function in stochastic computing (2019) (6)
Fast and accurate timing characterization using functionalinformation (2001) (6)
Rapid Prototyping & Evaluation of High-Performance Computers (1996) (6)
The Hypergeometric Distribution as a More Accurate Model for Stochastic Computing (2020) (6)
General modeling and technology-mapping technique for LUT-based FPGAs (1997) (6)
The input pattern fault model and its application (1997) (5)
Hierarchical Test Generation (1990) (5)
Aliasing-free error detection (ALFRED) (1993) (5)
A normalized-area measure for VLSI layouts (1988) (5)
Discovering 1-FT routes in mobile ad hoc networks (2004) (5)
Scalar-Vector Memory Interference in Vector Computers (1991) (5)
Path Complexity of Logic Networks (1978) (5)
Scalable sampling methodology for logic simulation: Reduced-Ordered Monte Carlo (2012) (5)
Equivalence Among Stochastic Logic Circuits and its Application to Synthesis (2019) (5)
Improving QuIDD-based Simulation (2009) (4)
Accuracy and Correlation in Stochastic Computing (2019) (4)
A 900 Mbps single-channel capacitive I/O link for wireless wafer-level testing of integrated circuits (2011) (4)
Gate sizing and V/sub t/ assignment for active-mode leakage power reduction (2004) (4)
Connectivity and Fault Tolerance of Multiple-Bus Systems (1994) (4)
Minimization of Fanout in Switching Networks (1974) (4)
Hardware-based Fast Real-time Image Classification with Stochastic Computing (2020) (4)
Design and reconfiguration strategies for near-optimal k-fault-tolerant tree architectures (1988) (4)
Self-Test and Adaptation for Random Variations in Reliability (2010) (4)
Benefits of Stochastic Computing in Hearing Aid Filterbank Design (2021) (4)
Design of Gracefully Degradable Hypercube-Connected Systems (1992) (4)
Near-optimum hierarchical layout synthesis of two-dimensional CMOS cells (1999) (4)
On-line characterization and reconfiguration for single event upset variations (2009) (4)
Partitioning logic circuits to maximize fault resolution (1976) (3)
AnSER : A Lightweight Reliability Evaluator for use in Logic Synthesis (3)
Balance testing of logic circuits (1993) (3)
Structural fault tolerance in VLSI-based systems (1994) (3)
1 A Model for Transient Faults in Logic Circuits (2006) (3)
Design of Scalable Hardware Test Generators for On-Line BIST (1996) (3)
On the Limits of Stochastic Computing (2019) (3)
Delay fault testing of IP-based designs via symbolic path modeling (1999) (3)
Optimal Testing and Design of Adders (1994) (3)
• Workshop on Fault-Tolerant Parallel and Distributed Systems (2004) (3)
Monitoring Transient Errors in Sequential Circuits (2007) (3)
Bayesian Accuracy Analysis of Stochastic Circuits (2020) (3)
Exploring Target Function Approximation for Stochastic Circuit Minimization (2020) (3)
On-Chip Test Generation Using Linear Subspaces (2006) (3)
Toward Physically-Adaptive Computing (2010) (3)
Low-Area and High-Speed Approximate Matrix-Vector Multiplier (2015) (2)
SURVEY OF bit-SLICED COMPUTER DESIGN. (1981) (2)
Optimizing router locations for minimum-energy wireless networks (2008) (2)
DFBT: A Design-for-Testability Method Based on Balance Testing (1994) (2)
A Local-Sparing Design Methodology for Fault-Tolerant Multiprocessors a a This research was supporte (1997) (2)
On-Line Monitor Design of Finite-State Machines (2002) (2)
FAULT RECOVERY IN LOOP NETWORKS. (1986) (2)
A self-testing dynamic RAM chip (1985) (2)
Synthesis of fault-tolerant beta-networks (1982) (2)
Summary and Extensions (2013) (2)
Area-optimal technology mapping for field-programmable gate arrays based on lookup tables (2005) (2)
Computing wiht ramdomness (2018) (2)
Probabilistic Transfer Matrices (2013) (2)
General technology mapping for field-programmable gate arrays based on lookup tables (2002) (2)
DESIGN OF SELF-TESTING VLSI COMPONENTS. (1987) (1)
Testability Properties of Divergent Trees (1997) (1)
Tutorial: basic concepts in quantum circuits (2003) (1)
TEST GENERATION USING EQUIVALENT NORMAL FORMS. (1979) (1)
Impact of Autocorrelation on Stochastic Circuit Accuracy (2019) (1)
Quantum Information Processing (2009) (1)
Fault-Tolerant Quantum Computers (2002) (1)
An advanced timing characterization method using mode dependecy (2001) (1)
Evaluation of Design Error Models for Verification Testing of Microprocessors 1 (1998) (1)
Linear Algebra and Quantum Mechanics (2009) (1)
Analysis and Design of Fault-Tolerant Computer Systems (1978) (1)
Guest Editors' Introduction: Stochastic Computing for Neuromorphic Applications (2021) (1)
Maxflow (2018) (1)
Checking Equivalence of States and Circuits (2009) (1)
BUILT-IN TESTING APPROACH FOR REGULAR VLSI CIRCUITS. (1985) (1)
On meshy trees (1989) (1)
A Local-Sparing Design Methodology for Fault-Tolerant MultiprocessorsaaThis research was supported in part by the Office of Naval Research under Contract N00014-85K0531 and N00014-90J1860, and in part by NSF Grants MIP-9210049 and MIP-9200526. (1997) (1)
Maxflow: Minimizing Latency in Hybrid Stochastic-Binary Systems (2018) (1)
Fault Recovery in Distributed Processing Loop Networks (1988) (1)
Line graph transformations to modeling large distributed systems (1990) (1)
Recovery from Transition Errors in Sequential Circuits (2007) (1)
Faults and Tests in Quantum Circuits (2005) (1)
On the Maximum Function in Stochastic Neural Networks (2018) (0)
CeMux: Maximizing the Accuracy of Stochastic Mux Adders and an Application to Filter Design (2021) (0)
Dependable Communication Synthes is for Dis tr ibuted Embedded Systems * (2003) (0)
Series-Parallel Cell Width Minimization (1992) (0)
Functional Cell Layout Methods (1992) (0)
Special Session 3B: New Topic (2008) (0)
4757503 Self-testing dynamic RAM (1989) (0)
Gate Modeling and Circuit Simulation (2009) (0)
Guest Editor's Introduction: Testing and Improving the Testability of Multimegabit Memories (1993) (0)
Planar Cell Width Minimization (1992) (0)
On the Equivalence of Regular Expressions (1968) (0)
Fast Test Simulation via Distributed Computing (2006) (0)
MODELING AND DETECTING CONTROL ERRORS IN MICROPROCESSORS (1999) (0)
Robust Coupling Delay Test Sets (2012) (0)
PathComplexity ofLogic Networks (1978) (0)
Design for Testability (1990) (0)
SELF-TESTING BIT-SLICED MICROCOMPUTERS. (1981) (0)
Error Simulation with Conditional Error Models (0)
Wavelet Transform Assisted Neural Networks for Human Activity Recognition (2022) (0)
Analyzing Multilevel Stochastic Circuits using Correlation Matrices (2022) (0)
Computing with Probabilistic Transfer Matrices (2013) (0)
Signature-Based Reliability Analysis (2013) (0)
Special Session 3B: New Topic Why Nanoscale Physics Favors Quantum Information Why Computing is Possible in Spite of Quantum Uncertainty (2008) (0)
Design and fabrication of combinational and sequential logic families (2002) (0)
Stochastic Computing Architectures for Lightweight LSTM Neural Networks (2022) (0)
Special Case: Simulating Stabilizer Circuits (2009) (0)
Event Propagation Conditions in Timing Analysis (1995) (0)
System testing and design for diagnosability (1976) (0)
Chapter 18 TASK SCHEDULING ALGORITHMS FOR FAULT TOLERANCE IN REAL-TIME EMBEDDED SYSTEMS (1999) (0)
Testability Properties of Divergent Trees Testability Properties of Divergent Trees (2022) (0)
MULTIPLEXED TEST STRUCTURES FOR IC PROCESS EVALUATION. (1987) (0)
A pr 2 00 4 Is Quantum Search Practical ? (0)
Removing constant-induced errors in stochastic circuits (2019) (0)
Hybrid Techniques for Optimizing Complex Systems (2009) (0)
Wireless wafer probing for on-chip analog voltage measurement (2012) (0)
FEATURE Q (2005) (0)
Robust Coupling Delay Test Sets (2012) (0)
Session details: Advances in synthesis (2014) (0)
2.2 Stochastic, Approximate and Neural Computing (2017) (0)
Testing Logic Circuits for Probabilistic Faults (2013) (0)
Properties of t put Pattern Fault MO (1997) (0)
S Is Quantum Search Practical? Q U a N T U M C O M P U T I N G (2005) (0)
State-Vector Simulation with Decision Diagrams (2009) (0)
Single Cell Width and Height Minimization (1992) (0)
OntheProperties ofIrredundant Logic Networks (1976) (0)
AGraphModelforFault-Tolerant Computing Systems (1976) (0)
Hybrid Techniques for Quantum Circuit Simulation (2014) (0)
Generic Circuit Simulation Techniques (2009) (0)
Cell Array Width and Height Minimization (1992) (0)
Density-Matrix Simulation with QuIDDs (2009) (0)
Retraining and Regularization to Optimize Neural Networks for Stochastic Computing (2020) (0)
Multiprocessor Systems For High Performance High Reliability Applications (1988) (0)
Circuit and Fault Modeling (1990) (0)
OnModifying Logic Networks to Improve TheirDiagnosability (1974) (0)
QUIDDPRO USER’S GUIDE (2007) (0)
Exploiting Randomness in Stochastic Computing (2019) (0)
Fault-tolerance and performance analysis of beta-networks (1986) (0)

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