Jordi Cortadella
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Spanish computer scientist
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Computer Science
Jordi Cortadella's Degrees
- PhD Computer Science Polytechnic University of Catalonia
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Why Is Jordi Cortadella Influential?
(Suggest an Edit or Addition)According to Wikipedia, Jordi Cortadella Fortuny is a Spanish computer scientist specializing in electronic design automation. He is a professor of computer science at the Polytechnic University of Catalonia. Cortadella was elected to the Academia Europaea in 2013. He was named as a Fellow of the Institute of Electrical and Electronics Engineers in 2015 for contributions to the design of asynchronous and elastic circuits.
Jordi Cortadella's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- Petrify: A Tool for Manipulating Concurrent Specifications and Synthesis of Asynchronous Controllers (Special Issue on Asynchronous Circuit and System Design) (1997) (554)
- Deriving Petri Nets for Finite Transition Systems (1998) (261)
- Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications (2006) (194)
- Petri Net Analysis Using Boolean Manipulation (1994) (192)
- Working-zone encoding for reducing the energy in microprocessor address buses (1998) (173)
- Logic Synthesis for Asynchronous Controllers and Interfaces (2002) (163)
- Synthesis of synchronous elastic architectures (2006) (152)
- The octahedron abstract domain (2004) (140)
- A Region-Based Algorithm for Discovering Petri Nets from Event Logs (2008) (113)
- Elastic Circuits (2009) (112)
- High-level synthesis techniques for reducing the activity of functional units (1995) (107)
- Individual flip-flops with gated clocks for low power datapaths (1997) (102)
- Exploiting the locality of memory references to reduce the address bus energy (1997) (99)
- Applications and Theory of Petri Nets 2004 (2004) (99)
- Verification of Asynchronous Circuits by BDD-based Model Checking of Petri Nets (1995) (93)
- Handshake protocols for de-synchronization (2004) (89)
- Synthesizing Petri nets from state-based models (1995) (87)
- New Region-Based Algorithms for Deriving Bounded Petri Nets (2010) (73)
- Coping with the variability of combinational logic delays (2004) (69)
- Symbolic Analysis of Bounded Petri Nets (2001) (69)
- Task generation and compile-time scheduling for mixed data-control embedded software (2000) (69)
- Scheduling and resource binding for low power (1995) (65)
- Variable-latency design by function speculation (2009) (63)
- Timing-driven logic bi-decomposition (2003) (53)
- A region-based theory for state assignment in speed-independent circuits (1997) (52)
- Checking signal transition graph implementability by symbolic BDD traversal (1995) (52)
- Process Mining Meets Abstract Interpretation (2010) (50)
- Structural methods for the synthesis of speed-independent circuits (1996) (50)
- Evaluation of A + B = K Conditions Without Carry Propagation (1992) (47)
- Quasi-static scheduling of independent tasks for reactive systems (2002) (47)
- Complete state encoding based on the theory of regions (1996) (46)
- Synchronous Elastic Circuits with Early Evaluation and Token Counterflow (2007) (46)
- Genet: A Tool for the Synthesis and Mining of Petri Nets (2009) (45)
- Efficient encoding schemes for symbolic analysis of Petri nets (1998) (45)
- A Recursive Paradigm to Solve Boolean Relations (2004) (45)
- A performance analytical model for Network-on-Chip with constant service time routers (2009) (43)
- Synchronous Elastic Networks (2006) (41)
- Design Automation of Real-Life Asynchronous Devices and Systems (2007) (39)
- A Symbolic Algorithm for the Synthesis of Bounded Petri Nets (2008) (36)
- High-level synthesis of asynchronous systems: Scheduling and process synchronization (1993) (35)
- Combining process algebras and Petri nets for the specification and synthesis of asynchronous circuits (1996) (33)
- Designing asynchronous circuits from behavioural specifications with internal conflicts (1994) (33)
- Polynomial algorithms for the synthesis of hazard-free circuits from signal transition graphs (1993) (32)
- Metastability in Better-Than-Worst-Case Designs (2014) (32)
- Formal verification of safety properties in timed circuits (2000) (32)
- Hardware and Petri Nets: Application to Asynchronous Circuit Design (2000) (30)
- Decomposition and technology mapping of speed-independent circuits using Boolean relations (1997) (30)
- A structural encoding technique for the synthesis of asynchronous circuits (2001) (30)
- Coupling Asynchrony and Interrupts: Place Chart Nets (1997) (30)
- Divide-and-Conquer Strategies for Process Mining (2009) (30)
- Structural Methods to Improve the Symbolic Analysis of Petri Nets (1999) (30)
- Correct-by-construction microarchitectural pipelining (2008) (29)
- Brownian Circuits: Fundamentals (2013) (29)
- Logic decomposition of speed-independent circuits (1999) (29)
- High-Radix Division and Square-Root with Speculation (1994) (28)
- SELF : Specification and design of synchronous elastic circuits (2005) (28)
- Synthesis of asynchronous controllers using integer linear programming (2006) (27)
- Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions (2002) (26)
- Verification of timed circuits with symbolic delays (2004) (26)
- Technology mapping for speed-independent circuits: Decomposition and resynthesis (1997) (26)
- Performance analysis of concurrent systems with early evaluation (2006) (26)
- Verification of concurrent systems with parametric delays using octahedra (2005) (25)
- Lazy transition systems: application to timing optimization of asynchronous circuits (1998) (24)
- A concurrent model for de-synchronization (2003) (24)
- ILP models for the synthesis of asynchronous control circuits (2003) (24)
- State encoding of large asynchronous controllers (2006) (23)
- Ring Oscillator Clocks and Margins (2016) (23)
- Process Discovery Algorithms Using Numerical Abstract Domains (2014) (23)
- Input/Output Compatibility of Reactive Systems (2002) (22)
- Asynchronous interface specification, analysis and synthesis (1998) (22)
- Hierarchical gate-level verification of speed-independent circuits (1995) (22)
- What is the cost of delay insensitivity? (1999) (21)
- An efficient unique state coding algorithm for signal transition graphs (1993) (21)
- Automatic Generation Of Synchronous Test Patterns For Asynchronous Circuits (1997) (20)
- Low-Power Array Multipliers with Transition-Retaining Barriers (1995) (19)
- Performance optimization of elastic systems using buffer resizing and buffer insertion (2008) (19)
- Jutge.org: Characteristics and Experiences (2018) (19)
- From synchronous to asynchronous: an automatic approach (2004) (19)
- Methodology and tools for state encoding in asynchronous circuit synthesis (1996) (19)
- An asynchronous architecture model for behavioral synthesis (1992) (19)
- Optimizing CMOS circuits for low power using transistor reordering (1996) (18)
- Log-Based Simplification of Process Models (2015) (18)
- Buffer Placement and Sizing for High-Performance Dataflow Circuits (2020) (18)
- Support-Reducing Decomposition for FPGA Mapping (2020) (18)
- A Boolean Rule-Based Approach for Manufacturability-Aware Cell Routing (2014) (18)
- Encoding Large Asynchronous Controllers With ILP Techniques (2008) (17)
- Concurrency and Hardware Design, Advances in Petri Nets (2002) (16)
- Narrowing the margins with elastic clocks (2010) (16)
- Mining structured petri nets for the visualization of process behavior (2016) (16)
- Synthesis of asynchronous control circuits with automatically generated relative timing assumptions (1999) (16)
- Derivation of Non-structural Invariants of Petri Nets Using Abstract Interpretation (2005) (16)
- Scheduling Synchronous Elastic Designs (2009) (15)
- Automatic microarchitectural pipelining (2010) (15)
- The Use of Petri Nets for the Design and Verification of Asynchronous Circuits and Systems (1998) (15)
- A general model for performance optimization of sequential systems (2007) (15)
- Retiming and recycling for elastic systems with early evaluation (2009) (15)
- Concurrency and Hardware Design (2002) (15)
- A mathematical formulation of the loop pipelining problem (1996) (14)
- Speculation in Elastic Systems (2009) (14)
- SafeRazor: Metastability-Robust Adaptive Clocking in Resilient Circuits (2015) (14)
- Discovering Duplicate Tasks in Transition Systems for the Simplification of Process Models (2016) (14)
- Synthesis of Asynchronous Hardware from Petri Nets (2003) (13)
- Extension of the working-zone-encoding method to reduce the energy on the microprocessor data bus (1998) (13)
- Synthesis Of Speed-independent Circuits From STG-unfolding Segment (1997) (13)
- RTL Synthesis: From Logic Synthesis to Automatic Pipelining (2015) (13)
- Bridging the gap between asynchronous design and designers (2004) (13)
- Static Task Mapping for Tiled Chip Multiprocessors with Multiple Voltage Islands (2012) (13)
- Partial order based approach to synthesis of speed-independent circuits (1997) (12)
- Enabling adaptability through elastic clocks (2009) (12)
- Quasi-static scheduling for concurrent architectures (2003) (12)
- Resource-constrained pipelining based on loop transformations (1993) (12)
- Analytical Performance Modeling of Hierarchical Interconnect Fabrics (2012) (12)
- Reactive clocks with variability-tracking jitter (2015) (11)
- CAD directions for high performance asynchronous circuits (1999) (11)
- Division with speculation of quotient digits (1993) (11)
- Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing (2010) (11)
- Evaluating 'A+B=K' conditions in constant time (1988) (10)
- Exact and Heuristic Allocation of MuIti-kernel Applications to Multi-FPGA Platforms (2019) (10)
- Automating synthesis of asynchronous communication mechanisms (2005) (10)
- Multi-level clustering for clock skew optimization (2009) (10)
- Architectural Exploration of Large-Scale Hierarchical Chip Multiprocessors (2013) (9)
- Area-Optimal Transistor Folding for 1-D Gridded Cell Design (2013) (9)
- A mechanism for reducing the cost of branches in RISC architectures (1988) (9)
- Integrating formal verification in an online judge for e-Learning logic circuit design (2012) (8)
- A Fast and Retargetable Framework for Logic-IP-Internal Electromigration Assessment Comprehending Advanced Waveform Effects (2016) (8)
- Identifying state coding conflicts in asynchronous system specifications using Petri net unfoldings (1998) (8)
- Stochastic and topologically aware electromigration analysis for clock skew (2015) (8)
- A Relational View of Subgraph Isomorphism (2000) (8)
- CNN-on-AWS: Efficient Allocation of Multikernel Applications on Multi-FPGA Platforms (2020) (8)
- SELF : Specification and design of a synchronous elastic architecture for DSM systems (2005) (8)
- Synthesis of All-Digital Delay Lines (2017) (8)
- Resource-Constrained Software Pipelining for High-Level Synthesis of DSP Systems (1995) (8)
- Automatic synthesis and optimization of partially specified asynchronous systems (1999) (8)
- Bi-Decomposition and Tree-Height Reduction for Timing Optimization (2002) (7)
- A high-level synthesis system for asynchronous circuits (1992) (7)
- Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis (1997) (7)
- Microarchitectural Transformations Using Elasticity (2011) (7)
- Synthesis of Reactive Systems: Application to Asynchronous Circuit Design (2002) (7)
- A retargetable and accurate methodology for logic-IP-internal electromigration assessment (2015) (7)
- Combining structural and symbolic methods for the verification of concurrent systems (1998) (6)
- Power-Optimal Mapping of CNN Applications to Cloud-Based Multi-FPGA Platforms (2020) (6)
- Boolean decomposition using two-literal divisors (2004) (6)
- Elasticity and Petri Nets (2008) (6)
- Layout-Aware Gate Duplication and Buffer Insertion (2007) (6)
- Waveform Transition Graphs: A Designer-Friendly Formalism for Asynchronous Behaviours (2017) (6)
- Designing a branch target buffer for executing branches with zero time cost in a RISC processor (1988) (6)
- A multi-radix approach to asynchronous division (2001) (5)
- Elastic systems (2010) (5)
- Maximum-Throughput Software Pipelining (1995) (5)
- Dynamic RAM for on-chip instruction caches (1988) (5)
- A Scheduling Strategy for Synchronous Elastic Designs (2011) (5)
- Timing-driven N-way decomposition (2009) (4)
- Reducing Register Pressure in Software Pipelining (1998) (4)
- Hardware primitives for the synthesis of multithreaded elastic systems (2014) (4)
- Voltage Noise Analysis with Ring Oscillator Clocks (2017) (4)
- A region-based theory for state assignment in asynchronous circuits. (1997) (4)
- A Compositional Method for the Synthesis of Asynchronous Communication Mechanisms (2007) (4)
- Behavioral transformations to increase noise immunity in asynchronous specifications (1999) (4)
- Support-Reducing Functional Decomposition for FPGA Technology Mapping (2018) (4)
- Specification Mining for Asynchronous Controllers (2016) (4)
- RESIS: A New Methodology for Register Optimization in Software Pipelining (1996) (4)
- RTL-Aware Dataflow-Driven Macro Placement (2019) (4)
- Symbolic Petri Net Analysis Using Boolean Manipulation (1997) (4)
- A case study for the verification of complex timed circuits: IPCMOS (2002) (4)
- NOTA SOBRE ANTIGÜEDAD, NACIONALISMO(S) E HISTORIOGRAFÍA: DOS ESTUDIOS DE CASO EN LAS HISTORIOGRAFÍAS VASCA Y CATALANA a note on antiquity, nationalism(s) and historiography: two case studies from the basque and catalan historiographies (2015) (4)
- On the Performance Evaluation of Multi-Guarded Marked Graphs with Single-Server Semantics (2010) (4)
- Automatic Safe Data Reuse Detection for the WCET Analysis of Systems With Data Caches (2020) (3)
- Applications and Theory of Petri Nets 2004: 25th International Conference, ICATPN 2004, Bologna, Italy, June 21-25, 2004, Proceedings (2004) (3)
- A hierarchical approach for generating regular floorplans (2014) (3)
- Dominator-based partitioning for delay optimization (2006) (3)
- Process Windows (2017) (3)
- Synthesis from Waveform Transition Graphs (2019) (3)
- Rclp: a Novel Approach for Resource-constrained Loop Pipelining Rclp:a Novel Approach for Resource-constrained Loop Pipelining 3 (1993) (3)
- Boolean Decomposition for AIG Optimization (2017) (3)
- Rclp: a Novel Approach for Resource-constrained Loop Pipelining Rclp:a Novel Approach for Resource-constrained Loop Pipelining 3 (1993) (3)
- A new look at the conditions for the synthesis of speed-independent circuits (1995) (3)
- Physical-aware system-level design for tiled hierarchical chip multiprocessors (2013) (3)
- Formal methods for the analysis and synthesis of nanometer-scale cellular arrays (2008) (3)
- A radix-16 SRT division unit with speculation of the quotient digits (1999) (3)
- Logic synthesis techniques for embedded control code optimization (1997) (3)
- Asynchronous multipliers with variable-delay counters (2001) (3)
- Physical planning for the architectural exploration of large-scale chip multiprocessors (2013) (2)
- Coupling Technology Mapping, Logic Optimization and State Encoding for Speed-independent Circuits (1996) (2)
- From molecular interactions to gates: a systematic approach (2006) (2)
- Symbolic performance analysis of elastic systems (2010) (2)
- Symbolic Techniques for the Automatic Test Pattern Generation for Speed-Independent Circuits (1997) (2)
- External Reviewers (2020) (2)
- Transistor Placement for Automatic Cell Synthesis through Boolean Satisfiability (2020) (2)
- State Encoding of Asynchronous Controllers Using Pseudo-Boolean Optimization (2018) (2)
- State-Based Encoding of Large Asynchronous Controllers (2018) (2)
- Robustness to Voltage Noise With Ring Oscillator Clocks (2019) (2)
- Polynomial Algorithms for Complete State Coding and Synthesis of Hazard-free Circuits from Signal Tr (1993) (2)
- Logic design of asynchronous circuits (2002) (2)
- Bridging modularity and optimality: delay-insensitive interfacing in asynchronous circuits synthesis (1999) (1)
- Reduced instruction buffer for RISC architectures (1989) (1)
- Performance-preserving clustering of elastic controllers (2008) (1)
- Synchronous Elastic Circuits (2006) (1)
- Decomposition of transition systems into sets of synchronizing state machines (2021) (1)
- RTL Synthesis: From Logic Synthesis to Automatic (2015) (1)
- Multilevel Dataflow-Driven Macro Placement Guided by RTL Structure and Analytical Methods (2021) (1)
- Static Timing Analysis (2017) (1)
- Register-Transfer Level Transformations for Low-Power Data-Paths (1998) (1)
- Increasing the robustness of digital circuits with ring oscillator clocks (2017) (1)
- Designing Asynchronous Circuits from Behavioural Speciications with Internal Connicts Designing Asynchronous Circuits from Behavioural Speciications with Internal Connicts (2007) (1)
- Glass: a graph-theoretical approach for global binding (1993) (1)
- Scheduling in a continuous area-time design space (1991) (1)
- Making branches transparent to the execution unit (1989) (1)
- Embedded code optimization via common control structure detection (1997) (1)
- Adaptive clock with useful jitter (2015) (0)
- Asynchronous Interface Speciication, Analysis and Synthesis 1 Speciication with Petri Nets 1.1 from Timing Diagrams to Petri Nets (1998) (0)
- Session details: High-performance synchronization techniques (2007) (0)
- Restructuring multi-level networks by using function approximations (2003) (0)
- Under-the-Cell Routing to Improve Manufacturability (2017) (0)
- Hardware Synthesis for Asynchronous Communications Mechanisms (2008) (0)
- Unified (A)Synchronous Circuit Development (2019) (0)
- Guest Editorial: Special Section on Asynchronous Circuits and Systems (2009) (0)
- Mix & Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops (2023) (0)
- Generation of Synchronizing State Machines from a Transition System: A Region–Based Approach (2023) (0)
- A hierarchical mathematical model for automatic pipelining and allocation using elastic systems (2017) (0)
- Decomposition of transition systems into sets of synchronizing Free-choice Petri Nets (2022) (0)
- 1 Process Windows (2017) (0)
- Synthesis of Embedded Software for Reactive Systems (2002) (0)
- Maximum Throughput Loop Pipelining with Register Optimization Maximum Throughput Loop Pipelining with Register Optimization (1994) (0)
- Design and Prototyping of Digital Signal Processing (DSP) Systems: Introduction (1994) (0)
- Time elastic digital systems and Petri Nets (2008) (0)
- On the realization of reactive systems (2001) (0)
- Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking (2023) (0)
- Corrections to "Jutge.org: Characteristics and Experiences" (2019) (0)
- Networks of Elastic Circuits (2005) (0)
- Conservative Symbolic Model-checking of Petri Nets for Speed-independent Circuit Veriication Conservative Symbolic Model-checking of Petri Nets for Speed-independent Circuit Veriication (2007) (0)
- A concurrent model for de-synchronization ( Extended version of the paper presented at the International Workshop on Logic Synthesis 2003 ) (2003) (0)
- From Nets to Circuits and from Circuits to Nets (2019) (0)
- Tutorial Eight Logic Design of Asynchronous Circuits (2002) (0)
- A Symbolic Technique for the Efficient ATPG of Speed-Independent Circuits (2004) (0)
- Keynote Paper Elastic Circuits (2009) (0)
- Measuring the tolerance of self-adaptive clocks to supply voltage noise (2011) (0)
- Register Optimization for Maximum Throughput Loop Pipelining (1995) (0)
- Session details: New frontiers in logic synthesis (2004) (0)
- Formal verification of a complex timed circuit : IPCMOS (2004) (0)
- Logic Design of Asynchronous Circuits (Tutorial Abstract) (2002) (0)
- Comments on 'Using cache mechanisms to exploit nonrefreshing DRAM's for on-chip memories' (1992) (0)
- CROSSTALK NOISE AVOIDANCE IN ASYNCHRONOUS (2007) (0)
- Cover Approximations for the Synthesis of Speed-Independent Circuits (2007) (0)
- Fast Energy-Optimal Multikernel DNN-Like Application Allocation on Multi-FPGA Platforms (2021) (0)
- Decomposition of Speed-Independent Circuits (1999) (0)
- Optimal exploration of the unrolling degree for software pipelining (1999) (0)
- Programming 1 and sustainability (2022) (0)
- Computing the full quotient in bi-decomposition by approximation (2020) (0)
- Logic decomposition of incompletely specified functions (2001) (0)
- Multi-Clustering Net Model for Placement Algorithms (2008) (0)
- Transistor-Level Fault Detection Based on PowerConsumptionGianluca Cornetta (1997) (0)
- Chairmen's introduction (1993) (0)
- Session B2: Processor Architecture II (1993) (0)
- Symbolic Petri Net AnalysisUsing Boolean (1997) (0)
- Region-based algorithms for process mining and synthesis of Petri nets (2009) (0)
- UNRET: A Transformation-based technique for software pipelining with resource constraints (1994) (0)
- Synthesis with Relative Timing (2002) (0)
- Analytical Models for Architectural Exploration of Many-core Chip Multiprocessors (2012) (0)
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