Josep Torrellas
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American computer scientist
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Josep Torrellascomputer-science Degrees
Computer Science
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Parallel Computing
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#31
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Computer Architecture
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Computer Science
Josep Torrellas's Degrees
- PhD Computer Science Stanford University
- Masters Computer Science Stanford University
- Bachelors Computer Science Polytechnic University of Catalonia
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Why Is Josep Torrellas Influential?
(Suggest an Edit or Addition)According to Wikipedia, Josep Torrellas is Professor and Willett Faculty Scholar in the Department of Computer Science and a research faculty for the Universal Parallel Computing Research Center at the University of Illinois Urbana–Champaign. Torrellas's research area is computer architecture, focusing on speculative multithreading, multiprocessor organization, integration of processors and memory, and architectural support for software debuggability and machine reliability. He has been involved in the Stanford DASH and the Illinois Cedar multiprocessor projects, and led the Illinois Aggressive COMA and FlexRAM Intelligent Memory projects.
Josep Torrellas's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects (2008) (419)
- Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors (2008) (342)
- Bulk Disambiguation of Speculative Threads in Multiprocessors (2006) (318)
- A Chip-Multiprocessor Architecture with Speculative Multithreading (1999) (299)
- ReVive: cost-effective architectural support for rollback recovery in shared-memory multiprocessors (2002) (295)
- False Sharing ans Spatial Locality in Multiprocessor Caches (1994) (250)
- Facelift: Hiding and slowing down aging in multicores (2008) (250)
- POSH: a TLS compiler that exploits program structure (2006) (246)
- BulkSC: bulk enforcement of sequential consistency (2007) (240)
- Cherry: Checkpointed early resource recycling in out-of-order microprocessors (2002) (237)
- DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Ef?ciently (2008) (213)
- Positional adaptation of processors: application to energy reduction (2003) (201)
- A framework for dynamic energy efficiency and temperature management (2000) (193)
- Architectural support for scalable speculative parallelization in shared-memory multiprocessors (2000) (187)
- Speculative synchronization: applying thread-level speculation to explicitly parallel applications (2002) (183)
- InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy (2018) (182)
- Using a user-level memory thread for correlation prefetching (2002) (180)
- ReEnact: using thread-level speculation mechanisms to debug data races in multithreaded codes (2003) (162)
- ReCycle:: pipeline adaptation to tolerate process variation (2007) (162)
- iWatcher: efficient architectural support for software debugging (2004) (153)
- FlexRAM: Toward an advanced Intelligent Memory system (1999) (149)
- Cache Telepathy: Leveraging Shared Resource Attacks to Learn DNN Architectures (2018) (143)
- AccMon: Automatically Detecting Memory-Related Bugs via Program Counter-Based Invariants (2004) (135)
- An efficient implementation of tree-based multicast routing for distributed shared-memory multiprocessors (1996) (135)
- Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing (2007) (120)
- Capo: a software-hardware interface for practical deterministic multiprocessor replay (2009) (119)
- The memory performance of DSS commercial workloads in shared-memory multiprocessors (1997) (114)
- Attack Directories, Not Caches: Side Channel Attacks in a Non-Inclusive World (2019) (112)
- Speculative Taint Tracking (STT): A Comprehensive Protection for Speculatively Accessed Data (2019) (110)
- Characterizing the caching and synchronization performance of a multiprocessor operating system (1992) (109)
- Runnemede: An architecture for Ubiquitous High-Performance Computing (2013) (102)
- The Augmint multiprocessor simulation toolkit for Intel x86 architectures (1996) (102)
- SigRace: signature-based data race detection (2009) (101)
- Blueshift: Designing processors for timing speculation from the ground up. (2009) (98)
- Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation (2005) (98)
- Secure hierarchy-aware cache replacement policy (SHARP): Defending against cache-based side channel attacks (2017) (97)
- EVAL: Utilizing processors with variation-induced timing errors (2008) (93)
- Eliminating squashes through learning cross-thread violations in speculative parallelization for multiprocessors (2002) (91)
- Hardware and software support for speculative execution of sequential binaries on a chip-multiprocessor (1998) (91)
- VARIUS-NTV: A microarchitectural model to capture the increased sensitivity of manycores to process variations at near-threshold voltages (2012) (91)
- Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking (2007) (91)
- Share Data Placement Optimizations to Reduce Multiprocessor Cache Miss Rates (1990) (90)
- Evaluating the Performance of Cache-Affinity Scheduling in Shared-Memory Multiprocessors (1995) (89)
- Using Register Lifetime Predictions to Protect Register Files against Soft Errors (2007) (88)
- Hardware for speculative run-time parallelization in distributed shared-memory multiprocessors (1998) (88)
- An efficient algorithm for the run-time parallelization of DOACROSS loops (1994) (87)
- Scalable Cache Miss Handling for High Memory-Level Parallelism (2006) (86)
- Data forwarding in scalable shared-memory multiprocessors (1995) (85)
- FlexRAM: toward an advanced intelligent memory system (1999) (84)
- Speeding up irregular applications in shared-memory multiprocessors: memory binding and group prefetching (1995) (84)
- Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors (2007) (82)
- ReViveI/O: efficient handling of I/O in highly-available rollback-recovery servers (2006) (80)
- L1 data cache decomposition for energy efficiency (2001) (79)
- Optimizing instruction cache performance for operating system intensive workloads (1995) (72)
- EnergySmart: Toward energy-efficient manycores for Near-Threshold Computing (2013) (71)
- The BubbleWrap many-core: Popping cores for sequential acceleration (2009) (71)
- Removing architectural bottlenecks to the scalability of speculative parallelization (2001) (69)
- Accurate and efficient filtering for the Intel thread checker race detector (2006) (68)
- CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging (2006) (65)
- BulkCompiler: High-performance Sequential Consistency through cooperative compiler and hardware support (2009) (62)
- Mosaic: Exploiting the spatial locality of process variation to reduce refresh energy in on-chip eDRAM modules (2014) (62)
- A direct-execution framework for fast and accurate simulation of superscalar processors (1998) (60)
- Reducing remote conflict misses: NUMA with remote cache versus COMA (1997) (59)
- Energy-efficient hybrid wakeup logic (2002) (59)
- Using Multiple Input, Multiple Output Formal Control to Maximize Resource Efficiency in Architectures (2016) (59)
- Architectures for Extreme-Scale Computing (2009) (58)
- Patching Processor Design Errors with Programmable Hardware (2007) (56)
- Hardware for speculative parallelization of partially-parallel loops in DSM multiprocessors (1999) (56)
- Tradeoffs in buffering memory state for thread-level speculation in multiprocessors (2003) (55)
- Flexible Snooping: Adaptive Forwarding and Filtering of Snoops in Embedded-Ring Multiprocessors (2006) (54)
- Refrint: Intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies (2013) (52)
- ReplayConfusion: Detecting cache-based covert channel attacks using record and replay (2016) (50)
- The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors (1999) (49)
- Programming the FlexRAM parallel intelligent memory system (2003) (49)
- Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors (2005) (49)
- Coping with Parametric Variation at Near-Threshold Voltages (2013) (48)
- Medium Access Control in Wireless Network-on-Chip: A Context Analysis (2018) (48)
- MicroScope: Enabling Microarchitectural Replay Attacks (2019) (47)
- Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware (2006) (46)
- Thread-Level Speculation on a CMP can be energy efficient (2005) (46)
- AtomTracker: A Comprehensive Approach to Atomic Region Inference and Violation Detection (2010) (45)
- Improving JavaScript performance by deconstructing the type system (2014) (45)
- Automatically mapping code on an intelligent memory architecture (2001) (44)
- Comparing the power and performance of Intel's SCC to state-of-the-art CPUs and GPUs (2012) (44)
- Cache-Only Memory Architectures (1999) (43)
- OrthoNoC: A Broadcast-Oriented Dual-Plane Wireless Network-on-Chip Architecture (2018) (43)
- Colorama: Architectural Support for Data-Centric Synchronization (2007) (43)
- Detailed characterization of a quad Pentium Pro server running TPC-D (1999) (42)
- CAVA: Using checkpoint-assisted value prediction to hide L2 misses (2006) (41)
- AutoPersist: an easy-to-use Java NVM framework based on reachability (2019) (41)
- Vulcan: Hardware Support for Detecting Sequential Consistency Violations Dynamically (2012) (39)
- Augmint - A Multiprocessor Simulation Environment for Intel x86 architectures (1996) (37)
- Instruction Prefetching of Systems Codes with Layout Optimized for Reduced Cache Misses (1996) (37)
- Benefits of cache-affinity scheduling in shared-memory multiprocessors: a summary (1993) (36)
- OpenSPARC : An Open Platform for Hardware Reliability Experimentation (2008) (36)
- VARIUS: A Model of Parameter Variation and Resulting Timing Errors for Microarchitects (2007) (36)
- Rebound: Scalable checkpointing for coherent shared memory (2011) (35)
- SWICH: A Prototype for Efficient Cache-Level Checkpointing and Rollback (2006) (34)
- PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection (2006) (34)
- The Bulk Multicore architecture for improved programmability (2009) (34)
- The impact of speeding up critical sections with data prefetching and forwarding (1996) (33)
- SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization (2008) (32)
- Two hardware-based approaches for deterministic multiprocessor replay (2009) (31)
- WeeFence: toward making fences free in TSO (2013) (31)
- Optimizing the Instruction Cache Performance of the Operating System (1998) (31)
- WiSync: An Architecture for Fast Synchronization through On-Chip Wireless Communication (2016) (31)
- Elastic Cuckoo Page Tables: Rethinking Virtual Memory Translation for Parallelism (2020) (31)
- Speculative interference attacks: breaking invisible speculation schemes (2020) (31)
- QuickRec: prototyping an intel architecture extension for record and replay of multithreaded programs (2013) (30)
- Scal-Tool: Pinpointing and Quantifying Scalability Bottlenecks in DSM Multiprocessors (1999) (29)
- Efficient and flexible architectural support for dynamic monitoring (2005) (28)
- Speculative Data-Oblivious Execution: Mobilizing Safe Prediction For Safe and Efficient Speculative Execution (2020) (28)
- FlexRAM: Toward an advanced Intelligent Memory system: A retrospective paper (2012) (28)
- Light64: Lightweight hardware support for data race detection during Systematic Testing of parallel programs (2009) (28)
- A clustered approach to multithreaded processors (1998) (28)
- Volition: scalable and precise sequential consistency violation detection (2013) (28)
- Energy-Efficient Thread-Level Speculation (2006) (27)
- Tangle: Route-oriented dynamic voltage minimization for variation-afflicted, energy-efficient on-chip networks (2014) (27)
- Replica: A Wireless Manycore for Communication-Intensive and Approximate Data (2019) (26)
- ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy Environment (2010) (26)
- Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication (2018) (26)
- The performance of the Cedar multistage switching network (1994) (26)
- SAVE: Sparsity-Aware Vector Engine for Accelerating DNN Training and Inference on CPUs (2020) (25)
- Architectural support for parallel reductions in scalable shared-memory multiprocessors (2001) (25)
- The Illinois Aggressive Coma Multiprocessor project (I-ACOMA) (1996) (25)
- Cyrus: unintrusive application-level record-replay for replay parallelism (2013) (25)
- CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction (2004) (25)
- Estimating the Performance Advantages of Relaxing Consistency in a Shared Memory Multiprocessor (1990) (24)
- PageForge: A Near-Memory Content-Aware Page-Merging Architecture (2017) (24)
- Speculative Locks: Concurrent Execution of Critical Sections in Shared-Memory Multiprocessors* (2004) (24)
- Profile-Based Energy Reduction for High-Performance Processors (2001) (23)
- Correlation Prefetching with a User-Level Memory Thread (2003) (23)
- Automatic Code Mapping on an Intelligent Memory Architecture (2001) (22)
- Xylem: Enhancing Vertical Thermal Conduction in 3D Processor-Memory Stacks (2017) (22)
- Distance-adaptive update protocols for scalable shared-memory multiprocessors (1996) (22)
- A Model for Timing Errors in Processors with Parameter Variation (2007) (22)
- Improving the performance of bristled CC-NUMA systems using virtual channels and adaptivity (1999) (21)
- Comparing data forwarding and prefetching for communication-induced misses in shared-memory MPs (1998) (21)
- iWatcher: simple, general architectural support for software debugging (2004) (21)
- Software trace cache (1999) (21)
- Threshold Voltage Variation Effects on Aging-Related Hard Failure Rates (2007) (21)
- RelaxReplay: record and replay for relaxed-consistency multiprocessors (2014) (20)
- A Near-Memory Processor for Vector, Streaming and Bit Manipulation Workloads (2005) (20)
- PageSeer: Using Page Walks to Trigger Page Swaps in Hybrid Memory Systems (2019) (20)
- Concurrency control with data coloring (2008) (19)
- Speculative Synchronization: Applying thread-level speculation to parallel applications (2002) (19)
- Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming (2006) (19)
- OmniOrder: Directory-based conflict serialization of transactions (2014) (19)
- Analysis of Critical Architectural and Program Parameters in a Hierarchical Shared Memory Multiprocessor (1990) (19)
- Replay debugging: Leveraging record and replay for program debugging (2014) (19)
- Pacman: Tolerating asymmetric data races with unintrusive hardware (2012) (18)
- SecDir: A Secure Directory to Defeat Directory Side-Channel Attacks (2019) (18)
- Yukta: Multilayer Resource Controllers to Maximize Efficiency (2018) (18)
- Designing Vertical Processors in Monolithic 3D (2019) (17)
- ScalCore: Designing a core for voltage scalability (2016) (17)
- A Chip-Multiprocessor Architecture with (1999) (16)
- Improving the data cache performance of multiprocessor operating systems (1996) (16)
- Analysis of critical architectural and programming parameters in a hierarchical (1990) (15)
- An empirical study of the effect of source-level loop transformations on compiler stability (2018) (15)
- Speculation Invariance (InvarSpec): Faster Safe Execution Through Program Analysis (2020) (15)
- A MAC protocol for Reliable Broadcast Communications in Wireless Network-on-Chip (2016) (15)
- Enhancing memory use in Simple Coma: Multiplexed Simple Coma (1998) (15)
- Inter-Disciplinary Research Challenges in Computer Systems for the 2020s (2018) (15)
- Toward a cost-effective DSM organization that exploits processor-memory integration (2000) (15)
- Proceedings of the 1st workshop on Architectural and system support for improving software dependability (2006) (14)
- Cache optimization for memory-resident decision support commercial workloads (1999) (14)
- Prototyping architectural support for program rollback using FPGAs (2005) (14)
- Dynamically detecting and tolerating IF-Condition Data Races (2014) (13)
- Smartapps, an application centric approach to high performance computing: compiler-assisted software and hardware support for reduction operations (2000) (13)
- InstantCheck: Checking the Determinism of Parallel Programs Using On-the-Fly Incremental Hashing (2010) (13)
- Executing Sequential Binaries on a Clustered Multithreaded Architecture with Speculation Support (1998) (13)
- Using an Adaptive HPC Runtime System to Reconfigure the Cache Hierarchy (2014) (13)
- Speeding Up SpMV for Power-Law Graph Analytics by Enhancing Locality & Vectorization (2020) (13)
- Illusionist: Transforming lightweight cores into aggressive cores on demand (2013) (13)
- BabelFish: Fusing Address Translations for Containers (2020) (13)
- μ Complexity : Estimating Processor Design Effort (2005) (12)
- Extreme-scale computer architecture: Energy efficiency from the ground up‡ (2013) (12)
- Defining a high-level programming model for emerging NVRAM technologies (2018) (12)
- Scheduling for HPC Systems with Process Variation Heterogeneity (2014) (12)
- FlexRAM Architecture Design Parameters (2002) (12)
- BulkSMT: Designing SMT processors for atomic-block execution (2012) (11)
- Optimization of instruction fetch for decision support workloads (1999) (11)
- Tangram: Integrated Control of Heterogeneous Computers (2019) (11)
- Speculative Synchronization: Programmability and Performance for Parallel Codes (2003) (11)
- Millimeter-Wave Propagation within a Computer Chip Package (2018) (11)
- Survive: Pointer-Based In-DRAM Incremental Checkpointing for Low-Cost Data Persistence and Rollback-Recovery (2017) (11)
- SparseTrain: Leveraging Dynamic Sparsity in Software for Training DNNs on General-Purpose SIMD Processors (2019) (11)
- Using software logging to support multiversion buffering in thread-level speculation (2003) (10)
- Positional processor adaptation: application to energy reduction (2003) (10)
- Record-Replay Architecture as a General Security Framework (2018) (10)
- One Protocol to Rule Them All: Wireless Network-on-Chip using Deep Reinforcement Learning (2021) (10)
- LORE: A loop repository for the evaluation of compilers (2017) (10)
- SCsafe: Logging sequential consistency violations continuously and precisely (2016) (9)
- CAP: Criticality analysis for power-efficient speculative multithreading (2007) (9)
- InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy (Corrigendum) (2019) (8)
- ShortCut: Architectural support for fast object access in scripting languages (2017) (8)
- Shield : Cost-Effective Soft-Error Protection for Register Files (2006) (8)
- Compiler support for data forwarding in scalable shared-memory multiprocessors (1999) (8)
- Are We Ready for High Memory-Level Parallelism ? (2006) (7)
- CASPAR: Breaking Serialization in Lock-Free Multicore Synchronization (2016) (7)
- FlexBulk: Intelligently forming atomic blocks in blocked-execution multiprocessors to minimize squashes (2011) (7)
- Speculative Parallel Execution of Loops with Cross-Iteration Dependences in DSM Multiprocessors (1997) (7)
- Report for the NSF Workshop on Cross ‐ layer Power Optimization and Management (2012) (7)
- Multiprocessor cache memory performance: characterization and optimization (1992) (7)
- Community Climate System Model (CCSM) (2011) (7)
- WiDir: A Wireless-Enabled Directory Cache Coherence Protocol (2021) (7)
- A Guide to Design MIMO Controllers for Architectures (2016) (6)
- Compiler Support for Software Cache Coherence (2016) (6)
- POSH: A Profiler-Enhanced TLS Compiler that Leverages Program Structure (2005) (6)
- Unified fine-granularity buffering of index and data: approach and implementation (2000) (6)
- Asymmetric Memory Fences: Optimizing Both Performance and Implementability (2015) (6)
- Adaptively Mapping Code in an Intelligent Memory Architecture (2000) (6)
- Opportunistic Beamforming in Wireless Network-on-Chip (2019) (6)
- An IRAM architecture for image analysis and pattern recognition (1998) (6)
- QuickCheck: using speculation to reduce the overhead of checks in NVM frameworks (2019) (6)
- Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips (2000) (6)
- Speeding up the memory hierarchy in Flat COMA multiprocessors (1997) (5)
- Graphite: optimizing graph neural networks on CPUs through cooperative software-hardware techniques (2022) (5)
- Design trade-offs in high-throughput coherence controllers (2003) (5)
- BulkCommit: Scalable and fast commit of atomic blocks in a lazy multiprocessor environment (2013) (5)
- Workshop on Advancing Computer Architecture Research ( ACAR-II ) Laying a New Foundation for IT : Computer Architecture for 2025 and Beyond (2011) (5)
- Fuzzy-Token: An Adaptive MAC Protocol for Wireless-Enabled Manycores (2021) (5)
- Speculative Taint Tracking (STT): A Formal Analysis (2019) (5)
- Understanding priority-based scheduling of graph algorithms on a shared-memory platform (2019) (5)
- Cflex: a programming language for the flexram intelligent memory architecture (2002) (5)
- Thrifty: An Exascale Architecture for Energy Proportional Computing (2014) (5)
- Comprehensive Hardware and Software Support for Operating Systems to Exploit (1999) (5)
- WearCore: A core for wearable workloads? (2016) (5)
- Draco: Architectural and Operating System Support for System Call Security (2020) (5)
- Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks (2016) (5)
- Biased reference counting: minimizing atomic operations in garbage collection (2018) (5)
- Sthira: A Formal Approach to Minimize Voltage Guardbands under Variation in Networks-on-Chip for Energy Efficiency (2017) (4)
- SparseTrain: Leveraging Dynamic Sparsity in Training DNNs on General-Purpose SIMD Processors (2019) (4)
- IEEE Symposium on Low-Power and High-Speed Chips (2011) (4)
- Second Workshop on Computer Architecture Evaluation Using Commercial Workloads (1999) (4)
- Chip multiprocessors with speculative multithreading: design for performance and energy efficiency (2004) (4)
- Parallel virtualized memory translation with nested elastic cuckoo page tables (2022) (4)
- Excel-NUMA: Toward Programmability, Simplicity, and High Performance (1999) (4)
- Reusable inline caching for JavaScript performance (2019) (4)
- Control Systems for Computing Systems: Making computers efficient with modular, coordinated, and robust control (2020) (4)
- Introductory user''s guide to the architect''s workbench tools (1988) (4)
- HetCore: TFET-CMOS Hetero-Device Architecture for CPUs and GPUs (2018) (4)
- An Updated Evaluation of ReCycle (2008) (4)
- Use IRAM for rasterization (1998) (3)
- International Conference on Parallel Architectures and Compilation Techniques, PACT '12, Minneapolis, MN, USA - September 19 - 23, 2012 (2012) (3)
- BulkCompactor: Optimized deterministic execution via Conflict-Aware commit of atomic blocks (2012) (3)
- Jamais vu: thwarting microarchitectural replay attacks (2021) (3)
- A Unified Approach to Speculative Parallelization of Loops in DSM Multiprocessors (2007) (3)
- Speculation, Thread-Level (2011) (3)
- Estimating design time for system circuits (2007) (3)
- Execution Dependence Extension (EDE): ISA Support for Eliminating Fences (2021) (3)
- DeAliaser: alias speculation using atomic region support (2013) (3)
- Workshop on Advancing Computer Architecture Research ( ACAR-1 ) Failure is not an Option : Popular Parallel Programming (2010) (3)
- LeadOut: Composing low-overhead frequency-enhancing techniques for single-thread performance in configurable multicores (2010) (3)
- How Processor-memory Integration Aaects the Design of Dsms 1 (1997) (3)
- Comparing the Performance of the DASH and Cedar Multiprocessors for Scientific Applications (1994) (3)
- Software Logging under Speculative Parallelization (2004) (3)
- Maya: Falsifying Power Sidechannels with Operating System Support (2019) (3)
- P-INSPECT: Architectural Support for Programmable Non-Volatile Memory Frameworks (2020) (3)
- A Brief Description of the NMP ISA and Benchmarks (2005) (3)
- Proceedings of the 44th Annual International Symposium on Computer Architecture (2012) (3)
- Parameter Variation at Near Threshold Voltage : The Power Efficiency versus Resilience Tradeoff (2013) (3)
- Architecting and Programming a Hardware-Incoherent Multiprocessor Cache Hierarchy (2016) (3)
- Prefetching in an Intelligent Memory Architecture Using a Helper Thread (2001) (3)
- How to build a useful thousand-core manycore system? (2009) (3)
- UniHeap: managing persistent objects across managed runtimes for non-volatile memory (2021) (3)
- Software Trace Cache for Commercial Applications (2002) (2)
- Exploiting Intelligent Memory for Database Workloads (2004) (2)
- Pinned loads: taming speculative loads in secure processors (2022) (2)
- This version contains an evaluation that is slightly update d and corrected from the version appearing at ISCA 2004. iWatcher: Efficient Architectural Support for Software Deb ugging (2004) (2)
- Structured Singular Value Control for Modular Resource Management in Multilayer Computers (2018) (2)
- Hardware for Speculative Reduction Parallelization and Optimization in DSM Multiprocessors (1999) (2)
- Cache coherence in embedded-ring multiprocessors (2007) (2)
- ReVive (2002) (2)
- Tangram (2019) (2)
- Replica (2019) (2)
- V-Combiner: speeding-up iterative graph processing on a shared-memory platform with vertex merging (2020) (2)
- Extreme-scale computer architecture (2016) (2)
- Exascale Hardware Architectures Working Group (2011) (2)
- MicroScope (2019) (2)
- Memory System Performance of a Database in a Shared-memory Multiprocessor (2007) (2)
- Dense dynamic blocks: optimizing SpMM for processors with vector and matrix units using machine learning techniques (2022) (2)
- Managing processor adaptation for energy reduction and temperature control (2002) (2)
- NoMap: Speeding-Up JavaScript Using Hardware Transactional Memory (2019) (2)
- Community Ice Code (CICE) (2011) (1)
- Empowering Software Debugging Through Architectural Support for Program Rollback (2005) (1)
- PROPOSES OUT-OF-ORDER TASK SPAWNING TO EXPLOIT MORE SOURCES OF SPECULATIVE TASK-LEVEL PARALLELISM . ENERGY-EFFICIENT THREAD-LEVEL (2006) (1)
- Binoculars: Contention-Based Side-Channel Attacks Exploiting the Page Walker (2022) (1)
- Efficient support for speculative tasking (2007) (1)
- Exploiting multiprocessor memory hierarchies for operating systems (1996) (1)
- Configurable, Highly Parallel Computer (2011) (1)
- Proceedings of the 23rd international conference on Parallel architectures and compilation (2014) (1)
- Maya: Using Formal Control to Obfuscate Power Side Channels (2021) (1)
- State Space Search (2011) (1)
- Architectural and compiler support to hide coherence misses in distributed shared-memory multiprocessors (1997) (1)
- An Direct-Execution Framework for Fast and Accurate Simulation of Superscalar Processors (1998) (1)
- T Thread-level Speculation (2011) (1)
- Speculative Multithreading Does not ( Necessarily ) Waste Energy Draft paper submitted for publication . November 6 , 2003 . Please keep confidential (2003) (1)
- Cloak: tolerating non-volatile cache read latency (2022) (1)
- Deploying Architectural Support for Software Defect Detection in Future Processors (1)
- Critical Sections (2011) (1)
- Designing Hardware that Supports Cycle-Accurate Deterministic Replay (2006) (1)
- MicroScope: Enabling Microarchitectural Replay Attacks (2020) (1)
- A Microarchitectural Model of Process Variation for Near-threshold Computing (2011) (1)
- WISE: Predicting the Performance of Sparse Matrix Vector Multiplication with Machine Learning (2023) (1)
- Maya: Falsifying Power Sidechannels with Dynamic Control (2019) (1)
- Techniques to address unreliability and variability of computing systems (2006) (1)
- Performance characterization and buffer memory optimization of database (2000) (1)
- Programming and Debugging Shared Memory Programs with Data Coloring (2008) (1)
- Designing a Robust Controller for Obfuscating a Computer’s Power (2021) (1)
- BabelFish: Fusing Address Translations for Containers (2021) (1)
- 6 Discussion and conclusions (2009) (1)
- Cluster File Systems (2011) (1)
- ShortCut (2017) (1)
- Techniques to Mitigate the Effects of Congenital Faults in Processors (2008) (1)
- SpanCoverage: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection (2005) (1)
- Speculative taint tracking (STT) (2021) (1)
- Session details: Session 1A: New Architectures (2018) (0)
- Session details: Speculative threading and parallelization (2009) (0)
- Proceedings of the 1st Workshop on Architectural and System Support for Improving Software Dependability, ASID 2006, San Jose, California, USA, October 21, 2006 (2006) (0)
- Memory-Efficient Hashed Page Tables (2023) (0)
- Session details: Productivity and debugging (2010) (0)
- Server Farm (2011) (0)
- Session details: Session 7B: Heterogeneous Architectures and Accelerators II (2016) (0)
- Software Logging under Speculative Parallelization Mar ı́a (2001) (0)
- Distributed Data Persistency (2021) (0)
- Special Topic: High Performance Computing Extreme-scale computer architecture (2016) (0)
- Graphite (2022) (0)
- Automatic Generation of Coherence Instructions for Software-Managed Multiprocessor Caches (2014) (0)
- Rapid Prototyping in Architecture Research using Hardware Hooks in COTS Systems (2006) (0)
- 2012 International Symposium on Computer Architecture Influential Paper Award (2012) (0)
- Millimeter wave wireless network on chip using deep reinforcement learning (2020) (0)
- Toward Extreme-Scale Processor Chips (2016) (0)
- Session details: Faults (2007) (0)
- Design of efficient simple coma architectures (2000) (0)
- Computer architecture education at the University of Illinois: current status and some thoughts (1996) (0)
- Session details: Parallelism I (2014) (0)
- Optimizing primary data caches for parallel scientific applications: the pool buffer approach (1996) (0)
- A Method for Hiding the Increased Non-Volatile Cache Read Latency (2021) (0)
- Maya: Using Formal Control to Obfuscate Power Side Channels (2022) (0)
- Lessons Learned During the Development of the CapoOne Deterministic Multiprocessor Replay System ∗ (2009) (0)
- SecDir (2019) (0)
- μManycore: A Cloud-Native CPU for Tail at Scale (2023) (0)
- Table of Contents: MICRO-39 2006 39 th Annual International Symposium on Microarchitecture (2006) (0)
- Session details: Session 7B: Heterogeneous Architectures and Accelerators II (2016) (0)
- Slower Compilation Times + Generates High Quality Code + Utilizes Profiling Information Optimizing Compiler Compiler Traits Baseline Compiler Optimizing Compiler Compilation Cycle (2019) (0)
- Session details: Session 7B: Heterogeneous Architectures and Accelerators II (2016) (0)
- SpecFaaS: Accelerating Serverless Applications with Speculative Function Execution (2023) (0)
- Session details: Parallelism I (2014) (0)
- SparseTrain (2020) (0)
- Session details: Session 6B: Testing and Tainting, Verification and Security (2015) (0)
- InvisiSpec (2019) (0)
- Reducing Remote Connict Misses: Numa with Remote Cache versus Coma 1 (1997) (0)
- Community Climate Model (CCM) (2011) (0)
- WISE (2023) (0)
- Untangle: A Principled Framework to Design Low-Leakage, High-Performance Dynamic Partitioning Schemes (2023) (0)
- Cloak (2022) (0)
- Jamais Vu: Thwarting Microarchitectural Replay Attacks Extended Abstract (2020) (0)
- List of the committees members (2011) (0)
- Session details: Parallelism I (2014) (0)
- Extreme scale computing: Challenges and opportunities (2010) (0)
- Multilayer Compute Resource Management with Robust Control Theory (2017) (0)
- Software trace cache (1999) (0)
- Making Parallel Programming Easy: Research Contributions from Illinois (2013) (0)
- Supernode Partitioning (2011) (0)
- Session details: Productivity and debugging (2010) (0)
- Session details: Speculative threading and parallelization (2009) (0)
- Jose Renau's Tenure-Track Application (2003) (0)
- Guest Editor's Introduction: Micro's Top Picks from Microarchitecture Conferences (2006) (0)
- M3T: Morphable Multithreaded Memory Tiles (2004) (0)
- Introduction to High-Performance Memory Systems (2004) (0)
- Session details: Session 6B: Testing and Tainting, Verification and Security (2015) (0)
- Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2006, New York, New York, USA, March 29-31, 2006 (2006) (0)
- Scalable Shared-Memory Architectures (2001) (0)
- 2012 IEEE COOL Chips XV (2012) (0)
- Special-Purpose Machines (2011) (0)
- Research Feature Cache-Only Memory Architectures (0)
- Computer architecture education at the University of Illinois (1998) (0)
- Snug: architectural support for relaxed concurrent priority queueing in chip multiprocessors (2020) (0)
- Programming the FlexRAM Intelligent Memory Architecture (0)
- TLS Chip Multiprocessors : Micro-Architectural Mechanisms for Fast Tasking with Out-of-Order Spawn (2003) (0)
- The Design Complexity of Program Undo Support in a General-Purpose Processor (2005) (0)
- Architectural techniques to mitigate the effect of spatial and temporal variations in processors (2008) (0)
- BLUE WATERS : APPLICATION-DRIVEN SYSTEM DESIGN FOR SUSTAINED PETASCALE PERFORMANCE (0)
- Many-Core Architecture for NTC: Energy Efficiency from the Ground Up (2016) (0)
- Defensive ML: Defending Architectural Side-channels with Adversarial Obfuscation (2023) (0)
- A μ − architectural Model of Process Variation for Near-Threshold Computing (2011) (0)
- Session details: Session 6B: Testing and Tainting, Verification and Security (2015) (0)
- Top Picks from the Computer Architecture Conferences of 2007 ......thi S Special Issue Represents the the Review Process (2007) (0)
- Cache-Only Memory Architecture (COMA) (2011) (0)
- Easing the programmer's burden does not compromise system performance or increase the complexity of hardware implementation. (2009) (0)
- Processor memory integration: how it affects scalable multiprocessors (1997) (0)
- Upcoming Architectural Advances in DSM Machines and Their Impact on Programmability (1999) (0)
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