Kaushik Roy

Kaushik Roy's AcademicInfluence.com Rankings

Kaushik Roy

Engineering

#1487

World Rank

#2183

Historical Rank

Electrical Engineering

#210

World Rank

#241

Historical Rank

engineering Degrees

Download Badge

Engineering

Kaushik Roy's Degrees

PhD Electrical Engineering Stanford University
Masters Electrical Engineering Stanford University

Why Is Kaushik Roy Influential?

(Suggest an Edit or Addition)

(See a Problem?)

Kaushik Roy's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits (2003) (2368)
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories (2000) (852)
Towards spike-based machine intelligence with neuromorphic computing (2019) (648)
Low-Power Digital Signal Processing Using Approximate Adders (2013) (641)
Low-Power CMOS VLSI Circuit Design (2000) (613)
Going Deeper in Spiking Neural Networks: VGG and Residual Architectures (2018) (528)
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS (2005) (502)
A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM (2007) (455)
Analysis and characterization of inherent application resilience for approximate computing (2013) (450)
A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS (2009) (446)
IMPACT: IMPrecise adders for low-power approximate computing (2011) (430)
Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks (1998) (402)
Leakage control with efficient use of transistor stacks in single threshold CMOS (1999) (334)
SALSA: Systematic logic synthesis of approximate circuits (2012) (328)
Robust subthreshold logic for ultra-low power operation (2001) (314)
Design and optimization of dual-threshold circuits for low-voltage low-power applications (1999) (312)
Impact of NBTI on the temporal performance degradation of digital circuits (2005) (306)
Reducing set-associative cache energy via way-prediction and selective direct-mapping (2001) (294)
Carbon-nanotube-based voltage-mode multiple-valued logic design (2005) (278)
Quality programmable vector processors for approximate computing (2013) (259)
MACACO: Modeling and analysis of circuits for approximate computing (2011) (249)
An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-caches (2001) (247)
Intrinsic leakage in low power deep submicron CMOS ICs (1997) (234)
Design and optimization of low voltage high performance dual threshold CMOS circuits (1998) (233)
AxNN: Energy-efficient neuromorphic systems using approximate computing (2014) (230)
PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference (2019) (230)
Low Voltage, Low Power VLSI Subsystems (2004) (225)
Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating (2009) (220)
A process-tolerant cache architecture for improved yield in nanoscale technologies (2005) (217)
Approximate computing and the quest for computing efficiency (2015) (216)
Enabling Spike-Based Backpropagation for Training Deep Neural Network Architectures (2019) (209)
Models and algorithms for bounds on leakage in CMOS circuits (1999) (202)
Ultra-low power digital subthreshold logic circuits (1999) (202)
A circuit-compatible model of ballistic carbon nanotube field-effect transistors (2004) (197)
Parameter Variation Tolerance and Error Resiliency: New Design Paradigm for the Nanoscale Era (2010) (196)
Computing in Memory With Spin-Transfer Torque Magnetic RAM (2017) (193)
Hardware Trojan Detection by Multiple-Parameter Side-Channel Analysis (2013) (192)
Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies (2006) (191)
Scalable effort hardware design: Exploiting algorithmic resilience for energy efficiency (2010) (186)
Modeling and optimization of fringe capacitance of nanoscale DGMOS devices (2005) (183)
Design of voltage-scalable meta-functions for approximate computing (2011) (181)
Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design (2012) (180)
Process variation in embedded memories: failure analysis and variation aware architecture (2005) (180)
Gate leakage reduction for scaled devices using transistor stacking (2003) (176)
Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning (2002) (172)
DRG-cache: a data retention gated-ground cache for low power (2002) (168)
Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis (2007) (168)
Diode-footed domino: a leakage-tolerant high fan-in dynamic circuit design style (2004) (166)
Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits (2006) (165)
Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits (2004) (163)
Spin-Based Neuron Model With Domain-Wall Magnets as Synapse (2012) (158)
Novel sizing algorithm for yield improvement under process variation in nanometer technology (2004) (158)
Magnetic Tunnel Junction Based Long-Term Short-Term Stochastic Synapse for a Spiking Neural Network with On-Chip STDP Learning (2016) (154)
Leakage Power Analysis and Reduction for Nanoscale Circuits (2006) (153)
Carbon Nanotube Electronics: Design of High-Performance and Low-Power Digital Circuits (2007) (150)
Circuit activity based logic synthesis for low power reliable operations (1993) (149)
Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives (2016) (148)
Multiple-parameter side-channel analysis: A non-invasive hardware Trojan detection approach (2010) (148)
Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor (1990) (146)
Substitute-and-simplify: A unified design paradigm for approximate and quality configurable circuits (2013) (146)
Low-power scan design using first-level supply gating (2005) (145)
QSERL: quasi-static energy recovery logic (2001) (144)
Tree-CNN: A hierarchical Deep Convolutional Neural Network for incremental learning (2018) (143)
Double gate-MOSFET subthreshold circuit for ultralow power applications (2004) (141)
Power-Aware Testing and Test Strategies for Low Power Devices (2008) (140)
Enabling Deep Spiking Neural Networks with Hybrid Conversion and Spike Timing Dependent Backpropagation (2020) (139)
TapeCache: a high density, energy efficient cache based on domain wall memory (2012) (139)
Proposal for an All-Spin Artificial Neural Network: Emulating Neural and Synaptic Functionalities Through Domain Wall Motion in Ferromagnets (2015) (139)
Computation sharing programmable FIR filter for low-power and high-performance applications (2004) (135)
A single-Vt low-leakage gated-ground cache for deep submicron (2003) (134)
KNACK: A hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque MRAM bit-cells (2011) (134)
A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications (2011) (129)
RMP-SNN: Residual Membrane Potential Neuron for Enabling Deeper High-Accuracy and Low-Latency Spiking Neural Network (2020) (129)
Training Deep Spiking Convolutional Neural Networks With STDP-Based Unsupervised Pre-training Followed by Supervised Fine-Tuning (2018) (128)
Statistical design and optimization of SRAM cell for yield enhancement (2004) (128)
A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS (2008) (125)
Conditional Deep Learning for energy-efficient and enhanced pattern recognition (2015) (124)
Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's (1999) (122)
Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective (2010) (122)
Magnetic Tunnel Junction Mimics Stochastic Cortical Spiking Neurons (2015) (122)
Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling (2003) (121)
SYCLOP: synthesis of CMOS logic for low power applications (1992) (121)
Ultra-low power DLMS adaptive filter for hearing aid applications (2001) (119)
Optimal body bias selection for leakage improvement and process compensation over different technology generations (2003) (118)
Significance driven computation: a voltage-scalable, variation-aware, quality-tuning motion estimator (2009) (117)
Design of power-efficient approximate multipliers for approximate artificial neural networks (2016) (117)
High-performance low-power CMOS circuits using multiple channel length and multiple oxide thickness (2000) (116)
Efficient Design of Micro-Scale Energy Harvesting Systems (2011) (116)
An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping (2006) (115)
X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories (2017) (115)
ASLAN: Synthesis of approximate sequential circuits (2014) (114)
Device optimization for digital subthreshold logic operation (2005) (113)
Deterministic clock gating for microprocessor power reduction (2003) (112)
Spin-Transfer Torque Memories: Devices, Circuits, and Systems (2016) (111)
Maximum power estimation for CMOS circuits using deterministic and statistic approaches (1996) (110)
CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation (2007) (109)
A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations (2005) (108)
Dynamic VTH Scaling Scheme for Active Leakage Power Reduction (2002) (107)
Device-Optimization Technique for Robust and Low-Power FinFET SRAM Design in NanoScale Era (2007) (106)
Datapath scheduling with multiple supply voltages and level converters (1997) (105)
Estimation Of Circuit Activity Considering Signal Correlations And Simultaneous Switching (1994) (103)
Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors (2002) (103)
Test challenges for deep sub-micron technologies (2000) (101)
Toward Fast Neural Computing using All-Photonic Phase Change Spiking Neurons (2018) (100)
Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy (2010) (100)
Encoding Neural and Synaptic Functionalities in Electron Spin: A Pathway to Efficient Neuromorphic Computing (2017) (100)
Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile (2005) (98)
Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance (2007) (97)
Reducing leakage in a high-performance deep-submicron instruction cache (2001) (95)
Asymmetric Drain Spacer Extension (ADSE) FinFETs for Low-Power and Robust SRAMs (2011) (95)
A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits (2006) (93)
Mixed-Vth (MVT) CMOS circuit design methodology for low power applications (1999) (93)
DWM-TAPESTRI - An energy efficient all-spin cache using domain wall shift based writes (2013) (93)
Future cache design using STT MRAMs for improved energy efficiency: Devices, circuits and architecture (2012) (92)
Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices (2007) (92)
NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution? (2008) (92)
Unsupervised regenerative learning of hierarchical features in Spiking Deep Networks for object recognition (2016) (91)
Process Variations and Process-Tolerant Design (2007) (91)
Modeling and estimation of failure probability due to parameter variations in nano-scale SRAMs for yield enhancement (2004) (91)
Deep Spiking Convolutional Neural Network Trained With Unsupervised Spike-Timing-Dependent Plasticity (2019) (91)
Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells (2014) (90)
Differential Current Switch Logic: A Low Power DCVS Logic Family (1995) (89)
Low voltage low power CMOS design techniques for deep submicron ICs (2000) (89)
Gradient Projection Memory for Continual Learning (2021) (89)
Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation (2010) (88)
Hybrid Spintronic-CMOS Spiking Neural Network With On-Chip Learning: Devices, Circuits and Systems (2015) (88)
Modeling of failure probability and statistical design of Spin-Torque Transfer Magnetic Random Access Memory (STT MRAM) array for yield enhancement (2008) (88)
Energy recovery circuits using reversible and partially reversible logic (1996) (87)
Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation (2003) (85)
Bit-Cell Level Optimization for Non-volatile Memories Using Magnetic Tunnel Junctions and Spin-Transfer Torque Switching (2012) (84)
Reliability Implications of Bias-Temperature Instability in Digital ICs (2009) (84)
Probabilistic Deep Spiking Neural Systems Enabled by Magnetic Tunnel Junction (2016) (84)
SPINDLE: SPINtronic Deep Learning Engine for large-scale neuromorphic computing (2014) (83)
Leakage power analysis and reduction: models, estimation and tools (2005) (83)
Physics-Based SPICE-Compatible Compact Model for Simulating Hybrid MTJ/CMOS Circuits (2013) (83)
Incremental Learning in Deep Convolutional Neural Networks Using Partial Network Sharing (2017) (82)
A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM (2007) (82)
Gabor filter assisted energy efficient fast learning Convolutional Neural Networks (2017) (82)
RESPARC: A reconfigurable and energy-efficient architecture with Memristive Crossbars for deep Spiking Neural Networks (2017) (79)
Process Variation Tolerant Low Power DCT Architecture (2007) (79)
A circuit model for carbon nanotube interconnects: comparative study with Cu interconnects for scaled technologies (2004) (78)
Low-power functionality enhanced computation architecture using spin-based devices (2011) (78)
Approximate storage for energy efficient spintronic memories (2015) (77)
Spin-Orbit Torque Induced Spike-Timing Dependent Plasticity (2014) (76)
The design and hardware implementation of a low-power real-time seizure detection algorithm (2009) (76)
Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits (2007) (76)
Roadmap on emerging hardware and technology for machine learning (2020) (75)
Software design for low power (1997) (74)
Process variation tolerant SRAM array for ultra low voltage applications (2008) (74)
POWERTEST: a tool for energy conscious weighted random pattern testing (1999) (73)
Digital Computation in Subthreshold Region for Ultralow-Power Operation: A Device–Circuit–Architecture Codesign Perspective (2010) (72)
DCG: deterministic clock-gating for low-power microprocessor design (2004) (72)
STDP-Based Pruning of Connections and Weight Quantization in Spiking Neural Networks for Energy-Efficient Recognition (2017) (72)
Approximate computing: An integrated hardware approach (2013) (72)
Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS (2007) (72)
Write-optimized reliable design of STT MRAM (2012) (71)
Scalable Effort Hardware Design (2014) (70)
Ultra-low-power DLMS adaptive filter for hearing aid applications (2003) (70)
Robust ultra-low power sub-threshold DTMOS logic (2000) (69)
VSV: L2-miss-driven variable supply-voltage scaling for low power (2003) (69)
Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI (2006) (69)
Fast Tag Comparator Using Diode Partitioned Domino for 64-bit Microprocessors (2007) (69)
Perovskite nickelates as bio-electronic interfaces (2019) (68)
Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using IDDQ (2007) (68)
Habituation based synaptic plasticity and organismic learning in a quantum perovskite (2017) (68)
Maximum power point considerations in micro-scale solar energy harvesting systems (2010) (68)
8T SRAM Cell as a Multibit Dot-Product Engine for Beyond Von Neumann Computing (2018) (68)
Multilevel Spin-Orbit Torque MRAMs (2015) (67)
Layout-aware optimization of stt mrams (2012) (67)
Leakage power reduction in low-voltage CMOS designs (1998) (67)
STAG: Spintronic-Tape Architecture for GPGPU cache hierarchies (2014) (66)
Leakage in nano-scale technologies: mechanisms, impact and design considerations (2004) (66)
On-Chip Variability Sensor Using Phase-Locked Loop for Detecting and Correcting Parametric Timing Failures (2010) (65)
Voltage Scalable High-Speed Robust Hybrid Arithmetic Units Using Adaptive Clocking (2010) (65)
An All-Memristor Deep Spiking Neural Computing System: A Step Toward Realizing the Low-Power Stochastic Brain (2017) (65)
Analytical Subthreshold Potential Distribution Model for Gate Underlap Double-Gate MOS Transistors (2007) (65)
Spike-FlowNet: Event-based Optical Flow Estimation with Energy-Efficient Hybrid Neural Networks (2020) (65)
Synthesis of delay fault testable combinational logic (1989) (65)
Carbon Nanotube Field-Effect Transistors for High-Performance Digital Circuits—DC Analysis and Modeling Toward Optimum Transistor Structure (2006) (64)
Ultra low power associative computing with spin neurons and resistive crossbar memory (2013) (64)
A power macromodeling technique based on power sensitivity (1998) (64)
Multiplier-less Artificial Neurons exploiting error resiliency for energy-efficient neural computing (2016) (64)
DIET-SNN: Direct Input Encoding With Leakage and Threshold Optimization in Deep Spiking Neural Networks (2020) (64)
Statistical timing analysis using levelized covariance propagation (2005) (63)
Hierarchical Temporal Memory Based on Spin-Neurons and Resistive Memory for Energy-Efficient Brain-Inspired Computing (2014) (63)
Deep Spiking Neural Network: Energy Efficiency Through Time Based Coding (2020) (63)
A forward body-biased low-leakage SRAM cache: device and architecture considerations (2003) (62)
A Vision for All-Spin Neural Networks: A Device to System Perspective (2016) (62)
Estimation of switching noise on power supply lines in deep sub-micron CMOS circuits (2000) (62)
Roadmap of Spin–Orbit Torques (2021) (62)
A Low-Power SRAM Using Bit-Line Charge-Recycling (2007) (62)
Spin Orbit Torque Based Electronic Neuron (2014) (62)
Spin Neurons: A Possible Path to Energy-Efficient Neuromorphic Computers (2013) (61)
Efficient power conversion for ultra low voltage micro scale energy transducers (2010) (61)
Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance (2010) (60)
Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation (2005) (60)
Xcel-RAM: Accelerating Binary Neural Networks in High-Throughput SRAM Compute Arrays (2018) (60)
A graph theoretic approach for synthesizing very low-complexityhigh-speed digital filters (2002) (60)
A novel wavelet transform-based transient current analysis for fault detection and localization (2002) (58)
Asymmetrically Doped FinFETs for Low-Power Robust SRAMs (2011) (58)
Low-power design techniques for scaled technologies (2006) (58)
Decoupling capacitance allocation for power supply noise suppression (2001) (58)
SPICE Models for Magnetic Tunnel Junctions Based on Monodomain Approximation (2013) (58)
Double-gate SOI devices for low-power and high-performance applications (2005) (58)
Toward Scalable, Efficient, and Accurate Deep Spiking Neural Networks With Backward Residual Connections, Stochastic Softmax, and Hybridization (2019) (58)
Photonic In-Memory Computing Primitive for Spiking Neural Networks Using Phase-Change Materials (2019) (58)
A 85mV 40nW Process-Tolerant Subthreshold 8×8 FIR Filter in 130nm Technology (2007) (58)
DIET-SNN: A Low-Latency Spiking Neural Network With Direct Input Encoding and Leakage and Threshold Optimization. (2021) (57)
Statistical estimation of sequential circuit activity (1995) (57)
Band-to-Band Tunneling Ballistic Nanowire FET: Circuit-Compatible Device Modeling and Design of Ultra-Low-Power Digital Circuits and Memories (2009) (56)
Technology Aware Training in Memristive Neuromorphic Systems for Nonideal Synaptic Crossbars (2017) (56)
Complexity reduction of digital filters using shift inclusive differential coefficients (2004) (56)
Underlap DGMOS for digital-subthreshold operation (2006) (56)
Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ (2003) (55)
High-performance low-energy STT MRAM based on balanced write scheme (2012) (55)
Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement (2007) (54)
Dynamic effort scaling: Managing the quality-efficiency tradeoff (2011) (54)
Coupled Spin Torque Nano Oscillators for Low Power Neural Computation (2015) (53)
Proposal for a Leaky-Integrate-Fire Spiking Neuron Based on Magnetoelectric Switching of Ferromagnets (2016) (53)
Energy-Efficient Non-Boolean Computing With Spin Neurons and Resistive Memory (2014) (53)
Multiple-parameter CMOS IC testing with increased sensitivity for I/sub DDQ/ (2000) (53)
CSDC: a new complexity reduction technique for multiplierless implementation of digital FIR filters (2005) (53)
Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring (2005) (52)
Spin-Transfer Torque MRAMs for Low Power Memories: Perspective and Prospective (2012) (51)
Statistical Characterization and On-Chip Measurement Methods for Local Random Variability of a Process Using Sense-Amplifier-Based Test Structure (2007) (51)
SHE-NVFF: Spin Hall Effect-Based Nonvolatile Flip-Flop for Power Gating Architecture (2014) (51)
Highly reliable memory-based Physical Unclonable Function using Spin-Transfer Torque MRAM (2014) (51)
Estimation of inductive and resistive switching noise on power supply network in deep sub-micron CMOS circuits (2000) (51)
STT-SNN: A Spin-Transfer-Torque Based Soft-Limiting Non-Linear Neuron for Low-Power Artificial Neural Networks (2014) (51)
Speed binning aware design methodology to improve profit under parameter variations (2006) (50)
Carbon Nanotube Field-Effect Transistors for High-Performance Digital Circuits—Transient Analysis, Parasitics, and Scalability (2006) (50)
Variation-Aware Low-Power Synthesis Methodology for Fixed-Point FIR Filters (2009) (50)
GENIEx: A Generalized Approach to Emulating Non-Ideality in Memristive Xbars using Neural Networks (2020) (49)
Process-Variation Resilient and Voltage-Scalable DCT Architecture for Robust Low-Power Computing (2010) (49)
A twisted-bundle layout structure for minimizing inductive coupling noise (2000) (49)
Power reduction in test-per-scan BIST (2000) (49)
Accurate power estimation of CMOS sequential circuits (1996) (49)
Modeling and testing of SRAM for new failure mechanisms due to process variations in nanoscale CMOS (2005) (48)
RxNN: A Framework for Evaluating Deep Neural Networks on Resistive Crossbars (2018) (48)
Digital CMOS logic operation in the sub-threshold region (2000) (48)
DSH-MRAM: Differential Spin Hall MRAM for On-Chip Memories (2013) (47)
Circuit optimization for minimisation of power consumption under delay constraint (1995) (47)
Optimal selection of supply voltages and level conversions during data path scheduling under resource constraints (1996) (47)
System level DSP synthesis using voltage overscaling, unequal error protection & adaptive quality tuning (2009) (47)
Variation Tolerance in a Multichannel Carbon-Nanotube Transistor for High-Speed Digital Circuits (2009) (46)
Low-power process-variation tolerant arithmetic units using input-based elastic clocking (2007) (46)
FinFET SRAM - device and circuit design considerations (2004) (46)
Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits (2005) (46)
High-performance FIR filter design based on sharing multiplication (2003) (46)
Enabling Spike-based Backpropagation in State-of-the-art Deep Neural Network Architectures (2019) (45)
Impact of gate underlap on gate capacitance and gate tunneling current in 16 nm DGMOS devices (2004) (45)
In-Memory Low-Cost Bit-Serial Addition Using Commodity DRAM Technology (2020) (45)
Design Space Exploration of Hysteresis-Free HfZrOx-Based Negative Capacitance FETs (2017) (45)
Magnetic Skyrmion as a Spintronic Deep Learning Spiking Neuron Processor (2018) (45)
A feasibility study of subthreshold SRAM across technology generations (2005) (45)
Design and Synthesis of Ultralow Energy Spin-Memristor Threshold Logic (2014) (45)
Intrinsic leakage in deep submicron CMOS ICs-measurement-based test solutions (2000) (45)
Variation-tolerant Spin-Torque Transfer (STT) MRAM array for yield enhancement (2008) (45)
Numerical analysis of domain wall propagation for dense memory arrays (2011) (44)
Power sensitivity-a new method to estimate power dissipation considering uncertain specifications of primary inputs (1997) (44)
Self calibrating circuit design for variation tolerant VLSI systems (2005) (44)
An evaluation of system-level fault tolerance on the Intel hypercube multiprocessor (1988) (44)
ReStoCNet: Residual Stochastic Binary Convolutional Spiking Neural Network for Memory-Efficient Neuromorphic Computing (2019) (44)
Stochastic interconnect modeling, power trends, and performance characterization of 3-D circuits (2001) (44)
A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime (2003) (44)
Modeling of dielectric breakdown-induced time-dependent STT-MRAM performance degradation (2011) (43)
Sub-Domino logic: ultra-low power dynamic sub-threshold digital logic (2001) (43)
Effect of quantum confinement on spin transport and magnetization dynamics in dual barrier spin transfer torque magnetic tunnel junctions (2010) (43)
Proposal For Neuromorphic Hardware Using Spin Devices (2012) (43)
PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-Efficient ReRAM (2019) (43)
Power minimization by simultaneous dual-V/sub th/ assignment and gate-sizing (2000) (43)
On-chip interconnect modeling by wire duplication (2002) (42)
Micro-scale energy harvesting: A system design perspective (2010) (42)
GaSb-InAs n-TFET With Doped Source Underlap Exhibiting Low Subthreshold Swing at Sub-10-nm Gate-Lengths (2014) (42)
A novel on-chip delay measurement hardware for efficient speed-binning (2005) (42)
A Low Effort Approach to Structured CNN Design Using PCA (2018) (42)
A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking (2008) (42)
Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias (2008) (42)
Low-Overhead Maximum Power Point Tracking for Micro-Scale Solar Energy Harvesting Systems (2012) (42)
Approximate Computing: An Energy-Efficient Computing Technique for Error Resilient Applications (2015) (42)
The effect of process variation on device temperature in finFET circuits (2007) (41)
Data-retention flip-flops for power-down applications (2004) (41)
Energy-Efficient Neural Computing with Approximate Multipliers (2018) (41)
Low-power design using multiple channel lengths and oxide thicknesses (2004) (41)
A Three-Terminal Dual-Pillar STT-MRAM for High-Performance Robust Memory Applications (2011) (41)
IMAC: In-Memory Multi-Bit Multiplication and ACcumulation in 6T SRAM Array (2020) (40)
A low-power SRAM using bit-line charge-recycling technique (2008) (40)
Injection-Locked Spin Hall-Induced Coupled-Oscillators for Energy Efficient Associative Computing (2015) (40)
Gated-V/sub dd/: a circuit technique to reduce leakage in deep-submicron cache memories (2000) (40)
Enhancing yield at the end of the technology roadmap (2004) (40)
ASP: Learning to Forget With Adaptive Synaptic Plasticity in Spiking Neural Networks (2017) (39)
Energy recovery clocking scheme and flip-flops for ultra low-energy applications (2003) (39)
Numerical analysis of typical STT-MTJ stacks for 1T-1R memory arrays (2010) (39)
Statistical modeling of pipeline delay and design of pipeline under process variation to enhance yield in sub-100nm technologies (2005) (39)
Asymmetric halo CMOSFET to reduce static power dissipation with improved performance (2005) (39)
Spintastic: Spin-based stochastic logic for energy-efficient computing (2015) (38)
Computing approximately, and efficiently (2015) (38)
Exploring high bandwidth pipelined cache architecture for scaled technology (2003) (38)
AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture (2014) (38)
Stochastic Spiking Neural Networks Enabled by Magnetic Tunnel Junctions: From Nontelegraphic to Telegraphic Switching Regimes (2017) (38)
Inherent Adversarial Robustness of Deep Spiking Neural Networks: Effects of Discrete Input Encoding and Non-Linear Activations (2020) (38)
Short-Term Plasticity and Long-Term Potentiation in Magnetic Tunnel Junctions: Towards Volatile Synapses (2015) (37)
Soft-Error-Resilient FPGAs Using Built-In 2-D Hamming Product Code (2012) (37)
Analysis of Options in Double-Gate MOS Technology: A Circuit Perspective (2007) (37)
Boolean and non-Boolean computation with spin devices (2012) (37)
Fine-Grained Redundancy in Adders (2007) (37)
Prospects of Thin-Film Thermoelectric Devices for Hot-Spot Cooling and On-Chip Energy Harvesting (2013) (37)
FinFET Based SRAM Design for Low Standby Power Applications (2007) (37)
Image Edge Detection Based on Swarm Intelligence Using Memristive Networks (2016) (36)
Leakage and process variation effects in current testing on future CMOS circuits (2002) (36)
PVT-aware leakage reduction for on-die caches with improved read stability (2006) (36)
On Routability for FPGAs under Faulty Conditions (1995) (36)
Feasibility study of emerging non-volatilememory based physical unclonable functions (2014) (36)
A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array (2011) (36)
A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor (2006) (36)
High level test generation using data flow descriptions (1990) (36)
Proposal for Switching Current Reduction Using Reference Layer With Tilted Magnetic Anisotropy in Magnetic Tunnel Junctions for Spin-Transfer Torque (STT) MRAM (2012) (35)
Modeling and estimation of total leakage current in nano-scaled-CMOS devices considering the effect of parameter variation (2003) (35)
Analysis and design of ultra low power thermoelectric energy harvesting systems (2010) (35)
Ultra-Low Power Nanomagnet-Based Computing: A System-Level Perspective (2011) (35)
Neuromorphic computing enabled by physics of electron spins: Prospects and perspectives (2018) (35)
TraNNsformer: Neural network transformation for memristive crossbar based neuromorphic system design (2017) (35)
1T Non-Volatile Memory Design Using Sub-10nm Ferroelectric FETs (2018) (35)
Ising computation based combinatorial optimization using spin-Hall effect (SHE) induced stochastic magnetization reversal (2017) (34)
A CMOS thermal sensor and its applications in temperature adaptive design (2006) (34)
Leakage Power Dependent Temperature Estimation to Predict Thermal Runaway in FinFET Circuits (2006) (34)
Robust Level Converter for Sub-Threshold/Super-Threshold Operation:100 mV to 2.5 V (2011) (34)
Bayesian Multi-objective Hyperparameter Optimization for Accurate, Fast, and Efficient Neural Network Accelerator Design (2020) (34)
Spin neuron for ultra low power computational hardware (2012) (34)
BiCMOS fault models: is stuck-at adequate? (1990) (34)
Significance driven hybrid 8T-6T SRAM for energy-efficient synaptic storage in artificial neural networks (2016) (34)
ASAP: a transistor sizing tool for speed, area, and power optimization of static CMOS circuits (1994) (34)
Self–precharging flip–flop (SPFF): A new level converting flip–flop (2002) (33)
Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations (2005) (33)
Discretization Based Solutions for Secure Machine Learning Against Adversarial Attacks (2019) (33)
A novel synthesis approach for active leakage power reduction using dynamic supply gating (2005) (33)
Comprehensive Scaling Analysis of Current Induced Switching in Magnetic Memories Based on In-Plane and Perpendicular Anisotropies (2016) (33)
Low-power high-performance double-gate fully depleted SOI circuit design (2002) (33)
High performance and low power domino logic using independent gate control in double-gate SOI MOSFETs (2004) (33)
A low power four transistor Schmitt Trigger for asymmetric double gate fully depleted SOI devices (2003) (32)
A Low Complexity Reconfigurable DCT Architecture to Trade off Image Quality for Power Consumption (2008) (32)
Model reduction in the time-domain using Laguerre polynomials and Krylov methods (2002) (32)
Testing cross-talk induced delay faults in static CMOS circuit through dynamic timing analysis (2002) (32)
High performance and low power FIR filter design based on sharing multiplication (2002) (32)
Dynamic supply current testing of analog circuits using wavelet transform (2002) (31)
Frequency domain analysis of switching noise on power supply network (2000) (31)
Robust Level Converter Design for Sub-threshold Logic (2006) (31)
Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation (2009) (31)
Reliability- and Process-Variation Aware Design of VLSI Circuits (2007) (31)
Spin-Orbit-Torque-Based Spin-Dice: A True Random-Number Generator (2015) (31)
Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems (2012) (31)
Accurate modeling of transistor stacks to effectively reduce total standby leakage in nano-scale CMOS circuits (2003) (31)
Technology and circuit design considerations in quasi-planar double-gate SRAM (2006) (30)
CLIP: Circuit Level IC Protection Through Direct Injection of Process Variations (2012) (30)
High Performance and Energy-Efficient On-Chip Cache Using Dual Port (1R/1W) Spin-Orbit Torque MRAM (2016) (30)
A framework for simulating hybrid MTJ/CMOS circuits: Atoms to system approach (2012) (30)
Skewed CMOS: Noise-immune high-performance low-power static circuit family (2000) (30)
STAxCache: An approximate, energy efficient STT-MRAM cache (2017) (30)
Perovskite neural trees (2020) (30)
Combined circuit and architectural level variable supply-voltage scaling for low power (2005) (29)
STDP-based Unsupervised Feature Learning using Convolution-over-time in Spiking Neural Networks for Energy-Efficient Neuromorphic Computing (2018) (29)
A high density, carbon nanotube capacitor for decoupling applications (2006) (29)
On the energy benefits of spiking deep neural networks: A case study (2016) (29)
I/sub DDQ/ testing for deep-submicron ICs: challenges and solutions (2002) (29)
Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability (2006) (29)
An alternate design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective (2009) (29)
Skewed CMOS: noise-tolerant high-performance low-power static circuit family (2002) (29)
Multiple-V/sub dd/ multiple-V/sub th/ CMOS (MVCMOS) for low power applications (1999) (29)
Design of high performance sense amplifier using independent gate control in sub-50nm double-gate MOSFET (2005) (29)
Optimizating Emerging Nonvolatile Memories for Dual-Mode Applications: Data Storage and Key Generator (2015) (29)
Resistive Crossbars as Approximate Hardware Building Blocks for Machine Learning: Opportunities and Challenges (2020) (28)
Control of current saturation and threshold voltage shift in indium oxide nanowire transistors with femtosecond laser annealing. (2011) (28)
Analysis of Liquid Ensembles for Enhancing the Performance and Accuracy of Liquid State Machines (2019) (28)
Cache Design with Domain Wall Memory (2016) (28)
Magnetic tunnel junction enabled all-spin stochastic spiking neural network (2017) (28)
A design methodology and device/circuit/architecture compatible simulation framework for low-power Magnetic Quantum Cellular Automata systems (2009) (28)
Fault Detection and Location Using IDD Waveform Analysis (2001) (28)
Optimization of Surface Orientation for High-Performance, Low-Power and Robust FinFET SRAM (2006) (28)
Low Power Robust FinFET-Based SRAM Design in Scaled Technologies (2015) (28)
Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS (2004) (28)
A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application (2005) (28)
Non-adaptive and adaptive filter implementation based on sharing multiplication (2000) (28)
Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters (2006) (28)
Low-power design (2004) (27)
Constructing energy-efficient mixed-precision neural networks through principal component analysis for edge intelligence (2019) (27)
Stochastic wire-length and delay distributions of 3-dimensional circuits (2000) (27)
ABRM: Adaptive $ \beta$-Ratio Modulation for Process-Tolerant Ultradynamic Voltage Scaling (2010) (27)
A Comprehensive Analysis on Adversarial Robustness of Spiking Neural Networks (2019) (27)
Tri-Mode Independent Gate FinFET-Based SRAM With Pass-Gate Feedback: Technology–Circuit Co-Design for Enhanced Cell Stability (2013) (27)
Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current (2005) (27)
Stochastic Spin-Orbit Torque Devices as Elements for Bayesian Inference (2017) (27)
Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching (2008) (27)
StoRM: A Stochastic Recognition and Mining processor (2014) (27)
Tree-CNN: A Deep Convolutional Neural Network for Lifelong Learning (2018) (27)
Energy-Efficient and Improved Image Recognition with Conditional Deep Learning (2017) (27)
Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching (1996) (27)
Efficient embedded learning for IoT devices (2016) (27)
A New Paradigm for Low-power, Variation-Tolerant Circuit Synthesis Using Critical Path Isolation (2006) (26)
Reduced computational redundancy implementation of DSP algorithms using computation sharing vector scaling (2002) (26)
Spin-Transfer Torque Magnetic neuron for low power neuromorphic computing (2015) (26)
An Enhanced Voltage Programming Pixel Circuit for Compensating GB-Induced Variations in Poly-Si TFTs for AMOLED Displays (2014) (26)
A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET (2006) (26)
A leakage control system for thermal stability during burn-in test (2005) (26)
Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop (2007) (26)
Leakage in nanometer scale CMOS circuits (2003) (26)
Learning to Generate Sequences with Combination of Hebbian and Non-hebbian Plasticity in Recurrent Spiking Neural Networks (2017) (26)
Energy Efficient Neural Computing: A Study of Cross-Layer Approximations (2018) (25)
High-Density and Robust STT-MRAM Array Through Device/Circuit/Architecture Interactions (2015) (25)
Area-Efficient SOT-MRAM With a Schottky Diode (2016) (25)
Trifecta: A Nonspeculative Scheme to Exploit Common, Data-Dependent Subcritical Paths (2010) (25)
Optimization Of Channel Segmentation For Channelled Architecture FPGAs (1992) (25)
Dynamic noise analysis with capacitive and inductive coupling [high-speed circuits] (2002) (25)
Multi-level magnetic RAM using domain wall shift for energy-efficient, high-density caches (2013) (25)
Poly-Si Thin-Film Transistors: An Efficient and Low-Cost Option for Digital Operation (2007) (25)
Synthesis of application-specific highly efficient multi-mode cores for embedded systems (2005) (25)
Spintronic Switches for Ultralow Energy On-Chip and Interchip Current-Mode Interconnects (2013) (25)
Algorithms for low power FIR filter realization using differential coefficients (1997) (25)
A hardware-algorithm co-design approach to optimize seizure detection algorithms for implantable applications (2010) (25)
Device optimization for ultra-low power digital sub-threshold operation (2004) (25)
Highly Reliable Spin-Transfer Torque Magnetic RAM-Based Physical Unclonable Function With Multi-Response-Bits Per Cell (2015) (25)
Process-Tolerant Ultralow Voltage Digital Subthreshold Design (2008) (24)
Perspective: Stochastic magnetic devices for cognitive computing (2018) (24)
Integrated MEMS Switches for Leakage Control of Battery Operated Systems (2006) (24)
Integrated Systems in the More-Than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components (2010) (24)
A Graph-based Synthesis Algorithm For AND/XOR Networks (1997) (24)
A Circuit-Compatible Model of Ballistic Carbon (2004) (24)
A novel multiple-valued logic design using ballistic carbon nanotube FETs (2004) (24)
A novel physics-based variable NBTI simulation framework from small area devices to 6T-SRAM (2013) (24)
Algorithmic and architectural techniques for low-power digital signal processing (1999) (24)
Design methodology to trade off power, output quality and error resiliency: application to color interpolation filtering (2007) (24)
Circuit-compatible modeling of carbon nanotube FETs in the ballistic limit of performance (2003) (23)
R-MRAM: A ROM-Embedded STT MRAM Cache (2013) (23)
Exploring Spin Transfer Torque Devices for Unconventional Computing (2015) (23)
Test consideration for nanometer-scale CMOS circuits (2006) (23)
Device/circuit/architecture co-design of reliable STT-MRAM (2015) (23)
A low power reconfigurable DCT architecture to trade off image quality for computational complexity (2004) (23)
Leakage control for deep-submicron circuits (2003) (22)
Cascaded carry-select adder (C2SA): a new structure for low-power CSA design (2005) (22)
A fully physical model for leakage distribution under process variations in nanoscale double-gate CMOS (2006) (22)
SpiLinC: Spiking Liquid-Ensemble Computing for Unsupervised Speech and Image Recognition (2018) (22)
Low power reconfigurable DCT design based on sharing multiplication (2002) (22)
Dynamic noise analysis in precharge-evaluate circuits (2000) (22)
FinFET SRAM: Optimizing Silicon Fin Thickness and Fin Ratio to Improve Stability at iso Area (2007) (22)
Ultra low energy analog image processing using spin based neurons (2012) (22)
Organismic materials for beyond von Neumann machines (2020) (22)
Low power adder with adaptive supply voltage (2003) (22)
A soft error monitor using switching current detection (2005) (22)
COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits (1997) (22)
Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations (2005) (22)
Towards Understanding the Effect of Leak in Spiking Neural Networks (2020) (22)
Self-Consistent Approach to Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits (2007) (22)
Complimentary Polarizers STT-MRAM (CPSTT) for On-Chip Caches (2013) (22)
Characterization of Random Process Variations Using Ultralow-Power, High-Sensitivity, Bias-Free Sub-Threshold Process Sensor (2010) (21)
A Compact Physical Model for Yield Under Gate Length and Body Thickness Variations in Nanoscale Double-Gate CMOS (2006) (21)
Mixed Precision Quantization for ReRAM-based DNN Inference Accelerators (2021) (21)
Dual-edge triggered level converting flip-flops (2004) (21)
Peak power reduction in low power BIST (2000) (21)
Magnetic Tunnel Junction as an On-Chip Temperature Sensor (2017) (21)
Low Power Synthesis of Dynamic Logic Circuits Using Fine-Grained Clock Gating (2006) (21)
A 135mV 0.13μW process tolerant 6T subthreshold DTMOS SRAM in 90nm technology (2008) (21)
A leakage tolerant high fan-in dynamic circuit design technique (2001) (21)
Oxide Thickness Optimization for Digital Subthreshold Operation (2008) (20)
A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors (2009) (20)
A Three-Dimensional Physical Model for $V_{\rm th}$ Variations Considering the Combined Effect of NBTI and RDF (2011) (20)
Low-power carry-select adder using adaptive supply voltage based on input vector patterns (2004) (20)
Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM (2006) (20)
MESL: Proposal for a Non-volatile Cascadable Magneto-Electric Spin Logic (2016) (20)
Multiple scan chain design technique for power reduction during test application in BIST (2003) (20)
Memories in Scaled technologies: A Review of Process Induced Failures, Test methodologies, and Fault Tolerance (2007) (20)
FALCON: Feature Driven Selective Classification for Energy-Efficient Image Recognition (2016) (20)
Leakage Current in Deep-Submicron CMOS Circuits (2002) (20)
Controlled Forgetting: Targeted Stimulation and Dopaminergic Plasticity Modulation for Unsupervised Lifelong Learning in Spiking Neural Networks (2019) (20)
Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology (2011) (20)
STT-MRAMs for future universal memories: Perspective and prospective (2012) (20)
Estimation of sequential circuit activity considering spatial and temporal correlations (1995) (20)
Cognitive computing with spin-based neural networks (2012) (20)
Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology (2006) (20)
Power trends and performance characterization of 3-dimensional integration for future technology generations (2001) (20)
Profit Aware Circuit Design Under Process Variations Considering Speed Binning (2008) (20)
A compact SPICE model for statistical post-breakdown gate current increase due to TDDB (2013) (20)
An Optimal Algorithm for Low Power Multiplierless FIR Filter Design using Chebychev Criterion (2007) (20)
A 160 mV Robust Schmitt Trigger Based (2007) (20)
Device-Aware Yield-Centric Dual-$V_{t}$ Design Under Parameter Variations in Nanoscale Technologies (2007) (19)
Modeling and Design Space Exploration for Bit-Cells Based on Voltage-Assisted Switching of Magnetic Tunnel Junctions (2016) (19)
M2CA: Modular Memristive Crossbar Arrays (2018) (19)
Logic synthesis for reliability—an early start to controlling electromigration and hot carrier effects (1994) (19)
Low-power DWT-based quasi-averaging algorithm and architecture for epileptic seizure detection (2010) (19)
Unsupervised incremental STDP learning using forced firing of dormant or idle neurons (2016) (19)
Vertically integrated SOI circuits for low-power and high-performance applications (2002) (19)
Spike timing dependent plasticity based enhanced self-learning for efficient pattern recognition in spiking neural networks (2017) (19)
Containing the Nanometer “Pandora-Box”: Cross-Layer Design Techniques for Variation Aware Low Power Systems (2011) (19)
Design Space Exploration of Typical STT MTJ Stacks in Memory Arrays in the Presence of Variability and Disturbances (2011) (19)
Invited — Cross-layer approximations for neuromorphic computing: From devices to circuits and systems (2016) (19)
A Physics-Based Three-Dimensional Analytical Model for RDF-Induced Threshold Voltage Variations (2011) (19)
Generating true random numbers using on-chip complementary polarizer spin-transfer torque magnetic tunnel junctions (2014) (19)
A novel fault tolerant cache to improve yield in nanometer technologies (2004) (19)
Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput (2008) (19)
Novel low-overhead operand isolation techniques for low-power datapath synthesis (2006) (19)
Hardware-Software Co-Design for an Analog-Digital Accelerator for Machine Learning (2018) (19)
Designing approximate circuits using clock overgating (2016) (19)
In-Memory Computing in Emerging Memory Technologies for Machine Learning: An Overview (2020) (19)
Spin based neuron-synapse module for ultra low power programmable computational networks (2012) (19)
Write-Optimized STT-MRAM Bit-Cells Using Asymmetrically Doped Transistors (2014) (19)
A Physical Model for Grain-Boundary-Induced Threshold Voltage Variation in Polysilicon Thin-Film Transistors (2012) (19)
Magnetic Pattern Recognition Using Injection-Locked Spin-Torque Nano-Oscillators (2016) (18)
Transistor reordering for power minimization under delay constraint (1996) (18)
Spin-Hall Magnetic Random-Access Memory With Dual Read/Write Ports for On-Chip Caches (2015) (18)
Power supply noise aware floorplanning and decoupling capacitance placement (2002) (18)
Low-power weighted random pattern testing (2000) (18)
High-Density SOT-MRAM Based on Shared Bitline Structure (2018) (18)
Atomistic tight-binding based evaluation of impact of gate underlap on source to drain tunneling in 5 nm gate length Si FinFETs (2013) (18)
A process variation aware low power synthesis methodology for fixed-point FIR filters (2007) (18)
A new reduced-complexity sphere decoder with true lattice-boundary-awareness for multi-antenna systems (2005) (18)
Beyond charge-based computation: Boolean and non-Boolean computing with spin torque devices (2013) (18)
Exploring Spin-Transfer-Torque Devices for Logic Applications (2014) (18)
Area-Efficient Nonvolatile Flip-Flop Based on Spin Hall Effect (2018) (18)
Fast and accurate estimation of nano-scaled SRAM read failure probability using critical point sampling (2005) (18)
Magnonic Spin-Transfer Torque MRAM With Low Power, High Speed, and Error-Free Switching (2011) (18)
Scaling Deep Spiking Neural Networks with Binary Stochastic Activations (2019) (18)
PABO: Pseudo Agent-Based Multi-Objective Bayesian Hyperparameter Optimization for Efficient Neural Accelerator Design (2019) (18)
Area Efficient ROM-Embedded SRAM Cache (2013) (17)
A forward body-biased-low-leakage SRAM cache: device and architecture considerations (2003) (17)
Design of ultra high density and low power computational blocks using nano-magnets (2013) (17)
Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit design (2001) (17)
Column-selection-enabled 8T SRAM array with ∼1R/1W multi-port operation for DVFS-enabled processors (2011) (17)
Viterbi-Based Efficient Test Data Compression (2011) (17)
Robust high-performance low-power carry select adder (2003) (17)
A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited (2017) (17)
Convolutional Spike Timing Dependent Plasticity based Feature Learning in Spiking Neural Networks (2017) (17)
An 8×8 sub-threshold digital CMOS carry save array multiplier (2001) (17)
Photonic Spiking Neural Networks - From Devices to Systems (2018) (17)
Power consumption in XOR-based circuits (1999) (17)
Source-Underlapped GaSb–InAs TFETs With Applications to Gain Cell Embedded DRAMs (2016) (17)
Modeling and estimation of leakage in sub-90 nm devices (2004) (17)
Approximate Computing (2016) (17)
Energy-Delay Optimization of the STT MRAM Write Operation Under Process Variations (2014) (17)
Two's complement computation sharing multiplier and its applications to high performance DFE (2003) (17)
Ultra-thin dielectric breakdown in devices and circuits: A brief review (2015) (17)
Voltage over-scaling: A cross-layer design perspective for energy efficient systems (2011) (17)
A bounded search algorithm for segmented channel routing for FPGA's and associated channel architecture issues (1993) (16)
A leakage-tolerant high fan-in dynamic circuit design style [logic circuits] (2003) (16)
First level hold: a novel low-overhead delay fault testing technique (2004) (16)
Design of a Low-Voltage Analog-to-Digital Converter Using Voltage-Controlled Stochastic Switching of Low Barrier Nanomagnets (2018) (16)
Fusion-FlowNet: Energy-Efficient Optical Flow Estimation using Sensor Fusion and Deep Fused Spiking-Analog Network Architectures (2021) (16)
Design and synthesis of low power weighted random pattern generator considering peak power reduction (1999) (16)
Staged Inference using Conditional Deep Learning for energy efficient real-time smart diagnosis (2017) (16)
Fast and Disturb-Free Nonvolatile Flip-Flop Using Complementary Polarizer MTJ (2017) (16)
Biologically Plausible Ferroelectric Quasi-Leaky Integrate and Fire Neuron (2019) (16)
Gated Decap: gate leakage control of on-chip decoupling capacitors in scaled technologies (2005) (16)
Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation (2006) (16)
Modeling and analysis of carbon nanotube interconnects and their effectiveness for high speed VLSI design (2004) (16)
X-CHANGR: Changing Memristive Crossbar Mapping for Mitigating Line-Resistance Induced Accuracy Degradation in Deep Neural Networks (2019) (16)
A 45nm 48-core IA processor with variation-aware scheduling and optimal core mapping (2011) (16)
An On-Chip Test Structure and Digital Measurement Method for Statistical Characterization of Local Random Variability in a Process (2008) (15)
A novel approach to high-level switching activity modeling with applications to low-power DSP system synthesis (2001) (15)
Process variation in nano-scale memories: failure analysis and process tolerant architecture (2004) (15)
Stage number optimization for switched capacitor power converters in micro-scale energy harvesting (2011) (15)
DyReCTape: A dynamically reconfigurable cache using domain wall memory tapes (2015) (15)
Self-Repairing SRAM for Reducing Parametric Failures in Nanoscaled Memory (2006) (15)
Exploring the design of ultra-low energy global interconnects based on spin-torque switches (2013) (15)
SAVS: a self-adaptive variable supply-voltage technique for process-tolerant and power-efficient multi-issue superscalar processor design (2006) (15)
HERQULES: System level cross-layer design exploration for efficient energy-quality trade-offs (2010) (15)
Stochastic Inference and Learning Enabled by Magnetic Tunnel Junctions (2018) (15)
Low-power approximate convolution computing unit with domain-wall motion based “Spin-Memristor” for image processing applications (2016) (15)
Power reduction in test-per-scan BIST with supply gating and efficient scan partitioning (2005) (15)
Modeling and Analysis of Leakage Currents in Double-Gate Technologies (2006) (15)
Estimation of power dissipation using a novel power macromodelingtechnique (2000) (15)
Effectiveness of low power dual-V/sub t/ designs in nano-scale technologies under process parameter variations (2005) (15)
Energy efficient many-core processor for recognition and mining using spin-based memory (2011) (15)
Gradual Channel Pruning While Training Using Feature Relevance Scores for Convolutional Neural Networks (2020) (15)
One Timestep is All You Need: Training Spiking Neural Networks with Ultra Low Latency (2021) (15)
The Effects of Direct Source-to-Drain Tunneling and Variation in the Body Thickness on (100) and (110) Sub-10-nm Si Double-Gate Transistors (2015) (14)
Heterojunction Intra-Band Tunnel FETs for Low-Voltage SRAMs (2012) (14)
Computing with coupled Spin Torque Nano Oscillators (2016) (14)
Cross-Layer Design Exploration for Energy-Quality Tradeoffs in Spiking and Non-Spiking Deep Artificial Neural Networks (2018) (14)
Domain Wall Coupling-Based STT-MRAM for On-Chip Cache Applications (2015) (14)
Cascaded carry-select adder (C/sup 2/SA): a new structure for low-power CSA design (2005) (14)
STDP Based Unsupervised Multimodal Learning With Cross-Modal Processing in Spiking Neural Networks (2021) (14)
Design space exploration of FinFETs in sub-10nm technologies for energy-efficient near-threshold circuits (2013) (14)
An Accurate Analytical SNM Modeling Technique for SRAMs Based on Butterworth Filter Function (2007) (14)
Asymmetric Underlapped Sub-10-nm n-FinFETs for High-Speed and Low-Leakage 6T SRAMs (2016) (14)
Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis (2010) (14)
Tri-Mode Independent-Gate FinFETs for Dynamic Voltage/Frequency Scalable 6T SRAMs (2011) (14)
Analysis of SRAM and eDRAM Cache Memories Under Spatial Temperature Variations (2010) (14)
Dynamic Bit-width Adaptation in DCT: Image Quality versus Computation Energy Trade-off (2006) (14)
On Modeling and Evaluation of Logic Circuits under Timing Variations (2012) (14)
PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices (2009) (14)
Performance analysis and benchmarking of all-spin spiking neural networks (Special session paper) (2017) (14)
Power trends and performance characterization of 3-dimensional integration (2001) (14)
Analysis of Super Cut-off Transistors for Ultralow Power Digital Logic Circuits (2006) (14)
Bayesian-based Hyperparameter Optimization for Spiking Neuromorphic Systems (2019) (14)
Mimicking Leaky-Integrate-Fire Spiking Neuron Using Automotion of Domain Walls for Energy-Efficient Brain-Inspired Computing (2019) (14)
Quasi-static energy recovery logic and supply-clock generation circuits (1997) (14)
A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale Technologies (2006) (14)
Domino-Style Spin–Orbit Torque-Based Spin Logic (2015) (13)
A Scalable Circuit-Architecture Co-Design to Improve Memory Yield for High-Performance Processors (2010) (13)
Exploiting Inherent Error Resiliency of Deep Neural Networks to Achieve Extreme Energy Efficiency Through Mixed-Signal Neurons (2019) (13)
Performance estimation of molecular crossbar architecture considering capacitive and inductive coupling between interconnects (2003) (13)
Neural network accelerator design with resistive crossbars: Opportunities and challenges (2019) (13)
A Novel Approach to Accurate Timing Verification Using RTL Descriptions (1989) (13)
Design Methodology for Low Power and Parametric Robustness Through Output-Quality Modulation: Application to Color-Interpolation Filtering (2009) (13)
Non-Volatile Complementary Polarizer Spin-Transfer Torque On-Chip Caches: A Device/Circuit/Systems Perspective (2014) (13)
A low-power implantable event-based seizure detection algorithm (2009) (13)
A Self-Consistent Electrothermal Model for Analyzing NBTI Effect in p-Type Poly-Si Thin-Film Transistors (2013) (13)
SPARE: Spiking Neural Network Acceleration Using ROM-Embedded RAMs as In-Memory-Computation Primitives (2017) (13)
In-situ, In-Memory Stateful Vector Logic Operations based on Voltage Controlled Magnetic Anisotropy (2018) (13)
Designing Energy-Efficient Intermittently Powered Systems Using Spin-Hall-Effect-Based Nonvolatile SRAM (2017) (13)
A high performance IDDQ testable cache for scaled CMOS technologies (2002) (13)
Tolerance to Small Delay Defects by Adaptive Clock Stretching (2007) (13)
LVDCSL: a high fan-in, high-performance, low-voltage differential current switch logic family (1998) (13)
Switching characteristics of generalized array multiplier architectures and their applications to low power design (1999) (12)
High-level modeling of switching activity with application to low-power DSP system synthesis (1999) (12)
A power-aware GALS architecture for real-time algorithm-specific tasks (2005) (12)
Efficient Hybrid Network Architectures for Extremely Quantized Neural Networks Enabling Intelligence at the Edge (2019) (12)
Self-Repairing SRAM Using On-Chip Detection and Compensation (2010) (12)
Modeling and Evaluation of Topological Insulator/Ferromagnet Heterostructure-Based Memory (2016) (12)
Brain-inspired computing with spin torque devices (2014) (12)
High-performance low-power carry select adder using dual transition skewed logic (2001) (12)
Device/circuit interactions at 22nm technology node (2009) (12)
Domain wall motion-based low power hybrid spin-CMOS 5-bit Flash Analog Data Converter (2015) (12)
Estimation of NBTI Degradation using IDDQ Measurement (2007) (12)
On-chip energy harvesting using thin-film thermoelectric materials (2013) (12)
Ultralow Power Computing with Sub-threshold Leakage: A Comparative Study of Bulk and SOI Technologies (2006) (12)
Toward a spintronic deep learning spiking neural processor (2016) (12)
Computing-in-memory with spintronics (2018) (11)
Energy-efficient recognition and mining processor using scalable effort design (2013) (11)
Integrated Systems in the More-than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components (2016) (11)
Rx-Caffe: Framework for evaluating and training Deep Neural Networks on Resistive Crossbars (2018) (11)
Modeling, design and cross-layer optimization of polysilicon solar cell based micro-scale energy harvesting systems (2012) (11)
Energy-Efficient and Robust Associative Computing With Injection-Locked Dual-Pillar Spin-Torque Oscillators (2015) (11)
A model for leakage control by MOS transistlor stacking (1997) (11)
Proposal of an Intrinsic-Source Broken-Gap Tunnel FET to Reduce Band-Tail Effects on Subthreshold Swing: A Simulation Study (2016) (11)
Ultra Low-Power Algorithm Design for Implantable Devices: Application to Epilepsy Prostheses (2011) (11)
Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology (2014) (11)
Dynamically Resizable Instruction Cache: An Energy-Efficient and High-Performance Deep-Submicron Instruction Cache (2000) (11)
Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering (2010) (11)
Independent gate skewed logic in double-gate SOI technology (2005) (11)
Coupled Spin-Torque Nano-Oscillator-Based Computation (2017) (11)
Spiking Neural Networks with Improved Inherent Recurrence Dynamics for Sequential Learning (2021) (11)
The use of RTL descriptions in accurate timing verification and test generation (VLSI) (1991) (11)
Efficient modeling of 1/f/sup /spl alpha// noise using multirate process (2006) (11)
Novel Low Overhead Post-Silicon Self-Correction Technique for Parallel Prefix Adders Using Selective Redundancy and Adaptive Clocking (2011) (11)
Multijunction Fault-Tolerance Architecture for Nanoscale Crossbar Memories (2008) (11)
Spintronic devices for ultra-low power neuromorphic computation (Special session paper) (2016) (10)
Design and optimization of double-gate SOI MOSFETs for low voltage low power circuits (1998) (10)
Fault detection and diagnosis using wavelet based transient current analysis (2002) (10)
sBSNN: Stochastic-Bits Enabled Binary Spiking Neural Network With On-Chip Learning for Energy Efficient Neuromorphic Computing at the Edge (2020) (10)
Magnetic Tunnel Junction Enabled Stochastic Spiking Neural Networks: From Non-Telegraphic to Telegraphic Switching Regime (2017) (10)
Asymmetric underlapped FinFET based robust SRAM design at 7nm node (2015) (10)
Synthesizing Images From Spatio-Temporal Representations Using Spike-Based Backpropagation (2019) (10)
On effective I/sub DDQ/ testing of low voltage CMOS circuits using leakage control techniques (2000) (10)
IMPULSE: A 65-nm Digital Compute-in-Memory Macro With Fused Weights and Membrane Potential for Spike-Based Sequential Learning Tasks (2021) (10)
Device-Circuit Analysis of Double-Gate MOSFETs and Schottky-Barrier FETs: A Comparison Study for Sub-10-nm Technologies (2014) (10)
Iterative Wirability and Performance Improvement for FPGAs (1993) (10)
Laser Induced Magnetization Reversal for Detection in Optical Interconnects (2014) (10)
SUBTHRESHOLD LEAKAGE CONTROL BY MULTIPLE CHANNEL LENGTH CMOS (McCMOS) (1997) (10)
An Energy-Efficient High-Performance Deep-Submicron Instruction Cache (2001) (10)
A 35.5-127.2 TOPS/W Dynamic Sparsity-Aware Reconfigurable-Precision Compute-in-Memory SRAM Macro for Machine Learning (2021) (10)
Impact of SoC power management techniques on verification and testing (2009) (10)
A high sensitivity process variation sensor utilizing sub-threshold operation (2008) (10)
A 200mV to 1.2V, 4.4MHz to 6.3GHz, 48×42b 1R/1W programmable register file in 65nm CMOS (2007) (10)
Sensitivity analysis and optimization of thin-film thermoelectric coolers (2013) (10)
All‐Electric Nonassociative Learning in Nickel Oxide (2022) (10)
Underlap DGMOS for ultra-low power digital sub-threshold operation (2005) (10)
Managing the Quality vs. Efficiency Trade-off Using Dynamic Effort Scaling (2013) (10)
Exploring variability and reliability of multi-level STT-MRAM cells (2012) (10)
Energy-Efficient Memory Using Magneto-Electric Switching of Ferromagnets (2017) (10)
Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices (2007) (10)
SPACE: Structured Compression and Sharing of Representational Space for Continual Learning (2020) (10)
A Computational Redundancy Reduction Approach for High performaice and Low Power DSP Algorithm Implementation (1999) (10)
Thermal analysis of 8-T SRAM for nano-scaled technologies (2008) (10)
A coarse-grained FPGA architecture for high-performance FIR filtering (1998) (10)
Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling (2010) (9)
Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM (2005) (9)
Optimal UTB FD/SOI device structure using thin BOX for sub-50-nm SRAM design (2006) (9)
An XOR-Based Decomposition Diagram and Its Application in Synthesis of AND/XOR Networks (Special Section on VLSI Design and CAD Algorithms) (1997) (9)
Multi-Junction Fault Tolerance Architecture for Nanoscale Crossbar Memories (2006) (9)
Yield, Area, and Energy Optimization in STT-MRAMs Using Failure-Aware ECC (2015) (9)
Low-Power System for Detection of Symptomatic Patterns in Audio Biological Signals (2016) (9)
Efficient statistical approach to estimate power considering uncertain properties of primary inputs (1998) (9)
Dual pillar spin torque nano-oscillator (2013) (9)
A physical model to predict STT-MRAM performance degradation induced by TDDB (2013) (9)
Exploring Boolean and non-Boolean computing with spin torque devices (2013) (9)
Estimation of maximum power for sequential circuits considering spurious transitions (1997) (9)
Compact thermal models for thermally aware design of VLSI circuits (2006) (9)
SOI-optimized 64-bit high-speed CMOS adder design (2002) (9)
Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications (2009) (9)
Spin-Torque Sensors for Energy Efficient High-Speed Long Interconnects (2015) (9)
CASH-RAM: Enabling In-Memory Computations for Edge Inference Using Charge Accumulation and Sharing in Standard 8T-SRAM Arrays (2020) (9)
Circuit-aware Device Design Methodology for Nanometer Technologies: A Case Study for Low Power SRAM Design (2006) (9)
Synthesis of application-specific highly-efficient multi-mode systems for low-power applications (2003) (9)
A low-voltage, low power STDP synapse implementation using domain-wall magnets for spiking neural networks (2016) (9)
Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering (2004) (9)
Domain-Specific Many-core Computing using Spin-based Memory (2014) (9)
Low complexity FIR filters using factorization of perturbed coefficients (2001) (9)
Ultra-low Energy, High-Performance Dynamic Resistive Threshold Logic (2013) (9)
Approximate computing: enabling voltage over-scaling in multimedia applications (2011) (9)
Circuits and Architectures for In-Memory Computing-Based Machine Learning Accelerators (2020) (9)
Low-power robust complementary polarizer STT-MRAM (CPSTT) for on-chip caches (2013) (9)
Exploration of device-circuit interactions in FinFET-based memories for sub-15nm technologies using a mixed mode quantum simulation framework: Atoms to systems (2011) (9)
Modeling and Analysis of the Asymmetric Source/Drain Extension CMOS Transistors for Nanoscale Technologies (2008) (9)
Adaptive supply voltage technique for low swing interconnects (2004) (9)
Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits (2005) (9)
Computing with Spin-Transfer-Torque Devices: Prospects and Perspectives (2014) (9)
An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS (2005) (8)
A novel low-power scan design technique using supply gating (2004) (8)
Analysis of drain-to-body band-to-band tunneling in double gate MOSFET (2005) (8)
Modeling of ballistic carbon nanotube field effect transistors for efficient circuit simulation (2003) (8)
Low-Energy Two-Stage Algorithm for High Efficacy Epileptic Seizure Detection (2015) (8)
An adaptive window-based susceptance extraction and its efficient implementation (2003) (8)
O2C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors (2008) (8)
Nano-switch for study of gold contact behavior (2009) (8)
Energy-Efficient All-Spin Cache Hierarchy Using Shift-Based Writes and Multilevel Storage (2015) (8)
A self-consistent model to estimate NBTI degradation and a comprehensive on-line system lifetime enhancement technique (2010) (8)
Double gate MOSFET subthreshold logic for ultra-low power applications (2003) (8)
Optimizing computations in a transposed direct form realization of Floating-Point LTI-FIR systems (1997) (8)
Ultra Low Energy Computing Using Adiabatic Switching Principle (1995) (8)
Logic Synthesis of Approximate Circuits (2020) (8)
A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points (2005) (8)
Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability (2005) (8)
Memory-based embedded digital ATE (2011) (8)
Double-gate MOSFETs with aymmetric drain underlap: A device-circuit co-design and optimization perspective for SRAM (2009) (8)
Technology Aware Training in Memristive Neuromorphic Systems based on non-ideal Synaptic Crossbars (2017) (8)
Embedding Read-Only Memory in Spin-Transfer Torque MRAM-Based On-Chip Caches (2016) (8)
Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors (2005) (8)
Ultra-High Density, High-Performance and Energy-Efficient All Spin Logic (2013) (8)
Energy-Efficient Object Detection Using Semantic Decomposition (2015) (8)
Ultra-Low power neuromorphic computing with spin-torque devices (2013) (8)
Optimal Spacing of Carbon Nanotubes in a CNFET Array for Highest Circuit Performance (2006) (8)
Energy efficient computing using coupled Dual-Pillar Spin Torque Nano Oscillators (2013) (8)
Sub-10 nm FinFETs and tunnel-FETs: From devices to systems (2015) (8)
A novel design methodology for high performance and low power digital filters (1999) (8)
Accurate characterization of random process variations using a robust low-voltage high-sensitivity sensor featuring replica-bias circuit (2010) (8)
Analysis of Stability Degradation of SRAMs Using a Physics-Based PBTI Model (2014) (8)
A technique to reduce power and test application time in BIST (2004) (8)
In situ unsupervised learning using stochastic switching in magneto-electric magnetic tunnel junctions (2019) (7)
Device-Circuit Co-Optimization for Robust Design of FinFET-Based SRAMs (2013) (7)
Technology-circuit co-design in width-quantized quasi-planar double-gate SRAM (2005) (7)
High-Frequency Modeling of Poly-Si Thin-Film Transistors for Low-Cost RF Applications (2012) (7)
An activity-driven encoding scheme for power optimization in microprogrammed control unit (1999) (7)
Minimally redundant parallel implementation of digital filters and vector scaling (2000) (7)
PCA-driven Hybrid network design for enabling Intelligence at the Edge (2019) (7)
Design of deep sub-micron CMOS circuits (2003) (7)
Improved clock-gating control scheme for transparent pipeline (2010) (7)
Distance Computation Based on Coupled Spin-Torque Oscillators: Application to Image Processing (2020) (7)
Training Deep Spiking Neural Networks for Energy-Efficient Neuromorphic Computing (2020) (7)
Stochastic Modeling of Positive Bias Temperature Instability in High- $\kappa $ Metal Gate nMOSFETs (2014) (7)
Power Sensitivity-A New Method to Estimate Power ConsideringUncertain Speci cations of Primary Inputs (1997) (7)
Design of sigma-delta modulators with arbitrary transfer functions (2005) (7)
Robust low-power multi-terminal STT-MRAM (2013) (7)
Reinforcement Learning With Low-Complexity Liquid State Machines (2019) (7)
Statistical SBD Modeling and Characterization and Its Impact on SRAM Cells (2014) (7)
Dual pillar spin-transfer torque MRAMs for low power applications (2013) (7)
i-SRAM: Interleaved Wordlines for Vector Boolean Operations Using SRAMs (2020) (7)
Magnetoelectric oxide based stochastic spin device towards solving combinatorial optimization problems (2017) (7)
Approximate computing: Energy-efficient computing with good-enough results (2013) (7)
Data-dependant sense-amplifier flip-flop for low power applications (2010) (7)
Technology Circuit Co-Design for Ultra Fast InSb Quantum Well Transistors (2008) (7)
Process variation tolerant online current monitor for robust systems (2005) (7)
Self-healing design in deep scaled CMOS technologies (2011) (7)
A graph theoretic approach for design and synthesis of multiplierless FIR filters (1999) (7)
Fault-Tolerance with Graceful Degradation in Quality: A Design Methodology and its Application to Digital Signal Processing Systems (2008) (7)
Power dissipation, variations and nanoscale CMOS design: Test challenges and self-calibration/self-repair solutions (2007) (7)
A time borrowing selectively clocked skewed logic for high-performance circuits in scaled technologies (2003) (7)
DSP data path synthesis for low-power applications (2001) (7)
Estimation of power sensitivity in sequential circuits with power macromodeling application (1998) (7)
A Low-Complexity Scan Reordering Algorithm for Low Power Test-Per-Scan BIST (2004) (7)
Neuromorphic learning with Mott insulator NiO (2021) (7)
DCT-SNN: Using DCT to Distribute Spatial Information over Time for Learning Low-Latency Spiking Neural Networks (2020) (7)
Explainable Learning: Implicit Generative Modelling during Training for Adversarial Robustness (2018) (7)
SRAMs in Scaled Technologies under Process Variations: Failure Mechanisms, Test & Variation Tolerant Design (2006) (7)
Design of Sigma–Delta Modulators With Arbitrary Transfer Functions (2007) (7)
Efficient generation of 1/f/sup /spl alpha// noise using a multi-rate filter bank (2003) (7)
Buffered Spin-Torque Sensors for Minimizing Delay and Energy Consumption in Global Interconnects (2017) (6)
Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current (2004) (6)
TraNNsformer: Clustered Pruning on Crossbar-Based Architectures for Energy-Efficient Neural Networks (2020) (6)
An All-Memristor Deep Spiking Neural Network: A Step Towards Realizing the Low Power, Stochastic Brain (2017) (6)
Variation-tolerant and self-repair design methodology for low temperature polycrystalline silicon liquid crystal and organic light emitting diode displays (2011) (6)
DeltaFrame-BP: An Algorithm Using Frame Difference for Deep Convolutional Neural Networks Training and Inference on Video Data (2018) (6)
Spatio-Temporal Pruning and Quantization for Low-latency Spiking Neural Networks (2021) (6)
TFT-LCD application specific low power SRAM using charge-recycling technique (2005) (6)
Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry (2008) (6)
Briefs Underlap DGMOS for Digital-Subthreshold Operation (2006) (6)
Dual Pillar Spin Transfer Torque MRAM with tilted magnetic anisotropy for fast and error-free switching and near-disturb-free read operations (2011) (6)
Spintronic switches for ultra low energy global interconnects (2014) (6)
Decision feedback equalizer with two's complement computation sharing multiplication (2001) (6)
Approximate computing for energy-efficient error-resilient multimedia systems (2013) (6)
Synthesis of selectively clocked skewed logic circuits (2002) (6)
A leakage-tolerant low-leakage register file with conditional sleep transistor (2004) (6)
Neuromorphic Computing Across the Stack: Devices, Circuits and Architectures (2018) (6)
Design and Comparative Analysis of Spintronic Memories Based on Current and Voltage Driven Switching (2018) (6)
EnsembleSNN: Distributed assistive STDP learning for energy-efficient recognition in spiking neural networks (2017) (6)
Interactive presentation: Process tolerant beta-ratio modulation for ultra-dynamic voltage scaling (2007) (6)
Design and Optimization of Spin-Transfer Torque MRAMs (2015) (6)
Proceedings of the 11th Great Lakes symposium on VLSI (2000) (6)
A physics-based statistical model for reliability of STT-MRAM considering oxide variability (2013) (6)
A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations (2005) (6)
Ising spin model using Spin-Hall Effect (SHE) induced magnetization reversal in Magnetic-Tunnel-Junction (2016) (6)
Design Methodology for Low Power Dissipation and Parametric Robustness through Output Quality Modulation : Application to Color Interpolation Filtering (6)
Purdue Nanoelectronics Research Laboratory Magnetic Tunnel Junction Model (2014) (6)
On the Intrinsic Robustness of NVM Crossbars Against Adversarial Attacks (2021) (6)
Spatial and Temporal Correlations (1995) (6)
Low field domain wall dynamics in artificial spin-ice basis structure (2015) (6)
Process Tolerant ß-ratio Modulation for Ultra-Dynamic Voltage Scaling (2007) (6)
Nano Spiral Inductors for Low-Power Digital Spintronic Circuits (2010) (6)
Thin-BOX Poly-Si Thin-Film Transistors for CMOS-Compatible Analog Operations (2011) (6)
Thermoelectric Spin-Transfer Torque MRAM With Fast Bidirectional Writing Using Magnonic Current (2013) (6)
Impact of body bias on delay fault testing of nanoscale CMOS circuits (2004) (6)
Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique (2008) (6)
Choice of flat-band voltage, V/sub DD/ and diameter of ambipolar Schottky-barrier carbon nanotube transistors in digital circuit design (2004) (5)
A novel low-complexity method for parallel multiplierless implementation of digital FIR filters (2005) (5)
A generic and reconfigurable test paradigm using Low-cost integrated Poly-Si TFTs (2007) (5)
Timed pattern generation for noise-on-delay calculation (2002) (5)
True random number generation using voltage controlled spin-dice (2016) (5)
Stimulating STDP to Exploit Locality for Lifelong Learning without Catastrophic Forgetting (2019) (5)
Implicit adversarial data augmentation and robustness with Noise-based Learning (2021) (5)
Power Dissipation Driven FPGA Place and Route Under Delay Constraints (1999) (5)
O2ABA: a novel high-performance predictable circuit architecture for the deep submicron era (2002) (5)
Self-Supervised Optical Flow with Spiking Neural Networks and Event Based Cameras (2021) (5)
Design of a novel three-valued static memory using Schottky barrier carbon nanotube FETs (2005) (5)
Accurate Modeling and Analysis of Currents in Trapezoidal FinFET Devices (2007) (5)
Device optimization for digital sub-threshold operation (2004) (5)
NLSTT-MRAM: Robust spin transfer torque MRAM using non-local spin injection for write (2012) (5)
Fast switching in CoTb based ferrimagnetic tunnel junction (2019) (5)
Noise analysis under capacitive and inductive coupling for high speed circuits (2002) (5)
Timed Input Pattern Generation for an Accurate Delay Calculation Under Multiple Input Switching (2010) (5)
Fast, low power evaluation of elementary functions using radial basis function networks (2017) (5)
Power Delivery for Nanoscale Processors with Single Wall Carbon Nanotube Interconnects (2006) (5)
Domain-wall shift based multi-level MRAM for high-speed, high-density and energy-efficient caches (2013) (5)
Novel Variation-Aware Circuit Design of Scaled LTPS TFT for Ultra low Power, Low-Cost Applications (2007) (5)
Dynamic bit-width adaptation in DCT (2006) (5)
LVDCSL: low voltage differential current switch logic, a robust low power DCSL family (1997) (5)
Modeling and analysis of gate leakage in ultra-thin oxide sub-50nm double gate devices and circuits (2005) (5)
Antiferroelectric Tunnel Junctions as Energy-Efficient Coupled Oscillators: Modeling, Analysis, and Application to Solving Combinatorial Optimization Problems (2020) (5)
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis (2005) (5)
On The Design of Adiabatic SRAMs (1996) (5)
Estimating Circuit Activity in Combinational CMOS Digital Circuits (2000) (5)
Stress Testing: A Low Cost Alternative for Burn-in (1997) (5)
Ultra-low Energy, High Performance and Programmable Magnetic Threshold Logic (2013) (5)
CASh: a novel "Clock As Shield" design methodology for noise immune precharge-evaluate logic (2001) (5)
Process-Tolerant Low-Power Adaptive Pipeline under Scaled-Vdd (2007) (5)
Dynamic noise model and its application to high speed circuit design (2002) (5)
Low power digital filters based on constrained least squares solution (1997) (5)
Data-Dependent Operation Speed-Up Through Automatically Inserted Signal Transition Detectors for Ultralow Voltage Logic Circuits (2014) (5)
Low-voltage process-adaptive logic and memory arrays for ultralow-power sensor nodes (2009) (5)
Neural Computing With Magnetoelectric Domain-Wall-Based Neurosynaptic Devices (2021) (5)
On complexity reduction of FIR digital filters using constrained least squares solution (1997) (5)
RF MEMS switches for leakage control in wireless handheld devices (2007) (4)
Variation-aware and self-healing design methodology for a system-on-chip (2012) (4)
Spin torques estimation and magnetization dynamics in dual barrier resonant tunneling penta-layer magnetic tunnel junctions (2010) (4)
Power Estimation Under Uncertain Delays (1998) (4)
P-channel Tunneling Field Effect Transistor (TFET): Sub-10nm technology enablement by GaSb-InAs with doped source underlap (2015) (4)
REDUCING GLITCHING AND LEAKAGE POWER IN LOW VOLTAGE CMOS CIRCUITS (1997) (4)
A low-power "near-threshold" epileptic seizure detection processor with multiple algorithm programmability (2012) (4)
Design of low power digital systems (1996) (4)
NBTI in n-Type SOI Access FinFETs in SRAMs and Its Impact on Cell Stability and Performance (2012) (4)
Accelerated BTI degradation under stochastic TDDB effect (2018) (4)
Exploring Boolean and Non-Boolean Computing Applications of Spin Torque Devices (2013) (4)
An 8×8 sub-threshold digital CMOS carry save array multiplier (2001) (4)
Selectively clocked CMOS logic style for low-power noise-immune operations in scaled technologies (2003) (4)
Low-power driven logic synthesis using accurate power estimation technique (1997) (4)
Dynamic Read Current Sensing With Amplified Bit-Line Voltage for STT-MRAMs (2020) (4)
Scalability of Carbon Nanotube FET-based Circuits (2006) (4)
Statistical TDDB Degradation in Memory Circuits: Bit-Cells to Arrays (2016) (4)
On Robustness of Spin-Orbit-Torque Based Stochastic Sigmoid Neurons for Spiking Neural Networks (2019) (4)
Estimation of average switching power under accurate modeling of signal correlations (1998) (4)
RMP-SNNs: Residual Membrane Potential Neuron for Enabling Deeper High-Accuracy and Low-Latency Spiking Neural Networks (2020) (4)
An Energy-Efficient Mixed-Signal Neuron for Inherently Error-Resilient Neuromorphic Systems (2017) (4)
PETE : Purdue Emerging Technology Evaluator (2007) (4)
Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits (2006) (4)
RECache: ROM-Embedded 8-Transistor SRAM Caches for Efficient Neural Computing (2018) (4)
Exploring SOI device structures and interconnect architecures for 3-dimensional integration (2001) (4)
Spin-torque memristor based offset cancellation technique for sense amplifiers (2017) (4)
A Low-Cost Low-Noise Amplifier in Poly-Si TFT Technology (2014) (4)
A Quantum-Well Charge-Trap Synaptic Transistor With Highly Linear Weight Tunability (2020) (4)
Workload dependent evaluation of thin-film thermoelectric devices for on-chip cooling and energy harvesting (2014) (4)
Device-Circuit Cosimulation for Energy Efficiency in Sub-10-nm Gate Length Logic and Memory (2016) (4)
Signal Strength Based Switching Activity Modeling and Estimation for DSP Applications (2001) (4)
Neuromorphic Computing Enabled by Spin-Transfer Torque Devices (2016) (4)
Theory of Multi-tube Carbon Nanotube Transistors for High Speed Variation-Tolerant Circuits (2008) (4)
I/sub DD/ waveforms analysis for testing of domino and low voltage static CMOS circuits (1998) (4)
Energy-efficient MRAM access scheme using hybrid circuits based on spin-torque sensors (2013) (4)
RAMANN: in-SRAM differentiable memory computations for memory-augmented neural networks (2020) (4)
Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications (2001) (4)
Scaled LTPS TFTs for low-cost low-power applications (2011) (4)
Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology (2005) (4)
Towards ADC-Less Compute-In-Memory Accelerators for Energy Efficient Deep Learning (2022) (4)
Robustness Hidden in Plain Sight: Can Analog Computing Defend Against Adversarial Attacks? (2020) (4)
Analog Approach to Constraint Satisfaction Enabled by Spin Orbit Torque Magnetic Tunnel Junctions (2018) (4)
Nano-magnet based ultra-low power logic design using non-majority gates (2009) (4)
Magnetoresistive Circuits and Systems: Embedded Non-Volatile Memory to Crossbar Arrays (2021) (4)
Layout-driven architecture synthesis for high-speed digital filters (2006) (4)
Noise resilient leaky integrate-and-fire neurons based on multi-domain spintronic devices (2022) (3)
Exploring Spike-Based Learning for Neuromorphic Computing: Prospects and Perspectives (2021) (3)
Multi-Level Neuromorphic Devices Built on Emerging Ferroic Materials: A Review (2021) (3)
Spin torque nano-oscillator based Oscillatory Neural Network (2016) (3)
Voltage-Driven Domain-Wall Motion based Neuro-Synaptic Devices for Dynamic On-line Learning (2017) (3)
Insulator-Metal Transition Material Based Artificial Neurons: A Design Perspective (2020) (3)
High-Performance Device Optimization and Dual-VT Technology Options for DoubleGate FET (2007) (3)
"All Programmable SOC FPGA for networking and computing in big data infrastructure" (2014) (3)
Robust Detection of Bridge Defects in STT-MRAM Cells Under Process Variations (2018) (3)
Attention Tree: Learning Hierarchies of Visual Features for Large-Scale Image Recognition (2016) (3)
Enabling Robust SOT-MTJ Crossbars for Machine Learning using Sparsity-Aware Device-Circuit Co-design (2021) (3)
Power supply noise-aware scheduling and allocation for DSP synthesis (2005) (3)
Modeling and Estimation of Total Leakage in Scaled CMOS Logic Circuits (2003) (3)
Skyrmion Sensor-Based Low-Power Global Interconnects (2017) (3)
Significance driven computation on next-generation unreliable platforms (2011) (3)
Floorplan-aware low-complexity digital filter synthesis for low-power & high-speed (2004) (3)
High-performance low-power dual transition preferentially sized (DTPS) logic (2005) (3)
Simulation studies of an All-Spin Artificial Neural Network: Emulating neural and synaptic functionalities through domain wall motion in ferromagnets (2015) (3)
Circuit Techniques for Leakage Reduction (2018) (3)
Self-Consistent Transport-Magnetic Simulation and Benchmarking of Hybrid Spin-Torque Driven Magnetic Tunnel Junctions (MTJs) (2010) (3)
Dynamic V/sub t/ SRAM: a leakage tolerant cache memory for low voltage microprocessors (2002) (3)
Short-circuit power analysis of an inverter driving an RLC load (2001) (3)
Cache Memory Design With Magnetic Skyrmions in a Long Nanotrack (2019) (3)
Low power and compact mixed-mode signal processing hardware using spin-neurons (2013) (3)
Test consideration for nanometer scale CMOS circuits (2003) (3)
Numerical analysis of a novel MTJ stack for high readability and writability (2011) (3)
Reliability Implications of NBTI in Digital Integrated Circuits (2013) (3)
Compact models considering incomplete voltage swing in complementary metal oxide semiconductor circuits at ultralow voltages: A circuit perspective on limits of switching energy (2009) (3)
Conditionally Deep Hybrid Neural Networks Across Edge and Cloud (2020) (3)
Revisiting Stochastic Computing in the Era of Nanoscale Nonvolatile Technologies (2020) (3)
A physical 3-D analytical model for the threshold voltage considering RDF (2009) (3)
NAX: Co-Designing Neural Network and Hardware Architecture for Memristive Xbar based Computing Systems (2021) (3)
Implicit Generative Modeling of Random Noise during Training for Adversarial Robustness (2018) (3)
Larger-than-V/sub dd/ forward body bias in sub-0.5V nanoscale CMOS (2004) (3)
Büttiker Probe-Based Modeling of TDDB: Application to Dielectric Breakdown in MTJs and MOS Devices (2016) (3)
Neural Networks at the Edge (2019) (3)
Hyperparameter Optimization in Binary Communication Networks for Neuromorphic Deployment (2020) (3)
Control unit synthesis targeting low-power processors (1995) (3)
Object Detection using Semantic Decomposition for Energy-Efficient Neural Computing (2015) (3)
Topological semi-metal Na3Bi as efficient spin injector in current driven magnetic tunnel junction (2019) (3)
Stochastic Switching of SHE-MTJ as a Natural Annealer for Efficient Combinatorial Optimization (2017) (3)
TDDB in HfSiON/SiO2 dielectric stack: Büttiker probe based NEGF modeling, prediction and experiment (2017) (3)
Coping with Variations through System-Level Design (2009) (3)
MRPF: an architectural transformation for synthesis of high-performance and low-power digital filters (2003) (3)
Biased Random Walk Using Stochastic Switching of Nanomagnets: Application to SAT Solver (2018) (3)
Smart cameras everywhere: AI vision on edge with emerging memories (2019) (3)
Delay fault localization in test-per-scan BIST using built-in delay sensor (2006) (3)
Automatic synthesis of FPGA channel architecture for routability and performance (1994) (3)
Design and Test of Low Voltage CMOS Circuits (2001) (3)
Investigation of dependence between time-zero and time-dependent variability in high-κ NMOS transistors (2016) (3)
Editorial: Understanding and Bridging the Gap Between Neuromorphic Computing and Machine Learning (2021) (3)
Digital LDO with Time-Interleaved Comparators for Fast Response and Low Ripple (2015) (3)
Correction to "Complimentary polarizers STT-MRAM (CPSTT) for on-chip caches" [Feb 13 232-234] (2013) (3)
Guest Editors' Introduction: Low-Power VLSI Design (1994) (2)
BiCMOS logic testing (1994) (2)
High Q and High Tuning Range FinFET Based Varactors for Low Cost SoC Integration (2006) (2)
A non-volatile cascadable magneto-electric material implication logic (2017) (2)
Low Power Design Methodologies for Systems-on-Chips (1999) (2)
On Channel Architecture and Routability for FPGAs Under Faulty Conditions (1994) (2)
Low complexity digital signal processing system design techniques (2005) (2)
Semantic driven hierarchical learning for energy-efficient image classification (2017) (2)
Asymmetrical domain wall propagation in bifurcated PMA wire structure due to the Dzyaloshinskii-Moriya interaction (2017) (2)
Magnetic Skyrmions for Cache Memory (2017) (2)
Network Compression via Mixed Precision Quantization Using a Multi-Layer Perceptron for the Bit-Width Allocation (2021) (2)
A parametric approach for low energy wireless data communication [mobile multimedia computing/communication applications] (2004) (2)
Functional Read Enabling In-Memory Computations in 1Transistor—1Resistor Memory Arrays (2020) (2)
Technology and Circuit Design Considerations in (2006) (2)
7nm Si FinFET Models with Symmetric and Asymmetric Underlap for Circuit Simulations (2013) (2)
Robust and Cascadable Nonvolatile Magnetoelectric Majority Logic (2017) (2)
Channel architecture optimization for performance and routability of row-based FPGAs (1993) (2)
Ultra Low Energy Analog Signal Processing Using Spin Neurons Based on Nano Magnets (2012) (2)
Image segmentation with stochastic magnetic tunnel junctions and spiking neurons (2017) (2)
Simultaneous multiple-V/sub dd/ scheduling and allocation for partitioned floorplan (2004) (2)
Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies (2008) (2)
Using Graphical Models as Explanations in Deep Neural Networks (2019) (2)
Variation Tolerant Memories in sub-90 nm Technologies (2006) (2)
Effects of Deposition Process on Poly-Si Microscale Energy Harvesting Systems: A Simulation Study (2016) (2)
Leakage reduction in stacked sub-10nm double-gate MOSFETs (2015) (2)
Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors (2003) (2)
DyReCTape: a dy namically re configurable c ache using domain wall memory tape s (2015) (2)
Effectiveness of using supply voltage as back-gate bias in ground plane SOI MOSFET (2004) (2)
Low-Power and Process Variation Tolerant Memories in sub-90nm Technologies (2006) (2)
On reliable circuits and systems: how reliability considerations are reshaping oxide scaling, device geometry, and VLSI algorithm (2005) (2)
Synthesis of skewed logic circuits (2005) (2)
Very Low-Complexity Digital Filters Based On Computational Redundancy Reduction (1999) (2)
Correction: Corrigendum: Magnetic Tunnel Junction Mimics Stochastic Cortical Spiking Neurons (2017) (2)
Circuit modeling of carbon nanotube interconnects and their performance estimation in VLSI design (2004) (2)
Physics-Based Compact Modeling of Successive Breakdown in Ultrathin Oxides (2015) (2)
Low-Overhead Circuit Synthesis for Temperature Adaptation Using Dynamic Voltage Scheduling (2007) (2)
A new crosstalk noise model for DOMINO logic circuits (2003) (2)
Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Current (2)
Multiple-V/sub dd/ scheduling/allocation for partitioned floorplan (2003) (2)
Low-Power Design Techniques and Test Implications (2010) (2)
Powerline Communication for Enhanced Connectivity in Neuromorphic Systems (2019) (2)
Exploring Vicinal Risk Minimization for Lightweight Out-of-Distribution Detection (2020) (2)
Energy efficient computation using injection locked bias-field free spin-hall nano-oscillator array with shared heavy metal (2017) (2)
Prospects of efficient neural computing with arrays of magneto-metallic neurons and synapses (2016) (2)
Adaptive accelerated aging for 28 nm HKMG technology (2018) (2)
REad/access-preferred (REAP) SRAM - architecture-aware bit cell design for improved yield and lower VMIN (2009) (2)
All-Photonic Phase Change Spiking Neuron: Toward Fast Neural Computing using Light (2018) (2)
Nano-scaled SRAM thermal stability analysis using hierarchical compact thermal models (2008) (2)
Approximate computing for efficient information processing (2014) (2)
Low-Power Architecture for Epileptic Seizure Detection Based on Reduced Complexity DWT (2012) (2)
Functional analysis of circuits under timing variations (2012) (2)
Cryogenic Neuromorphic Hardware (2022) (2)
Analysis of Bridge Defects in STT-MRAM Cells Under Process Variations and a Robust DFT Technique for Their Detection (2018) (2)
Explicitly Trained Spiking Sparsity in Spiking Neural Networks with Backpropagation (2020) (2)
Ferroelectric FET Based Coupled-Oscillatory Network for Edge Detection (2021) (2)
Embracing Stochasticity to Enable Neuromorphic Computing at the Edge (2021) (2)
Realistic spin-FET performance assessment for reconfigurable logic circuits (2010) (2)
Exploring SOI device structures and interconnect architectures for low-power high-performance circuits (2002) (2)
Nanometer scale technologies: device considerations (2004) (2)
Effect of Dzyaloshinskii–Moriya Interaction at Ferrimagnet and Heavy Metal Interface (2019) (2)
Adaptive accelerated aging with 28nm HKMG technology (2017) (2)
Optimizing Oxide Thickness for Digital Sub-threshold Operation (2006) (2)
Energy Efficient and High Performance Current-Mode Neural Network Circuit using Memristors and Digitally Assisted Analog CMOS Neurons (2015) (2)
Energy efficient 'in memory' computing to enable decentralised service workflow composition in support of multi-domain operations (2021) (2)
NAX: neural architecture and memristive xbar based accelerator co-design (2022) (2)
Efficient synthesis of AND/XOR networks (1997) (2)
Optimal Selection of Supply Voltages and Level Conversions During Low Power Data Path Scheduling (1996) (2)
Process Variation Tolerant Online Current Monitor for Fault Immune Systems (2005) (2)
Erratum: Short-Term Plasticity and Long-Term Potentiation in Magnetic Tunnel Junctions: Towards Volatile Synapses [Phys. Rev. Applied 5, 024012 (2016)] (2017) (2)
MICRO-SCALE ENERGY HARVESTING (2012) (2)
Integer linear programming-based synthesis of skewed logic circuits (2003) (2)
RAMANN (2020) (2)
Design for burn-in test: A technique for burn-in thermal stability under die-to-die parameter variations (2009) (2)
Cyclic resistance change in perpendicularly magnetized Co/Ni nanowire induced by alternating current pulse injection (2017) (2)
Energy recovery clocked dynamic logic (2005) (2)
Stochastic Interconnect Modeling , Power Trends , and Performance Characterization of 3-Dimensional Circuits (2001) (2)
Technology/Circuit Co-Design for III-V FETs (2010) (1)
Computational Modeling of Negative Bias Temperature Instability ( NBTI ) for Reliability-aware VLSI Design (2005) (1)
Robust and high sensitivity biosensor using injection locked spin torque nano-oscillators (2015) (1)
A logic-aware layout methodology to enhance the noise immunity of domino circuits (2003) (1)
Optimal Dual-$V_{T}$ Design in Sub-100-nm PD/SOI and Double-Gate Technologies (2008) (1)
Column-selection-enabled 8T SRAM array with (2011) (1)
LALM: a logic-aware layout methodology to enhance the noise immunity of domino circuits (2003) (1)
Power analysis and design at system level (1997) (1)
Efficiency attacks on spiking neural networks (2022) (1)
Using Super Cut-off Carbon Nanotube Sleep Transistors in Silicon Based Low Power Digital Circuits (2006) (1)
HyperX: A Hybrid RRAM-SRAM partitioned system for error recovery in memristive Xbars (2022) (1)
TREND: Transferability based Robust ENsemble Design (2020) (1)
Editorial Special Issue on “Memory Devices and Technologies for the Next Decade” (2020) (1)
Relevant-features based Auxiliary Cells for Energy Efficient Detection of Natural Errors (2020) (1)
Design verification and robust design technique for cross-talk faults (2001) (1)
Digital Circuits with Carbon Nanotube Transistors (2007) (1)
Accurate and Accelerated Neuromorphic Network Design Leveraging A Bayesian Hyperparameter Pareto Optimization Approach (2021) (1)
Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates (2007) (1)
HBIST: An approach towards zero external test cost (2012) (1)
Design in the Nanometer Regime: Process Variation (2006) (1)
Learning Spatio-Temporal Representations Using Spike-Based Backpropagation (2018) (1)
POWER ESTIMATION AND SYNTHESIS FOR LOW POWER (2002) (1)
High power keeps cool (2004) (1)
Energy-Efficient Target Recognition using ReRAM Crossbars for Enabling On-Device Intelligence (2020) (1)
SPARE: Spiking Networks Acceleration Using CMOS ROM-Embedded RAM as an In-Memory-Computation Primitive. (2017) (1)
High Performance and Low Power Electronics on Flexible Substrate (2007) (1)
Implicit Generative Modeling of Random Noise during Training improves Adversarial Robustness (2019) (1)
6.3. SOFTWARE DESIGN FOR LOW POWER (1997) (1)
A process/device/circuit/system compatible simulation framework for poly-Si TFT based SRAM design (2013) (1)
On fault modeling and fault tolerance of antifuse based FPGAs (1993) (1)
Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes (2016) (1)
Invited Talk: Re-Engineering Computing with Neuro-Inspired Learning: Devices, Circuits, and Systems (2020) (1)
Guest editorial: low-power electronics and design (2000) (1)
Low-Power and Variation-Tolerant Application-Specific System Design (2011) (1)
INVITED : A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era (2017) (1)
Poly-Si Thin Film Transistors: Opportunities for low-cost RF applications (2012) (1)
On-Chip Non-volatile STT-MRAM for Zero-Standby Power (2017) (1)
Current mirror evaluation logic: A new circuit style for high fan–in dynamic gates (2002) (1)
Sense–amplifierless DCSL: A circuit style tolerant to floating body effects in PD/SOI (2002) (1)
Verifying Reliability (Dagstuhl Seminar 12341) (2012) (1)
Body Thickness Optimization and Sensitivity Analysis for High Performance FinFETs (2007) (1)
Estimating Area Efficiency of Antifuse based Channeled FPGA Architectures (1993) (1)
9nm GaSb-InAs TFET Models with Doped Source Underlap for Circuit Simulations (2014) (1)
Quantifying the Brain Predictivity of Artificial Neural Networks With Nonlinear Response Mapping (2020) (1)
A novel high-performance predictable circuit architecture for the deep sub-micron era (2000) (1)
VEDA: Variation-aware energy-efficient Discrete Wavelet Transform architecture (2010) (1)
Low Power Systems-on-Chip (2002) (1)
Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Model for CMOS Logic Gates with Scaled Supply Voltage (2007) (1)
A High Performance, Scalable Multiplexed Keeper Technique (2007) (1)
On The D esign of Adiabatic SRAM s (1996) (1)
Exploring Low Temperature Poly-Si for Low Cost and Low Power Sub-micron Digital Operation (2006) (1)
Implications of SiO/sub 2/ Breakdown in an Integrated Nanoscale Power Supply (2005) (1)
Brain-Inspired Computing: Adventure from Beyond CMOS Technologies to Beyond von Neumann Architectures ICCAD Special Session Paper (2021) (1)
Effectiveness of energy recovery techniques in reducing on-chip power density in molecular nano-technologies (2004) (1)
Dynamically Resizable Instruction Cache: A Design for an Energy-Efficient and High-Performance Deep-Submicron Instruction Cache (2000) (1)
Perovskite Quantum Organismoids (2017) (1)
Nonequilibrium Green’s Function and First-Principles Approach to Modeling of Multiferroic Tunnel Junctions (2019) (1)
MTL (2021) (1)
Convolving over time via recurrent connections for sequential weight sharing in neural networks (2017) (1)
Statistical Estimation of CMOS Circuit Activity under Probabilistic Delays (Special Section on VLSI Design and CAD Algorithms) (1997) (1)
Proposal for a Leaky Integrate Fire Spiking Neuron Using Voltage Driven Domain Wall Motion (2017) (1)
Exploiting Inherent Error-Resiliency of Neuromorphic Computing to achieve Extreme Energy-Efficiency through Mixed-Signal Neurons (2018) (1)
Leakage in nanometer scale CMOS circuits (2003) (1)
Automatic Synthesis Techniques for Approximate Circuits (2018) (1)
Tutorial: SoC Power Management Verification and Testing Issues (2008) (1)
An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs (2008) (1)
Optical Receiver With Helicity-Dependent Magnetization Reversal (2019) (1)
Thermoelectric Spin-Transfer Torque MRAM with Sub-Nanosecond Bi-Directional Writing using Magnonic Current (2011) (1)
Adaptive Supply Voltage for Low-Power Ripple-Carry and Carry-Select Adders (2007) (1)
Multiple Vth CMOS for Leakage Control in Deep Submicron IC's (1998) (1)
Structured test methodologies and test economics for multichip modules (1996) (1)
Digital and Analog-Mixed-Signal In-Memory Processing in CMOS SRAM (2019) (1)
Dopant straggle-free heterojunction intra-band tunnel (HIBT) FETs with low drain-induced barrier lowering/thinning (DIBL/T) and reduced variation in OFF current (2012) (1)
Integrated test solutions and test economics for MCMs (1995) (1)
Power VLSI Design/CAD (2005) (0)
Memory design for robust and energy-efficient computing systems (2013) (0)
Chaos-guided Input Structuring for Improved Learning in Recurrent Neural Networks (2017) (0)
Optical Receiver with Helicity Dependent Switching of Magnetization (2018) (0)
Self–precharging flip–flop (SPFF): A new level converting flip–flop (2002) (0)
Skewed CMOS: Noise-immune high-performance low-power static circuit family (2000) (0)
The Applicability of IDD Waveform Analysis to Testing of CMOS Circuits (1997) (0)
Mission-Specific Processing Techniques Enable Low-Power, High-Performance Surveillance Sensors (2004) (0)
Accurate and Eecient Technique to Calculate Sensitivities of Power to Uncertainties in Primary Inputs (2007) (0)
A Physical Model to Predict Grain Boundary Induced Transistor Threshold Voltage Variation in Poly-Si TFTs (2013) (0)
Design of CMOS Circuits in the Nanometer Regime: Leakage Tolerance (2006) (0)
(Invited) Spacer Thickness Optimization for FinFET-based Logic and Memories: A Device-Circuit Co-Design Approach (2013) (0)
Device-Circuit Co-design of FinFETs in Scaled Technologies (2012) (0)
Evaluating Opportunity and Effectiveness of Cache Resizing in Reducing Energy Dissipation (2001) (0)
Split gates: A low swing technique for reducing power for high fanout gates (1999) (0)
1 Optical Receiver with Helicity Dependent Magnetization Reversal (2019) (0)
Complexity Reduction of Digital Filters Using Shift (2004) (0)
Guest Editorial Advances in Design of Energy-Efficient Circuits and Systems (Second Issue) (2011) (0)
Timing Verification and Synthesis of Circuits for Delay Fault Testability (1990) (0)
T1: Low Power Design (1996) (0)
Accurate and Efficient Technique to Calculate Sensitivities of' Power to Primary Inputs (1996) (0)
Cross‐Hierarchy Design Exploration for Implantable Electronics (2014) (0)
Stochastic Quantization Using Magnetic Tunnel Junction Devices: A Simulation Study (2017) (0)
# 2001-001 Evaluating Opportunity and Effectiveness of Cache Resizing to Reduce Energy Dissipation (2000) (0)
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004 (2004) (0)
Accelerated variation simulation through parameter reduction (2013) (0)
T5: Low-Power Design (1997) (0)
Timed Pattern Generation for (2002) (0)
A SINGLE SHOT PCA-DRIVEN ANALYSIS OF NETWORK STRUCTURE TO REMOVE REDUNDANCY (2018) (0)
A cross-layer approach to cognitive computing: invited (2022) (0)
Editorial - Special Issue on Low-Power Arrays (2012) (0)
Minimizing ohmic loss in future processor IR events (2006) (0)
Low-Power and testable circuit synthesis using Shannon decomposition (2007) (0)
Efficient Neuromorphic Systems and Emerging Technologies: Prospects and Perspectives (2017) (0)
Editorial - special section: low-power systems-on-chip (2002) (0)
A HighDensity, CarbonNanotube Capacitor forDecoupling Applications (2006) (0)
Opt irnizat ion of Channel Segment at ion for Channelled Architecture FPGAs (1992) (0)
Power Diss ipat ion Driven F P G A Place and Route under De lay Constraints (0)
Aware Training in Memristive Neuromorphic Systems based on non-ideal Synaptic (2017) (0)
Efficient simulation of coded DS/CDMA over wireless personal communication channels (1996) (0)
Capacitively Driven Global Interconnect With Energy-Efficient Receiver Based on Magneto-Electric Switching (2018) (0)
Leakage grading of inputs to CMOS logic (1998) (0)
A Co-design view of Compute in-Memory with Non-Volatile Elements for Neural Networks (2022) (0)
Low power design under parameter variations (2008) (0)
Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor (2004) (0)
A hybrid spin-charge mixed-mode simulation framework for evaluating STT-MRAM bit-cells utilizing multiferroic tunnel junctions (2013) (0)
Computation Partitioning and Reuse for Power Efficient High Performance Digital Signal Processing (2007) (0)
Reward Modulated Spike Timing Dependent Plasticity Based Learning Mechanism in Spiking Neural Networks (2016) (0)
An Energy Efficient Set Associative Cache Algorithm (2019) (0)
Embedded tutorial: SoC Power Management Verification (2008) (0)
Accurate Power Estimation of Combinational CMOS Digital Circuits (2017) (0)
Performance and Wirability Driven Layout for Row-Based FPGAs (1998) (0)
Oscillatory Fourier Neural Network: A Compact and Efficient Architecture for Sequential Processing (2021) (0)
Erratum to "CASH-RAM: Enabling In-Memory Computations for Edge Inference Using Charge Accumulation and Sharing in Standard 8T-SRAM Arrays" (2020) (0)
Dual ferroelectric capacitor architecture and its application to TAG RAM (2010) (0)
Spin transfer torque memories for on-chip caches: Prospects and perspectives (2016) (0)
A new oscillator coupling function for improving the solution of graph coloring problem (2020) (0)
Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems (2011) (0)
RobustLevel Converter Design forSub-threshold Logic (2006) (0)
Evaluating the Stability of Recurrent Neural Models during Training with Eigenvalue Spectra Analysis (2019) (0)
Design in the nano-scale Era: Low-power, reliability, and error resiliency (2009) (0)
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001 (2001) (0)
Special Session 5A: Embedded Tutorial - Robust Design: Techniques and Trends (2008) (0)
Low Power SoC Design (2002) (0)
The international conference on computer-aided design 1989 (1990) (0)
Guest Editorial Computing in Emerging Technologies (Second Issue) (2015) (0)
A leakage-tolerant low-swing circuit style in partially depleted silicon-on-insulator CMOS technologies (2006) (0)
A Forward Body-Biased Low-Leakage SRAM Cache: Device and Arch i tect u re Cons iderat ions (2003) (0)
Keynote Talk 5 (2011) (0)
Multi-resistance states and neural learning with perovskite nickelates (2018) (0)
Improved current saturation and shifted switching threshold voltage in In2O3 nanowire based, fully transparent NMOS inverters via femtosecond laser annealing (2010) (0)
Spin as state variable for computation: prospects and perspectives (2012) (0)
Joint control of communication subsystems for low-energy image transmission (2005) (0)
Profit Aware Circuit Design Under Process Variations (2008) (0)
Impact of Leakage Power and Variation on Testing (2006) (0)
Variation in I ON and I OFF of transistors ( Source : Intel ) Coping With Variations Through System-level Design (2008) (0)
Automatic Test Reordering for Electrical and Thermal Stress during Monitored Burn-in (1994) (0)
Leakage Reduction for On-Die Caches (2005) (0)
Elst imat ion of Sequential Circuit Activity Considering Spatio-Temporal Correlations 1 (2013) (0)
Reading spin-torque memory with spin-torque sensors (2013) (0)
3 Circuit Techniques for Leakage Reduction Subthreshold Leakage @bullet Gate Leakage @bullet Source/substrate and Drain/substrate P-n Junction Leakage Dual Threshold Cmos @bullet Multiple Supply Voltage Leakage Control Using Transistor Stacks (self-reverse Bias) @bullet Sleep Transistor @bullet Vari (2005) (0)
Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits (2003) (0)
Relevant-features based Auxiliary Cells for Robust and Energy Efficient Deep Learning (2019) (0)
Extent of Variation Resilience in Strained CMOS: From Transistors to Digital Circuits (2017) (0)
An active suppression circuit for the reduction of di/dt event supply voltage variation (2008) (0)
Circuit Optimization for Mhimization of Power Consumption under Deliay Constraint (1995) (0)
Estimation of Maximum Power Spurious for Sequential Circuits Considering Transitions (1997) (0)
Leakage in Nano-Scale TeChndogieS: eChiPsliSsPaS, Impact and Design Considerations (2004) (0)
Tutorial T2C: Beyond von-Neumann Computing: Devices, Circuits, and Applications (2018) (0)
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005 (2005) (0)
Panel: SoC power management implications on validation and testing (2008) (0)
Capacitively Driven Global Interconnect with Magnetoelectric Switching Based Receiver for Higher Energy Efficiency (2018) (0)
Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of (2007) (0)
PowerDelivery forNanoscale Processors with Single WallCarbon Nanotube Interconnects (2015) (0)
Stochastic Switching of Nanomagnets for Post-CMOS Computing (2018) (0)
Enabling Homeostasis using Temporal Decay Mechanisms in Spiking CNNs Trained with Unsupervised Spike Timing Dependent Plasticity (2020) (0)
Design Space and Memory Technology Co-exploration for In-Memory Computing Based Machine Learning Accelerators (2022) (0)
2005IEEEDallas/CAS Workshop: Architecture, Circuits, andImplementation ofSoCs (2005) (0)
Soft Errors: System Effects, Protection Techniques and Case Studies (2008) (0)
ge Reduction in Stacked m Double-Gate MOSFET (2015) (0)
A NewParadigm forLow-power, Variation-Tolera nt Circuit Synthesis UsingCritical PathIsolation (2006) (0)
Energy-Efficient and Robust Associative Computing with Electrically Coupled Dual Pillar Spin-Torque Oscillators (2013) (0)
Reduction in Stacked Double-Gate MOSFET (2015) (0)
Ultra low voltage CMOS (2009) (0)
Purdue Emerging Technology Evaluator (2007) (0)
Tutorial Part 4: Low-Power Design (2004) (0)
Design and Performance Analysis of Low Power Multipliers (2020) (0)
A metric for analyzing effective on-chip inductive coupling (2003) (0)
Trim bit setting of analog filters using wavelet-based supply current analysis (2004) (0)
Spin-torque sensors with differential signaling for fast and energy efficient global interconnects (2017) (0)
Modeling and Simulation of Spin Transfer Torque Generated at Topological Insulator/Ferromagnetic Heterostructure (2015) (0)
Guest Editorial Computing in Emerging Technologies (First Issue) (2014) (0)
BASED ON SHARING MULTIPLICATION (2002) (0)
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, Chicago, Illinois, USA, March 2-4, 2000 (2000) (0)
Exploring Ultra Low-Power on-Chip Clocking Using Functionality Enhanced Spin-Torque Switches (2013) (0)
Minimizing Ohmic Loss and Supply Voltage Variation Using a Novel Distributed Power Supply Network (2006) (0)
26 The Reliability Challenge from Random Process Variability Induced Timing Errors (2012) (0)
In-Memory Computing based Machine Learning Accelerators: Opportunities and Challenges (2022) (0)
Biologically Plausible Class Discrimination Based Recurrent Neural Network Training for Motor Pattern Generation (2020) (0)
Integrated Design & Test: Conquering the Conflicting Requirements of Low-Power, Variation-Tolerance and Test Cost (2011) (0)
Circuit Optimization by Transistor Reordering for Minimization of Power Consumption under Delay Constraint (1993) (0)
Hardware/Software co-design with ADC-Less In-memory Computing Hardware for Spiking Neural Networks (2022) (0)
Concurrent Electro-Thermal Design of VLSI Circuits (2006) (0)
Efficient Communication Channel Utilization for Mapping FFT onto Mesh Array (2004) (0)
Algorithmic and architectural low-power techniques for digital signal processing and wireless communication applications (2005) (0)
Eecient Synthesis of Anddxor Networks (1996) (0)
A Low Power High Performance Multiplexed Keeper Technique (2006) (0)
NAX (2022) (0)
High Performance and Low Power Domino Logic Using Independent Gate Control in Double-Gate SO 1 MOSFETs (2008) (0)
Structured Learning for Action Recognition in Videos (2019) (0)
Power Constrained Test Scheduling with Low Power Weighted Random Testing (2001) (0)
Mixed-V/sub th/ (MVT) CMOS circuit design methodology for low power applications (1999) (0)
Low Power VLSI Signal Processing (2000) (0)
Leakage Reduction Techniques for Nanometer Scale CMOS Circuits (2003) (0)
On Power Reduction of FIR Digital Filters Using Constrained Least Squares Solution * (2013) (0)

This paper list is powered by the following services:

What Schools Are Affiliated With Kaushik Roy?

Kaushik Roy is affiliated with the following schools:

Purdue University