Kaustav Banerjee
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Electrical engineer
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Kaustav Banerjeeengineering Degrees
Engineering
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#2473
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Applied Physics
#816
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#838
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Electrical Engineering
#952
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#1027
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Engineering
Kaustav Banerjee's Degrees
- Bachelors Electrical Engineering Stanford University
- Masters Electrical Engineering Stanford University
- PhD Electrical Engineering Stanford University
Why Is Kaustav Banerjee Influential?
(Suggest an Edit or Addition)According to Wikipedia, Kaustav Banerjee is a professor of electrical and computer engineering and director of the Nanoelectronics Research Laboratory at the University of California, Santa Barbara. He obtained Ph.D. degree in electrical engineering and computer sciences from the University of California. He was named Fellow of the Institute of Electrical and Electronics Engineers in 2012 "for contributions to modeling and design of nanoscale integrated circuit interconnects." One of Banerjee's notable doctoral student is Deblina Sarkar, who later joined the faculty of Massachusetts Institute of Technology. The journal Nature Nanotechnology recognised their paper on tunnel field-effect transistor -based biosensor published in Applied Physics Letters in as one of the highlight papers in 2012.
Kaustav Banerjee's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- Electrical contacts to two-dimensional semiconductors. (2015) (1096)
- 3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration (2001) (1009)
- Role of metal contacts in designing high-performance monolayer n-type WSe2 field effect transistors. (2013) (776)
- MoS₂ field-effect transistor for next-generation label-free biosensors. (2014) (731)
- A subthermionic tunnel field-effect transistor with an atomically thin channel (2015) (702)
- Interconnect limits on gigascale integration (GSI) in the 21st century (2001) (516)
- Computational Study of Metal Contacts to Monolayer Transition-Metal Dichalcogenide Semiconductors (2014) (427)
- Circuit Modeling and Performance Analysis of Multi-Walled Carbon Nanotube Interconnects (2008) (363)
- A power-optimal repeater insertion methodology for global interconnects in nanometer designs (2002) (343)
- Performance analysis of carbon nanotube interconnects for VLSI applications (2005) (320)
- Modeling, Analysis, and Design of Graphene Nano-Ribbon Interconnects (2009) (319)
- High-performance MoS2 transistors with low-resistance molybdenum contacts (2014) (316)
- Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status, and Prospects (2009) (306)
- Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits (2009) (293)
- Synthesis of high-quality monolayer and bilayer graphene on copper using chemical vapor deposition (2011) (293)
- Functionalization of transition metal dichalcogenides with metallic nanoparticles: implications for doping and gas-sensing. (2015) (291)
- Two-dimensional van der Waals materials (2016) (267)
- Compact AC Modeling and Performance Analysis of Through-Silicon Vias in 3-D ICs (2010) (247)
- A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy (2006) (217)
- Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects (2005) (205)
- On the Applicability of Single-Walled Carbon Nanotubes as VLSI Interconnects (2009) (203)
- Analysis of on-chip inductance effects for distributed RLC interconnects (2002) (188)
- Global (interconnect) warming (2001) (185)
- 2D Semiconductor FETs—Projections and Design for Sub-10 nm VLSI (2015) (183)
- Scaling analysis of multilevel interconnect temperatures for high-performance ICs (2005) (175)
- Vertical Si-Nanowire $n$-Type Tunneling FETs With Low Subthreshold Swing ($\leq \hbox{50}\ \hbox{mV/decade}$ ) at Room Temperature (2011) (172)
- On thermal effects in deep sub-micron VLSI interconnects (1999) (171)
- Proposal for tunnel-field-effect-transistor as ultra-sensitive and label-free biosensors (2012) (170)
- Surface functionalization of two-dimensional metal chalcogenides by Lewis acid-base chemistry. (2016) (168)
- CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With $\leq 50$-mV/decade Subthreshold Swing (2011) (165)
- High-Frequency Analysis of Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design (2009) (157)
- Analytical modeling of single electron transistor for hybrid CMOS-SET analog IC design (2004) (149)
- Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part I: Modeling, Analysis, and Experimental Validation (2010) (143)
- Are carbon nanotubes the future of VLSI interconnections? (2006) (143)
- Impact of Contact on the Operation and Performance of Back-Gated Monolayer MoS2 Field-Effect-Transistors. (2015) (127)
- Controllable and Rapid Synthesis of High-Quality and Large-Area Bernal Stacked Bilayer Graphene Using Chemical Vapor Deposition (2014) (123)
- A global interconnect optimization scheme for nanometer scale VLSI with implications for latency, bandwidth, and power dissipation (2004) (118)
- Multiple Si layer ICs: motivation, performance analysis, and design implications (2000) (117)
- A Compact Current–Voltage Model for 2D Semiconductor Based Field-Effect Transistors Considering Interface Traps, Mobility Degradation, and Inefficient Doping Effect (2014) (116)
- Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status and Prospects (2009) (114)
- Characterization of self-heating in advanced VLSI interconnect lines based on thermal finite element simulation (1998) (108)
- Modeling and analysis of grain-orientation effects in emerging metal-gate devices and implications for SRAM reliability (2008) (107)
- High-performance few-layer-MoS2 field-effect-transistor with record low contact-resistance (2013) (100)
- Compact modeling and SPICE-based simulation for electrothermal analysis of multilevel ULSI interconnects (2001) (96)
- 2D crystal semiconductors: Intimate contacts. (2014) (92)
- Analytical thermal model for multilevel VLSI interconnects incorporating via effect (2002) (89)
- Carbon nanotube interconnects: implications for performance, power dissipation and thermal management (2005) (87)
- Intercalation Doped Multilayer-Graphene-Nanoribbons for Next-Generation Interconnects. (2017) (86)
- Cool Chips: Opportunities and Implications for Power and Thermal Management (2008) (85)
- A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-In Dynamic or Gates (2010) (84)
- Carbon Nanomaterials: The Ideal Interconnect Technology for Next-Generation ICs (2010) (83)
- Modeling and design of a low-voltage SOI suspended-gate MOSFET (SG-MOSFET) with a metal-over-gate architecture (2002) (81)
- Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part II: Implications for Process, Device, and Circuit Design (2010) (79)
- Analysis and optimization of thermal issues in high-performance VLSI (2001) (77)
- High-current failure model for VLSI interconnects under short-pulse stress conditions (1997) (76)
- Is negative capacitance FET a steep-slope logic switch? (2020) (74)
- The effect of interconnect scaling and low-k dielectric on the thermal characteristics of the IC metal (1996) (73)
- Low-frequency noise in bilayer MoS(2) transistor. (2014) (70)
- Statistical modeling of metal-gate Work-Function Variability in emerging device technologies and implications for circuit design (2008) (69)
- A Comparative Scaling Analysis of Metallic and Carbon Nanotube Interconnections for Nanometer Scale VLSI Technologies (2004) (69)
- Accurate analysis of on-chip inductance effects and implications for optimal repeater insertion and technology scaling (2001) (69)
- Analysis of IR-drop scaling with implications for deep submicron P/G network designs (2003) (68)
- High-Frequency Behavior of Graphene-Based Interconnects—Part I: Impedance Modeling (2011) (66)
- Interconnect challenges for nanoscale electronic circuits (2004) (65)
- Few electron devices: towards hybrid CMOS-SET integrated circuits (2002) (65)
- On-chip intercalated-graphene inductors for next-generation radio frequency electronics (2018) (63)
- A self-consistent junction temperature estimation methodology for nanometer scale ICs with implications for performance and thermal management (2003) (63)
- Localized heating effects and scaling of sub-0.18 micron CMOS devices (2001) (61)
- Analysis of non-uniform temperature-dependent interconnect performance in high performance ICs (2001) (61)
- Hybrid NEMS-CMOS integrated circuits: A novel strategy for energy-efficient designs (2009) (61)
- Fundamental limitations of conventional-FET biosensors: Quantum-mechanical-tunneling to the rescue (2012) (60)
- Graphene and beyond-graphene 2D crystals for next-generation green electronics (2014) (60)
- Introspective 3D chips (2006) (59)
- Proposal for all-graphene monolithic logic circuits (2013) (59)
- Correction to MoS2 Field-Effect Transistor for Next-Generation Label-Free Biosensors (2014) (58)
- A quasi-analytical SET model for few electron circuit simulation (2002) (58)
- A computational study of metal-contacts to beyond-graphene 2D semiconductor materials (2012) (58)
- Subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations (2004) (57)
- Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications (2007) (56)
- Metal-to-Multilayer-Graphene Contact—Part I: Contact Resistance Modeling (2012) (56)
- Current Status and Future Perspectives of Carbon Nanotube Interconnects (2008) (56)
- Analysis and design of distributed ESD protection circuits for high-speed mixed-signal and RF ICs (2002) (55)
- Compact AC modeling and analysis of Cu, W, and CNT based through-silicon vias (TSVs) in 3-D ICs (2009) (53)
- Graphene nano-ribbon (GNR) interconnects: A genuine contender or a delusive dream? (2008) (53)
- Analysis of nonuniform ESD current distribution in deep submicron NMOS transistors (2002) (52)
- High-Frequency Behavior of Graphene-Based Interconnects—Part II: Impedance Analysis and Implications for Inductor Design (2011) (51)
- Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability (2013) (49)
- Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era (2004) (49)
- Tunnel-field-effect-transistor based gas-sensor: Introducing gas detection with a quantum-mechanical transducer (2013) (48)
- Effects of non-uniform substrate temperature on the clock signal integrity in high performance designs (2001) (47)
- Subthreshold-swing physics of tunnel field-effect transistors (2014) (45)
- Defect and strain engineering of monolayer WSe2 enables site-controlled single-photon emission up to 150 K (2021) (45)
- A Statistical Framework for Estimation of Full-Chip Leakage-Power Distribution Under Parameter Variations (2007) (45)
- Modeling and Analysis of Self-Heating in FinFET Devices for Improved Circuit and EOS/ESD Performance (2007) (43)
- Exponential Data Fitting and Its Applications (2018) (43)
- Electron-hole duality during band-to-band tunneling process in graphene-nanoribbon tunnel-field-effect-transistors (2010) (40)
- 2-D Layered Materials for Next-Generation Electronics: Opportunities and Challenges (2018) (40)
- Design and analysis of compact ultra Energy-Efficient logic gates using laterally-actuated double-electrode NEMS (2010) (39)
- Modelling and analysis of power dissipation in single electron logic (2002) (39)
- High-Performance Field-Effect-Transistors On Monolayer-WSe2 (2013) (39)
- Compact Modeling and Analysis of Through-Si-Via-Induced Electrical Noise Coupling in Three-Dimensional ICs (2011) (37)
- RF LDMOS characterization and its compact modeling (2001) (35)
- Coupled analysis of electromigration reliability and performance in ULSI signal nets (2001) (35)
- A CAD framework for co-design and analysis of CMOS-SET hybrid integrated circuits (2003) (34)
- Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI (2005) (34)
- Design Optimization of FinFET Domino Logic Considering the Width Quantization Property (2010) (34)
- Can 2D-Nanocrystals Extend the Lifetime of Floating-Gate Transistor Based Nonvolatile Memory? (2014) (33)
- Boosting Hydrogen Evolution Performance of MoS2 by Band Structure Engineering (2017) (33)
- Accurate Intrinsic Gate Capacitance Model for Carbon Nanotube-Array Based FETs Considering Screening Effect (2008) (33)
- Impact of on-chip inductance on power distribution network design for nanometer scale integrated circuits (2005) (32)
- Analysis of substrate thermal gradient effects on optimal buffer insertion (2001) (32)
- Carbon Nanotube Vias: Does Ballistic Electron–Phonon Transport Imply Improved Performance and Reliability? (2011) (32)
- Graphene nanoribbon based negative resistance device for ultra-low voltage digital logic applications (2013) (31)
- Aging-resilient design of pipelined architectures using novel detection and correction circuits (2010) (31)
- A Novel Enhanced Electric-Field Impact-Ionization MOS Transistor (2010) (30)
- Analysis of on-chip inductance effects using a novel performance optimization methodology for distributed RLC interconnects (2001) (30)
- SETMOS: a novel true hybrid SET-CMOS high current Coulomb blockade oscillation cell for future nano-scale analog ICs (2003) (29)
- Thermal characteristics of submicron vias studied by scanning Joule expansion microscopy (2000) (29)
- Scaling and variability analysis of CNT-based NEMS devices and circuits with implications for process design (2008) (29)
- Fast 3-D thermal analysis of complex interconnect structures using electrical modeling and simulation methodologies (2009) (28)
- A Fully Analytical Model for the Series Impedance of Through-Silicon Vias With Consideration of Substrate Effects and Coupling With Horizontal Interconnects (2011) (28)
- Ultimate Monolithic-3D Integration With 2D Materials: Rationale, Prospects, and Challenges (2019) (27)
- Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems (2006) (27)
- Irradiation of Nanostrained Monolayer WSe2 for Site-Controlled Single-Photon Emission up to 150K (2020) (26)
- Metal-to-Multilayer-Graphene Contact—Part II: Analysis of Contact Resistance (2012) (26)
- Vertically Stacked and Independently Controlled Twin-Gate MOSFETs on a Single Si Nanowire (2011) (25)
- High-frequency effects in carbon nanotube interconnects and implications for on-chip inductor design (2008) (25)
- Interconnect Modeling and Analysis in the Nanometer Era: Cu and Beyond (2005) (24)
- A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMS (2010) (23)
- 2D electronics: Graphene and beyond (2013) (23)
- On the Electrostatic Discharge Robustness of Graphene (2014) (23)
- Low-Resistivity Long-Length Horizontal Carbon Nanotube Bundles for Interconnect Applications—Part II: Characterization (2013) (23)
- Low-Resistivity Long-Length Horizontal Carbon Nanotube Bundles for Interconnect Applications—Part I: Process Development (2013) (22)
- Modeling techniques and verification methodologies for substrate coupling effects in mixed-signal system-on-chip designs (2004) (22)
- Performance evaluation and design considerations of 2D semiconductor based FETs for sub-10 nm VLSI (2014) (21)
- Impact of scaling on the performance and reliability degradation of metal-contacts in NEMS devices (2011) (21)
- Designing band-to-band tunneling field-effect transistors with 2D semiconductors for next-generation low-power VLSI (2015) (21)
- Characterization of self-heating and current-carrying capacity of intercalation doped graphene-nanoribbon interconnects (2017) (21)
- Variability analysis of FinFET-based devices and circuits considering electrical confinement and width quantization (2009) (20)
- A fast analytical technique for estimating the bounds of on-chip clock wire inductance (2001) (20)
- Impact-ionization field-effect-transistor based biosensors for ultra-sensitive detection of biomolecules (2013) (20)
- Designing artificial 2D crystals with site and size controlled quantum dots (2017) (19)
- Performance analysis and technology of 3-D ICs (2000) (19)
- Carbon Nanotube Vias: A Reality Check (2007) (19)
- Analysis of gate-bias-induced heating effects in deep-submicron ESD protection designs (2002) (19)
- An Ultra-Short Channel Monolayer MoS2 FET Defined By the Curvature of a Thin Nanowire (2016) (19)
- Impact of gate-to-contact spacing on ESD performance of salicided deep submicron NMOS transistors (2002) (19)
- 3-D ICs: Motivation, performance analysis, and technology (2000) (19)
- A thermally-aware methodology for design-specific optimization of supply and threshold voltages in nanometer scale ICs (2005) (18)
- Supply and power optimization in leakage-dominant technologies (2005) (18)
- Power dissipation issues in interconnect performance optimization for sub-180 nm designs (2002) (17)
- A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates (2006) (16)
- CMOS-Compatible Doped-Multilayer-Graphene Interconnects for Next-Generation VLSI (2018) (16)
- Grain-Orientation Induced Quantum Confinement Variation in FinFETs and Multi-Gate Ultra-Thin Body CMOS Devices and Implications for Digital Design (2011) (16)
- Characterization of FeCl 3 Intercalation Doped CVD Few-Layer Graphene (2016) (16)
- A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations (2005) (15)
- Power supply optimization in sub-130 nm leakage dominant technologies (2004) (15)
- Effect of band-tails on the subthreshold performance of 2D tunnel-FETs (2016) (14)
- Amarogentin regulates self renewal pathways to restrict liver carcinogenesis in experimental mouse model (2016) (14)
- Temperature and current effects on small-geometry-contact resistance (1997) (14)
- Investigation of self-heating phenomenon in small geometry vias using scanning Joule expansion microscopy (1999) (14)
- Inductance aware interconnect scaling (2002) (14)
- Gate bias induced heating effect and implications for the design of deep submicron ESD protection (2001) (14)
- Graphene based heterostructure tunnel-FETs for low-voltage/high-performance ICs (2010) (14)
- All-carbon interconnect scheme integrating graphene-wires and carbon-nanotube-vias (2017) (14)
- Graphene inductors for high-frequency applications - design, fabrication, characterization, and study of skin effect (2014) (13)
- Impact of off-state leakage current on electromigration design rules for nanometer scale CMOS technologies (2004) (13)
- Undoped and catalyst-free germanium nanowires for high-performance p-type enhancement-mode field-effect transistors (2016) (13)
- A Thermal Simulation Process Based on Electrical Modeling for Complex Interconnect, Packaging, and 3DI Structures (2010) (13)
- Potent anti-proliferative activities of organochalcogenocyanates towards breast cancer. (2018) (12)
- Analysis and optimization of substrate noise coupling in single-chip RF transceiver design (2002) (12)
- Analysis and design of ESD protection circuits for high-frequency/RF applications (2001) (12)
- Compact modeling and analysis of coupling noise induced by through-Si-vias in 3-D ICs (2010) (12)
- The dependence of W-plug via EM performance on via size (1996) (12)
- High current effects in silicide films for sub-0.25 /spl mu/m VLSI technologies (1998) (12)
- Understanding the Device Physics in Polymer‐Based Ionic–Organic Ratchets (2017) (12)
- An Electrothermally-Aware Full-Chip Substrate Temperature Gradient Evaluation Methodology for Leakage Dominant Technologies with Implications for Power Estimation and Hot-Spot Management (2006) (11)
- Prospects of graphene electrodes in photovoltaics (2013) (11)
- A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part I: Electrothermal Couplings and Full-Chip Package Thermal Model (2007) (11)
- Top illuminated inverted organic ultraviolet photosensors with single layer graphene electrodes (2012) (11)
- Emerging Nanoelectronics: Life with and after CMOS (2004) (11)
- Analysis and optimization of distributed ESD protection circuits for high-speed mixed-signal and RF applications (2001) (11)
- Trends for ULSI Interconnections and Their Implications for Thermal, Reliability and Performance Issues (Invited Paper) (2001) (10)
- Characterization of FeCl3 Intercalation Doped CVD Few-Layer Graphene (2016) (10)
- A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies (2008) (10)
- Monolithic-3D Integration with 2D Materials: Toward Ultimate Vertically-Scaled 3D-ICs (2018) (10)
- Thermal Scaling Analysis of Multilevel Cu/Low-k Interconnect Structures in Deep Nanometer Scale Technologies (2005) (10)
- Engineered 2D nanomaterials–protein interfaces for efficient sensors (2015) (10)
- High-speed low-power FinFET based domino logic (2009) (10)
- An Insight into the High Current ESD Behavior of Drain Extended NMOS (DENMOS) Devices in Nanometer Scale CMOS Technologies (2007) (9)
- Trisulfides over disulfides: highly selective synthetic strategies, anti-proliferative activities and sustained H2S release profiles. (2019) (9)
- Thermal analysis of the fusion limits of metal interconnect under short duration current pulses (1996) (9)
- Thermal Challenges of 3D ICs (2008) (9)
- Non-uniform chip-temperature dependent signal integrity (2001) (9)
- Scaling analysis of graphene nanoribbon tunnel-FETs (2009) (9)
- A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part II: Implementation and Implications for Power Estimation and Thermal Management (2007) (9)
- Analysis and implications of parasitic and screening effects on the high-frequency/RF performance of tunneling-carbon nanotube FETs (2008) (9)
- A Microscopic Understanding of Nanometer Scale DENMOS Failure Mechanism under ESD Conditions (2007) (8)
- Can Carbon Nanotubes Extend the Lifetime of On-Chip Electrical Interconnections? (2006) (8)
- Area-Selective-CVD Technology Enabled Top-Gated and Scalable 2D-Heterojunction Transistors with Dynamically Tunable Schottky Barrier (2019) (8)
- Mechanisms leading to erratic snapback behavior in bipolar junction transistors with base emitter shorted (2005) (8)
- Non-uniform conduction induced reverse channel length dependence of ESD reliability for silicided NMOS transistors (2002) (8)
- Room temperature 2D memristive transistor with optical short-term plasticity (2017) (8)
- ESD characterization of atomically-thin graphene (2012) (8)
- Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate (2009) (8)
- A built-in aging detection and compensation technique for improving reliability of nanoscale CMOS designs (2010) (8)
- Prospects of carbon nanomaterials for next-generation green electronics (2010) (7)
- Analysis and implications of ic cooling for deep nanometer scale cmos technologies (2005) (7)
- Metallic-nanoparticle assisted enhanced band-to-band tunneling current (2011) (7)
- A Physical Model for Work-Function Variation in Ultra-Short Channel Metal-Gate MOSFETs (2011) (7)
- LEAKAGE AND VARIATION AWARE THERMAL MANAGEMENT OF NANOMETER SCALE ICS (2004) (7)
- New physical insight and modeling of second breakdown (It/sub 2/) phenomenon in advanced esd protection devices (2005) (7)
- 0.5T0.5R—An Ultracompact RRAM Cell Uniquely Enabled by van der Waals Heterostructures (2021) (7)
- Via design and scaling strategy for nanometer scale interconnect technologies (2002) (7)
- Nano, quantum, and molecular computing: are we ready for the validation and test challenges? (2003) (7)
- Fast extraction of high-frequency parallel admittance of Through-Silicon-Vias and their capacitive coupling-noise to active regions (2012) (7)
- Physical Modeling of the Capacitance and Capacitive Coupling Noise of Through-Oxide Vias in FDSOI-Based Ultra-High Density 3-D ICs (2013) (7)
- 3D device modeling of damage due to filamentation under an ESD event in nanometer scale drain extended NMOS (DE-NMOS) (2008) (6)
- A mode-balanced reconfigurable logic gate built in a van der Waals strata (2021) (6)
- Quantum Engineered Devices Based on Two-Dimensional Materials for Next-Generation Information Processing and Storage. (2022) (6)
- An Interconnect Scaling Scheme with Constant On-Chip Inductive Effects (2003) (5)
- Modeling and Extraction of Nanometer Scale Interconnects: Challenges and Opportunities (Invited) (2006) (5)
- Teaching microelectronics in the silicon ICs showstopper zone: a course on ultimate devices and circuits: towards quantum electronics (2002) (5)
- One-Dimensional Edge Contacts to Two-Dimensional Transition-Metal Dichalcogenides: Uncovering the Role of Schottky-Barrier Anisotropy in Charge Transport across MoS2 /Metal Interfaces (2021) (5)
- Effect of Grain Orientation on NBTI Variation and Recovery in Emerging Metal-Gate Devices (2010) (5)
- Computational study of gate-induced drain leakage in 2D-semiconductor field-effect transistors (2017) (5)
- 3D Integration for Introspection (2007) (5)
- Heterogeneous ICs : A Technology for the Next Decade and Beyond (2001) (4)
- High current effects in silicide films for sub-0.25 μm VLSI technologies (1998) (4)
- Impact of strain engineering and channel orientation on the ESD performance of nanometer scale CMOS devices (2009) (4)
- 3-D integrable optoelectronic devices for telecommunications ICs (2002) (4)
- A comprehensive analytical capacitance model of a two dimensional nanodot array [cellular neural net application] (2004) (4)
- Two-dimensional materials enabled next-generation low-energy compute and connectivity (2021) (4)
- Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs With Multiple Substrates (2012) (4)
- (Invited) 2D/3D Tunnel-FET: Toward Green Transistors and Sensors (2017) (4)
- SET-based quantiser circuit for digital communications (2002) (4)
- Impact of Transport Anisotropy on the Performance of van der Waals Materials-Based Electron Devices (2020) (4)
- Work-function variation induced fluctuation in bias-temperature-instability characteristics of emerging metal-gate devices and implications for digital design (2010) (4)
- High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate (2008) (4)
- UCSB Graphene Nanoribbon Interconnect Compact Model (2017) (4)
- Benzimidazole- and Imidazole-Fused Selenazolium and Selenazinium Selenocyanates: Ionic Organoselenium Compounds with Efficient Peroxide Scavenging Activities. (2021) (3)
- Interfacial Thermal Conductivity of 2D Layered Materials: An Atomistic Approach (2018) (3)
- A SET quantizer circuit aiming at digital communication system (2002) (3)
- Prospects of carbon nanomaterials in VLSI for interconnections and energy storage (2009) (3)
- Quasi-analytical Modelling of Drain Current and Conductance of Single Electron Transistors with MIB (2002) (3)
- Computational Study of Interfaces between 2 D MoS 2 and Surroundings (2015) (3)
- Performance analysis of multi-walled carbon nanotube based interconnects (2007) (3)
- AC conductance modeling and analysis of graphene nanoribbon interconnects (2010) (3)
- Demonstration of CMOS-Compatible Multi-Level Graphene Interconnects With Metal Vias (2021) (3)
- Enhanced thermal stability of novel helical-finned jacketed stirred tank heater (2020) (3)
- Prospects of ultra-thin nanowire gated 2D-FETs for next-generation CMOS technology (2016) (3)
- Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate (2010) (3)
- NanoCarbon for next-generation green electronics: Status and prospects (2013) (2)
- The Amelioration of Detrimental Biochemical Anomalies by Supplementing B, C, and E Vitamins in Subjects with Type 2 Diabetes Mellitus May Reduce the Rate of Development of Diabetic Retinopathy (2022) (2)
- 3-D ICS DSM Interconnect Performance Modeling and Analysis (2003) (2)
- 2-Dimensional tunnel devices and circuits on graphene: Opportunities and challenges (2013) (2)
- Junction-Less Monolayer MoS2 FETs (2015) (2)
- How to derive the highest mobility from 2D FETs — A first-principle study (2017) (2)
- Corrections to "Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate" [Jul 09 1047-1060] (2010) (2)
- A Compact Current–Voltage Model for 2-D-Semiconductor-Based Lateral Homo-/Hetero-Junction Tunnel-FETs (2020) (2)
- Compact capacitance and capacitive coupling-noise modeling of Through-Oxide Vias in FDSOI based ultra-high density 3-D ICs (2011) (2)
- Nano-enhanced Architectures : Using Carbon Nanotube Interconnects in Cache Design (2)
- On the Electrostatics of Bernal-Stacked Few-Layer Graphene on Surface-Passivated Semiconductors (2014) (2)
- A quantitative inquisition into ESD sensitivity to strain in nanoscale CMOS protection devices (2010) (2)
- CMOS vs Nano: comrades or rivals? (2009) (1)
- Characterization and Closed-Form Modeling of Edge/Top/Hybrid Metal-2D Semiconductor Contacts (2022) (1)
- Correction to "Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability" (2020) (1)
- SETMOS: a Novel True Hybrid SET-CMOS Cell with High Current and Coulomb Blockade for Future Nano-scale Analog ICs (2003) (1)
- Some Clarifications on “Compact Modeling and Analysis of Through-Si-Via Induced Electrical Noise Coupling in Three-Dimensional ICs” (2012) (1)
- Is negative capacitance FET a steep-slope logic switch? (2020) (1)
- Engineered 2D nanomaterials–protein interfaces for efficient sensors – ERRATUM (2015) (1)
- Can Kinetic Inductance in Low-Dimensional Materials Enable a New Generation of RF-Electronics? (2018) (1)
- Graphene based transistors: physics, status and future perspectives (2009) (1)
- 0.5T0.5R - Introducing an Ultra-Compact Memory Cell Enabled by Shared Graphene Edge-Contact and h-BN Insulator (2020) (1)
- Computational Study of Spin Injection in 2D Materials (2019) (1)
- Benzimidazole-based Ionic and Non-ionic Organoselenium Compounds: Innovative Synthetic Strategies, Structural Characterizations and Preliminary Anti-Proliferative Activities (2022) (1)
- Novel logic devices based on 2D crystal semiconductors: Opportunities and challenges (2013) (1)
- On-chip intercalated-graphene inductors for next-generation radio frequency electronics (2018) (1)
- Author Correction: Is negative capacitance FET a steep-slope logic switch? (2020) (1)
- Graphene based nanomaterials for VLSI interconnect and energy-storage applications (2009) (1)
- 2D Materials for Smart Life (2018) (1)
- Reliability and Performance of CMOS-Compatible Multi-Level Graphene Interconnects Incorporating Vias (2020) (1)
- A fast semi-numerical technique for the solution of the poisson-boltzmann equation in a cylindrical nanowire (2007) (1)
- Modeling and analysis of intrinsic gate capacitance for carbon nanotube array based devices considering variation in screening effect and diameter (2007) (1)
- The scaling of the microLED and the advantage of 2D materials (2021) (1)
- Towards GREEN Electronics : Design , Modeling and Fabrication of Steep Subthreshold Slope Switches (2011) (0)
- Designing artificial 2D crystals with site and size controlled quantum dots (2017) (0)
- A Comparative Study of Interconnect Circuit Techniques for Energy Efficient On-Chip Interconnects (2016) (0)
- Tutorial 1: Emerging Technologies for VLSI Design (2006) (0)
- Electrical characterization of back-gated and top-gated germanium-core/silicon-shell nanowire field-effect transistors (2016) (0)
- Reliable , High-Performance I / O Buffer Design for Multiple Power Supply Systems (1997) (0)
- Some results pertaining electromagnetic characterization and model building for passive systems including TSVs, for 3-D IC applications (2011) (0)
- Advanced ElectroThermal Modeling and Simulation Techniques for Deep SubMicron Devices (2000) (0)
- Defect and Strain Engineering of Monolayer WSe2 for Site-Controlled Single-Photon Emission up to 150K (2021) (0)
- Non-Uniform Interconnect Temperature-Driven Buffer Insertion (2001) (0)
- Invited) 2D Van Der Waals Crystals and Heterostructures for Smart Life (2016) (0)
- Electrical Properties of Erbium Doped Aluminum Gallium Arsenide (1993) (0)
- An efficient 3D Green's function approach for fast impedance extraction of interconnects and spiral inductors in CMOS RF/Millimeter-wavelength circuits (2010) (0)
- Can CarbonNanotubes ExtendtheLifetime of On-Chip Electrical Interconnections ? (Invited) (2006) (0)
- Getting to the Bottom of Negative Capacitance FETs (2018) (0)
- [Keynote Talk] 2D Materials and Devices for Smart Life (2019) (0)
- -D ICs: Performance Analysis, and Technology (2000) (0)
- Session details: Emerging technologies: blue-sky research or CMOS replacement? (2009) (0)
- UCSB 2D Transition-Metal-Dichalcogenide (TMD) FET model (2015) (0)
- Power and Thermal Challenges for 65 nm and Below (2006) (0)
- ce Few-Layer-MoS2 Field-Effect-Trans Record Low Contact-Resistance (2013) (0)
- SESSION 38: CMOS and interconnect reliability ESD, soft errors and backend reliability issues for nanoscale CMOS technologies (2004) (0)
- NEMS-Based Ultra Energy-Efficient Digital ICs: Materials, Device Architectures, Logic Implementation, and Manufacturability (2017) (0)
- How to derive the highest mobility from 2D FETs — A first-principle study (2017) (0)
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