Keivan Navi

Q: What Schools Are Affiliated With Keivan Navi

Keivan Navi is affiliated with the following schools: University of California, Berkeley, University of California, Irvine, Islamic Azad University, Shahid Beheshti University, Stanford University

Keivan Navi's AcademicInfluence.com Rankings

Keivan Navi

Computer Science

#10159

World Rank

#10654

Historical Rank

Computational Linguistics

#2563

World Rank

#2588

Historical Rank

Machine Learning

#4639

World Rank

#4691

Historical Rank

Artificial Intelligence

#5001

World Rank

#5066

Historical Rank

computer-science Degrees

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Computer Science

Keivan Navi's Degrees

Masters Computer Science Stanford University
Bachelors Computer Science University of California, Berkeley

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Keivan Navi's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

A new quantum-dot cellular automata full-adder (2016) (229)
Design of energy-efficient and robust ternary circuits for nanotechnology (2011) (213)
Five-Input Majority Gate, a New Device for Quantum-Dot Cellular Automata (2010) (201)
Design of a Novel Reversible Multiplier Circuit Using HNG Gate in Nanotechnology (2008) (195)
A Novel Reversible BCD Adder For Nanotechnology Based Systems (2008) (190)
Novel Robust Single Layer Wire Crossing Approach for Exclusive OR Sum of Products Logic Design with Quantum-Dot Cellular Automata (2014) (177)
Two new low-power Full Adders based on majority-not gates (2009) (163)
Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata (2015) (149)
A Novel Design for Quantum-dot Cellular Automata Cells and Full Adders (2007) (148)
Towards single layer quantum-dot cellular automata adders based on explicit interaction of cells (2016) (147)
New robust QCA D flip flop and memory structures (2012) (142)
A novel low-power full-adder cell for low voltage (2009) (130)
Efficient Reverse Converter Designs for the New 4-Moduli Sets $\{2^{n} -1, 2^{n}, 2^{n} +1, 2^{2n + 1}-1\}$ and $\{2^{n} -1, 2^{n} +1, 2^{2n}, 2^{2n} +1\}$ Based on New CRTs (2010) (123)
Optimized Reversible Multiplier Circuit (2009) (122)
A Novel Fault Tolerant Reversible Gate For Nanotechnology Based Systems (2008) (120)
A Novel Reversible Full Adder Circuit for Nanotechnology Based Systems (2007) (114)
An Efficient Quantum-Dot Cellular Automata Full Adder Based on a New Convertible 7-Input Majority-Not Gate (2020) (113)
A novel design of 8-bit adder/subtractor by quantum-dot cellular automata (2014) (109)
Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell (2008) (107)
Novel Reversible Multiplier Circuit in Nanotechnology (2008) (106)
How to Teach Residue Number System to Computer Scientists and Engineers (2011) (102)
A symmetric quantum-dot cellular automata design for 5-input majority gate (2014) (99)
Design of a Novel Fault Tolerant Reversible Full Adder for Nanotechnology Based Systems (2008) (95)
Efficient RNS Implementation of Elliptic Curve Point Multiplication Over ${\rm GF}(p)$ (2013) (93)
A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits (2013) (93)
Efficient QCA Exclusive-or and Multiplexer Circuits Based on a Nanoelectronic-Compatible Designing Approach (2014) (89)
Efficient reverse converter designs for the new 4-moduli sets {2n - 1, 2n, 2n + 1, 22n+1 - 1} and {2n - 1, 2n + 1, 22n, 22n + 1} based on new CRTs (2010) (88)
A novel low-power full-adder cell with new technique in designing logical gates based on static CMOS inverter (2009) (85)
Towards ultra-efficient QCA reversible circuits (2017) (82)
Design and Evaluation of CNFET-Based Quaternary Circuits (2012) (79)
Restoring and non-restoring array divider designs in Quantum-dot Cellular Automata (2015) (79)
Efficient CNTFET-based Ternary Full Adder Cells for Nanoelectronics (2011) (76)
Designing quantum-dot cellular automata counters with energy consumption analysis (2015) (75)
Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style (2014) (75)
A new high dynamic range moduli set with efficient reverse converter (2008) (75)
High Speed Capacitor-Inverter Based Carbon Nanotube Full Adder (2010) (70)
A new design procedure for all-optical photonic crystal logic gates and functions based on threshold logic (2016) (66)
Two novel ultra high speed carbon nanotube Full-Adder cells (2009) (65)
A Novel Robust QCA Full-adder☆ (2015) (61)
Design and analysis of a high-performance CNFET-based Full Adder (2012) (61)
A New Design for 7:2 Compressors (2007) (59)
Novel design of a fast reversible Wallace sign multiplier circuit in nanotechnology (2011) (58)
A Novel Architecture for Quantum-Dot Cellular Automata Multiplexer (2011) (57)
Novel direct designs for 3-input XOR function for low-power and high-speed applications (2010) (57)
Novel Efficient Adder Circuits for Quantum-Dot Cellular Automata (2011) (56)
HQCA-WSN: High-quality clustering algorithm and optimal cluster head selection using fuzzy logic in wireless sensor networks (2020) (56)
New Quantum Dot Cellular Automata Cell Arrangements (2013) (55)
Two New Low-Power and High-Performance Full Adders (2009) (52)
Arithmetic Circuits of Redundant SUT-RNS (2009) (52)
Design and implementation of Multistage Interconnection Networks using Quantum-dot Cellular Automata (2011) (48)
High-speed full adder based on minority function and bridge style for nanoscale (2011) (47)
An energy and cost efficient majority-based RAM cell in quantum-dot cellular automata (2017) (47)
A low-voltage and energy-efficient full adder cell based on carbon nanotube technology (2010) (46)
MINIMIZATION AND OPTIMIZATION OF REVERSIBLE BCD-FULL ADDER/SUBTRACTOR USING GENETIC ALGORITHM AND DON'T CARE CONCEPT (2009) (45)
An Energy-Efficient Full Adder Cell Using CNFET Technology (2012) (45)
Quantum-dot cellular automata circuits with reduced external fixed inputs (2017) (45)
Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach (2015) (44)
Universal ternary logic circuit design through carbon nanotube technology (2009) (42)
Quaternary full adder cells based on carbon nanotube FETs (2015) (41)
New efficient five-input majority gate for quantum-dot cellular automata (2012) (41)
Novel Design for Quantum Dots Cellular Automata to Obtain Fault-Tolerant Majority Gate (2012) (40)
New Method for Decreasing the Number of Quantum Dot Cells in QCA Circuits (2008) (39)
An energy and area efficient 4: 2 compressor based on FinFETs (2018) (39)
All-optical photonic crystal logic gates using nonlinear directional coupler (2017) (39)
A Novel CMOS Full Adder (2007) (38)
A New Low Power Dynamic Full Adder Cell Based on Majority Function (2008) (38)
Ultra-area-efficient reversible multiplier (2012) (37)
High-Performance Mixed-Mode Universal Min-Max Circuits for Nanotechnology (2012) (37)
High Speed NP-CMOS and Multi-Output Dynamic Full Adder Cells (2010) (36)
High-Efficient Circuits for Ternary Addition (2014) (35)
Coplanar wire crossing in quantum cellular automata using a ternary cell (2013) (35)
Design of Robust and High-Performance 1-Bit CMOS Full Adder for Nanometer Design (2008) (34)
Method for designing ternary adder cells based on CNFETs (2017) (34)
New Arithmetic Residue to Binary Converters (2007) (33)
An improved reverse converter for the moduli set {2n-1, 2n, 2n+1, 2n+1-1} (2008) (32)
A Novel Multiple Valued Logic OHRNS Modulo rn Adder Circuit (2007) (32)
An efficient architecture for designing reverse converters based on a general three-moduli set (2008) (32)
NOVEL REVERSIBLE FAULT TOLERANT ERROR CODING AND DETECTION CIRCUITS (2011) (32)
Efficient Quantum Dot Cellular Automata Memory Architectures Based on the New Wiring Approach (2014) (30)
High Performance CNFET-based Ternary Full Adders (2017) (30)
Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits (2010) (29)
Designing Reconfigurable Quantum-Dot Cellular Automata Logic Circuits (2013) (29)
Performance of CMOS current mode full adders (1994) (29)
Designing High Speed Sequential Circuits by Quantum-Dot Cellular Automata: Memory Cell and Counter Study (2015) (29)
Design and Verification of New n-Bit Quantum-Dot Synchronous Counters Using Majority Function-Based JK Flip-Flops (2015) (29)
New fully single layer QCA full-adder cell based on feedback model (2015) (28)
Dramatically Low-Transistor-Count High-Speed Ternary Adders (2013) (28)
Efficient Carbon Nanotube Galois Field Circuit Design (2009) (28)
A New Residue to Binary Converter Based on Mixed-Radix Conversion (2008) (27)
Ultra-Efficient Fuzzy Min/Max Circuits Based on Carbon Nanotube FETs (2018) (27)
Cost-efficient QCA reversible combinational circuits based on a new reversible gate (2015) (27)
New Design of RNS Subtractor for modulo 2n+ 1 (2006) (26)
Design and evaluation of energy-efficient carbon nanotube FET-based quaternary minimum and maximum circuits (2017) (25)
A novel low power Exclusive-OR via cell level-based design function in quantum cellular automata (2017) (25)
A new five-moduli set for efficient hardware implementation of the reverse converter (2009) (25)
A Reverse Converter for the Enhanced Moduli Set {2n-1, 2n+1, 22n, 22n+1-1} Using CRT and MRC (2010) (24)
Carbon Nanotube Field Effect Transistor Switching Logic for Designing Efficient Ternary Arithmetic Circuits (2017) (24)
A hardware-friendly arithmetic method and efficient implementations for designing digital fuzzy adders (2011) (24)
Novel CNFET ternary circuit techniques for high-performance and energy-efficient design (2019) (24)
Design and analysis of efficient QCA reversible adders (2018) (23)
A 3D universal structure based on molecular-QCA and CNT technologies (2016) (23)
CAST-WSN: The Presentation of New Clustering Algorithm Based on Steiner Tree and C-Means Algorithm Improvement in Wireless Sensor Networks (2017) (23)
A novel majority based imprecise 4: 2 compressor with respect to the current and future VLSI industry (2020) (23)
A Novel Seven Input Majority Gate in Quantum-dot Cellular Automata (2012) (23)
A New Two Phase Configuration for Switched Reluctance Motor with High Starting Torque (2007) (23)
An energy efficient full adder cell for low voltage (2009) (22)
Ultra-low-power carbon nanotube FET-based quaternary logic gates (2016) (22)
Optimal design of RAM cell using novel 2:1 multiplexer in QCA technology (2019) (22)
Differential Cascode Voltage Switch (DCVS) Strategies by CNTFET Technology for Standard Ternary Logic (2013) (22)
A New Moduli Set for Residue Number System: {rn 2,rn 1,rn} (2007) (21)
A New Robust and High-Performance Hybrid Full Adder Cell (2011) (21)
A New Cell Design Methodology for Balanced XOR-XNOR Circuits for Hybrid-CMOS Logic (2009) (21)
Efficient Class of Redundant Residue Number System (2007) (21)
A Novel Quaternary Full Adder Cell Based on Nanotechnology (2015) (21)
Ultra high speed Full Adders (2008) (20)
Optimum Quaternary Galois Field Circuit Design through Carbon Nano Tube Technology (2007) (20)
Implementation of all-optical reversible logic gate based on holographic laser induced grating using azo-dye doped polymers (2013) (20)
On the design of new low-power CMOS standard ternary logic gates (2010) (19)
A new systematic design approach for low-power analog integrated circuits (2012) (19)
CNFET-based approximate ternary adders for energy-efficient image processing applications (2016) (19)
Efficient MRC-Based Residue to Binary Converters for the New Moduli Sets {22n, 2n -1, 2n+1 -1} and {22n, 2n -1, 2n-1 -1} (2009) (19)
Novel efficient full adder and full subtractor designs in quantum cellular automata (2019) (18)
Analytical Review of Noise Margin in MVL: Clarification of a Deceptive Matter (2019) (18)
Implementation of reversible logic design in nanoelectronics on basis of majority gates (2012) (17)
Multi-output majority gate-based design optimization by using evolutionary algorithm (2013) (17)
Optimized Quantum Circuit Partitioning (2020) (17)
A New Low Power 32×32-bit Multiplier (2007) (17)
A New Moduli Set for Residue Number System in Ternary Valued Logic (2007) (17)
Algorithms and multi-valued circuits for the multioperand addition in the binary stored-carry number system (1993) (17)
An Ultra High-Speed (4; 2) Compressor with a New Design Approach for Nanotechnology Based on the Multi-Input Majority Function (2014) (16)
A General Reverse Converter Architecture with Low Complexity and High Performance (2011) (16)
Design, analysis, and implementation of partial product reduction phase by using wide m: 3 (4 ≤ m ≤ 10) compressors (2013) (16)
Efficient Single-Electron Transistor Inverter-Based Logic Circuits and Memory Elements (2013) (16)
Robust Coplanar Full Adder Based on Novel Inverter in Quantum Cellular Automata (2018) (16)
A novel ternary half adder and multiplier based on carbon nanotube field effect transistors (2017) (15)
An Ultra-High Speed and Low Complexity Quantum-Dot Cellular Automata Full Adder (2015) (15)
A combined three and five inputs majority gate-based high performance coplanar full adder in quantum-dot cellular automata (2019) (15)
CNFET-Based Design of Energy-Efficient Symmetric Three-Input XOR and Full Adder Circuits (2013) (15)
Design of Efficient and Testable n-Input Logic Gates in Quantum-Dot Cellular Automata (2013) (15)
Design and analysis of carbon nanotube FET based quaternary full adders (2016) (15)
Five New MVL Current Mode Differential Absolute Value Circuits Based on Carbon Nano-tube Field Effect Transistors (CNTFETs) (2010) (15)
CML current mode full adders for 2.5-V power supply (1994) (15)
Improved Modulo 2n +1 Adder Design (2008) (14)
A novel design of a ternary coded decimal adder/subtractor using reversible ternary gates (2018) (14)
A novel ternary quantum-dot cell for solving majority voter gate problem (2014) (14)
Optimized Adder Cells for Ternary Ripple-Carry Addition (2014) (14)
A new four-modulus RNS to binary converter (2010) (14)
Reversible Multiplexer Design in Quantum-Dot Cellular Automata (2014) (14)
An applicable high-efficient CNTFET-based full adder cell for practical environments (2012) (14)
A Novel High-Speed 54Ã54 bit Multiplier (2007) (14)
Design of quaternary 4-2 and 5-2 compressors for nanotechnology (2016) (13)
Design and evaluation of a 5-input majority gate-based content-addressable memory cell in quantum-dot cellular automata (2017) (13)
A Novel Design of a Multiplier Using Reversible Ternary Gates (2019) (13)
Design and Evaluation of a Reconfigurable Fault Tolerant Quantum-Dot Cellular Automata Gate (2013) (13)
A Novel High-Speed 54 × 54 bit Multiplier (2007) (13)
On the design of quaternary arithmetic logic unit based on CNTFETs (2019) (12)
A Novel Mixed Mode Current and Dynamic Voltage Full Adder (2008) (12)
A Novel Quantum-Dot Cellular Automata Reconfigurable Majority Gate with 5 and 7 Inputs Support (2015) (12)
Designing positive, negative and standard gates for ternary logics using quantum dot cellular automata (2020) (12)
Configurable all-optical photonic crystal XOR/AND and XNOR/NAND logic gates (2020) (12)
An Energy- and Area-Efficient Approximate Ternary Adder Based on CNTFET Switching Logic (2018) (12)
New CNTFET-Based Arithmetic Cells with Weighted Inputs for High Performance Energy Efficient Applications (2013) (12)
A critical appraisal of heterogeneity in Obsessive-Compulsive Disorder using symptom-based clustering analysis. (2017) (12)
A Novel Design Approach for Ternary Compressor Cells Based on CNTFETs (2016) (12)
Designing quantum-dot cellular automata circuits using a robust one layer crossover scheme (2014) (11)
Two novel inverter-based ternary full adder cells using CNFETs for energy-efficient applications (2020) (11)
A Systematic Approach to Design Boolean Functions using CNFETs and an Array of CNFET capacitors (2014) (11)
A New Approach to Overflow Detection in Moduli Set {2n-3, 2n-1, 2n+1, 2n+3} (2009) (11)
Low-power, high-speed 1-bit inexact Full Adder cell designs applicable to low-energy image processing (2017) (11)
High speed reverse converter for new five-moduli set {2n, 22n+1-1, 2n/2-1, 2n/2+1, 2n+1} (2010) (11)
Energy-Efficient Single-Layer QCA Logical Circuits Based on a Novel XOR Gate (2018) (11)
All optical fan out able half adder circuit based on nonlinear directional coupler (2017) (10)
High Speed Full Swing Current Mode BiCMOS Logical Operators (2007) (10)
A high-performance fully programmable membership function generator based on 10 nm gate-all-around CNTFETs (2020) (10)
A Novel Ternary-to-Binary Converter in Quantum-Dot Cellular Automata (2012) (10)
A Parallel Implementation of the Reverse Converter for the Moduli Set {2n, 2n–1, 2n–1–1} (2009) (10)
Reliability Study of Single Stage Multi-Input Majority Function for QCA (2013) (10)
A Novel Design Approach for Multi-input XOR Gate Using Multi-input Majority Function (2014) (10)
Cellular learning automata based evolutionary computing (CLA-EC) for intrinsic hardware evolution (2005) (10)
A CNFET-based hybrid multi-threshold 1-bit full adder design for energy efficient low power applications (2018) (10)
Synthesis and Optimization by Quantum Circuit Description Language (2014) (9)
Design of testable reversible latches by using a novel efficient implementation of Fredkin gate (2020) (9)
On the design of low power 1-bit full adder cell (2009) (9)
A low-power high-speed hybrid multi-threshold full adder design in CNFET technology (2018) (9)
A Novel DCVS Tree Reduction Algorithm (2006) (9)
A Novel Current Mode Full Adder Based on Majority Function (2008) (9)
Design and Power Analysis of New Coplanar One-Bit Full-Adder Cell in Quantum-Dot Cellular Automata (2018) (9)
New Current-Mode Integrated Ternary Min/Max Circuits without Constant Independent Current Sources (2015) (9)
An Efficient 5-Input Exclusive-OR Circuit Based on Carbon Nanotube FETs (2014) (9)
A new SPICE model for organic molecular transistors and a novel hybrid architecture (2012) (8)
From multivalued current mode CMOS circuits to efficient voltage mode CMOS arithmetic operators (1995) (8)
Design of Ultra Low Power Ternary Half Adder and Multiplier for Nanotechnology (2016) (8)
A Fully Parallel Reverse Converter (2007) (8)
Voltage mirror circuit by carbon nanotube field effect transistors for mirroring dynamic random access memories in multiple-valued logic and fuzzy logic (2015) (8)
Modeling the effects of hot-spot traffic load on the performance of wormhole-switched hypermeshes (2011) (8)
From static ternary adders to high-performance race-free dynamic ones (2015) (8)
A novel FPGA-programmable switch matrix interconnection element in quantum-dot cellular automata (2015) (8)
Designing high-speed, low-power full adder cells based on carbon nanotube technology (2014) (8)
Rotation-Based Design and Synthesis of Quantum Circuits (2016) (8)
A capacitive multi-threshold threshold gate design to reach a high-performance PVT-tolerant 4:2 compressor by carbon nanotube FETs (2018) (7)
Towards Approximate Computing with Quantum-Dot Cellular Automata (2017) (7)
Coplanar Architecture for Quantum-Dot Cellular Automata Systolic Array Design (2013) (7)
New Current-Mode Multipliers by CNTFET-Based n-Valued Binary Converters (2016) (7)
CNFET Based Basic Gates and a Novel FullAdder Cell (2012) (7)
Novel Optimum Parity-Preserving Reversible Multiplier Circuits (2020) (7)
Low Power Dynamic CMOS Full-Adder Cell (2015) (7)
Maximally Redundant High-Radix Signed-Digit Adder: New Algorithm and Implementation (2009) (7)
Efficient radix-r adders for nanoelectronics (2016) (7)
A New Full Adder Cell for Molecular Electronics (2011) (7)
A Six Transistors Full Adder (2008) (7)
Performance analysis and simulation of two different architectures of (6:3) and (7:3) compressors based on carbon Nano-Tube Field Effect Transistors (2013) (7)
Efficient RNS to binary converters for the new 4-moduli set {2n, 2n+1-1, 2n-1, 2n-1-1} (2012) (7)
High-performance ternary operators for scrambling (2017) (7)
A Simplified Modulo (2n-1) Squaring Scheme for Residue Number System (2005) (7)
New high-performance majority function based full adders (2009) (7)
High-Performance CML approximate full adders for image processing application of laplace transform (2020) (6)
An Optimum Moduli Set in Residue Number System (2010) (6)
Well-Polarized Quantum-dot Cellular Automata Inverters (2012) (6)
A Single Parity-Check Digit for One Trit Error Detection in Ternary Communication Systems: Gate-Level and Transistor-Level Designs (2017) (6)
Delay Reduction in Optimized Reversible Multiplier Circuit (2012) (6)
Ultra High Speed CNFET Full-Adder Cell Based on Majority Gates (2010) (6)
A new approach for designing compressors with a new hardware-friendly mathematical method for multi-input XOR gates (2017) (6)
Novel ensemble method for the prediction of response to fluvoxamine treatment of obsessive–compulsive disorder (2018) (6)
A High Speed Residue-to-Binary Converter for Balanced 4-Moduli Set (2016) (6)
Low Power Modulo 2n+1 Adder Based on Carry Save Diminished-One Number System (2008) (6)
Design and Implementation of a Three-operand Multiplier through Carbon Nanotube Technology (2015) (6)
Improving rule based classification using harmony search (2019) (6)
A basis for the comparison of binary and m-valued current mode circuits: the multioperand addition with redundant number systems (1993) (5)
New dynamic ternary minimum and maximum circuits with reduced switching activity and without any additional voltage sources (2015) (5)
Using Car Semi-Active Suspension Systems To Decrease Undesirable Effects Of Road Excitations On Human Health (2006) (5)
Improving the Teleportation Cost in Distributed Quantum Circuits Based on Commuting of Gates (2021) (5)
Efficient Reverse Converters for 4-Moduli Sets {2$$^{2n-1}-1$$2n-1-1, 2$$^{n}$$n, 2$$^{n}+1$$n+1, 2$$^{n}-1$$n-1} and {2$$^{2n-1}$$2n-1, 2$$^{2n-1}-1$$2n-1-1, 2$$^{n}+1$$n+1, 2$$^{n}-1$$n-1} Based on CRTs Algorithm (2014) (5)
Efficient Reverse Converter Design for Five Moduli (2012) (5)
Parallel Lagrange interpolation on k-ary n-cubes with maximum channel utilization (2008) (5)
Toward efficient implementation of basic balanced ternary arithmetic operations in CNFET technology (2019) (5)
Ultra-Low Cost Full Adder Cell Using the nonlinear effect in Four-Input Quantum Dot Cellular Automata Majority Gate (2020) (5)
A design procedure for fan-out improvement in all-optical photonic crystal logic design (2019) (5)
Design of a Low-Voltage High-Speed Switched-Capacitor Filters Using Improved Auto Zeroed Integrator (2008) (5)
Multi-V t Ternary Circuits by Carbon Nanotube Filed Effect Transistor Technology for Low-Voltage and Low-Power Applications (2014) (5)
An Efficient Analog-to-Digital Converter Based on Carbon Nanotube FETs (2016) (5)
An efficient cntfet-based 7-input minority gate (2013) (5)
High-performance ternary logic gates for nanoelectronics (2015) (5)
A novel digital fuzzy system for image edge detection based on wrap-gate carbon nanotube transistors (2020) (5)
New Modules for Quantum-dot Cellular Automata AND & OR Gates (2012) (5)
Physical proof and design of ternary full adder circuit in ternary quantum‐dot cellular automata technology (2022) (4)
A new design of reverse converter for a three-moduli set (2009) (4)
Design and Implementation of an ASIP-Based Crypto Processor for IDEA and SAFER K-64 (2012) (4)
A High Dynamic Range 3-Moduli-Set with Efficient Reverse Converter (2009) (4)
A Robust Encrypted Nanocommunication in QCA Circuit (2021) (4)
High Speed Implementation of r n Moduli (2008) (4)
Ternary DDCVSL: a combined dynamic logic style for standard ternary logic with single power source (2020) (4)
Performance Modeling of Wormhole Hypermeshes Under Hotspot Traffic (2007) (4)
Spin-Based Imprecise 4-2 Compressor for Energy-Efficient Multipliers (2019) (4)
High-Speed Arithmetic Algorithms for Multiple-valued Logics in Mixed-Mode (2006) (4)
Analytical performance evaluation of molecular logic circuits (2012) (4)
Ternary inverter gate designs using OPV5-based single-molecule field-effect transistors (2020) (4)
A novel 3D three/five-input majority-based full adder in nanomagnetic logic (2019) (4)
An Efficient Versatile Logic Cell for Single-Electron Technology (2014) (4)
Ternary Versus Binary Multiplication with Current-Mode CNTFET-Based K-Valued Converters (2016) (4)
A High-Efficient Multi-Output Mixed Dynamic/Static Single-Bit Adder Cell (2013) (3)
Noise Margin Calculation in Multiple-Valued Logic (2020) (3)
Performance evaluation of In-Circuit Testing on QCA based circuits (2008) (3)
Physic-Based Imaginary Potential and Incoherent Current Models for RTD Simulation Using Optical Model (2008) (3)
Robust Carbon Nanotube Field Effect Transistor-Based Penternary Logic Circuits (2014) (3)
Ternary cyclic redundancy check by a new hardware-friendly ternary operator (2016) (3)
Minimization of Multiple-Valued Decision Diagrams Based on Matrix Computation (2008) (3)
Efficient programmable power‐of‐two scaler for the three‐moduli set {2n+p, 2n − 1, 2n+1 − 1} (2020) (3)
Efficient CNFET-based Rectifiers for Nanoelectronics (2013) (3)
Improving rule-based classification using Harmony Search (2019) (3)
High-speed energy efficient process, voltage and temperature tolerant hybrid multi-threshold 4: 2 compressor design in CNFET technology (2020) (3)
Study of the Reverse Converters for the Large Dynamic Range Four-Moduli Sets (2011) (3)
A Novel Device to Implement Full Set of Three-Input Logic Gates Using a Naphthalene-Based Single-Molecule Field-Effect Transistor (2021) (3)
Efficient Ternary Galois Field Circuit Design Through Carbon Nanotube Technology (2008) (3)
Novel ternary adders and subtractors in quantum cellular automata (2022) (3)
A novel reversible design for double edge triggered flip-flops and new designs of reversible sequential circuits (2014) (3)
A New Moduli Set {3n - 1,3n+1,3n + 2,3n - 2} in Residue Number System (2008) (3)
Fluvoxamine treatment response prediction in obsessive-compulsive disorder: association rule mining approach (2019) (3)
Imprecise Minority-Based Full Adder for Approximate Computing Using CNFETs (2019) (2)
Novel implementation of 3D multiplexers in nano magnetic logic technology (2020) (2)
Partial product generation for unbalanced ternary signed multiplication (2019) (2)
Novel single-trit comparator circuits in ternary quantum-dot cellular automata (2022) (2)
Energy efficient hybrid full adder design for digital signal processing in nanoelectronics (2021) (2)
Novel Architecture for IEEE-754 Standard (2006) (2)
Efficient Incorporation of the RNS Datapath in Reverse Converter (2021) (2)
A new low power full adder cell in CMOS inverter (2010) (2)
High-performance bridge-style full adder structure (2008) (2)
Redundant Multi-Level one-hot Residue Number System based error correction codes (2010) (2)
An Efficient 5‐Input Exclusive‐OR Circuit Based on Carbon Nanotube FETs (2014) (2)
Implementing RNS Arithmetic unit through Single Electron Quantum-dot Cellular Automata (2017) (2)
Energy Consumption Optimization for Basic Arithmetic Circuits with Transistor Sizing Based on Genetic Algorithm (2009) (2)
Classification of EEG-based motor imagery BCI by using ECOC (2019) (2)
High Dynamic Range RNS Bases for Modular Multiplication (2011) (2)
Two Novel Current-Mode CNFET-Based Full Adders Using ULPD as Voltage Regulator (2020) (2)
A New High-Speed Low Power Consumption Multiplier (2007) (2)
Designing sustainable nano-electronic base gates using aromatic molecules structures (2013) (2)
Designing Nanoelectronic-Compatible 8-bit Square Root Circuit by Quantum-Dot Cellular Automata (2015) (2)
Design of Low Voltage and High-Speed BiCMOS Buffer for Driving Large Load Capacitor (2016) (2)
A Novel Full Subtractor /Full Adder Design in Quantum Cellular Automata (2021) (2)
Robust fuzzy SRAM for accurate and ultra-low-power MVL and fuzzy logic applications (2016) (2)
Performance Comparison of High-Speed High-Order (n:2) and (n:3) CNFET-Based Compressors (2013) (2)
New Current-Mode Ternary Full Adder Circuits Based on Carbon Nanotube Field Effect Transistor Technology (2016) (2)
Multiple-valued Interconnection Network (2006) (1)
A Novel Reversible Adder/Subtractor with Overflow Detection (2016) (1)
A Novel Design of Reversible Squarer Circuit (2013) (1)
Design of a New High-Speed and High-Performance Full Adder Cell Based on Carbon Nanotube Field Effect Transistors (2016) (1)
A symmetric quantum-dot cellular automata design for 5-input majority gate (2014) (1)
Optimal selection of ensemble classifiers using particle swarm optimization and diversity measures (2019) (1)
Introducing Coplanar Wire Crossing in Ternary Quantum Cellular Automata (2015) (1)
Systematic Transistor Sizing of a CNFET-Based Ternary Inverter for High Performance and Noise Margin Enlargement (2022) (1)
Reducing Harmful Effects Of Road Excitations On Human Health By Designing Car Active Suspension Systems (2006) (1)
A new algorithm for determining all possible symmetric hybrid redundant numbers (2009) (1)
A New Switched opamp Approach for Improving the Operation of Auto-Reset Switched-capacitor Filters (2011) (1)
High Performance and Low Power Half-Adder Cells in Carbon Nanotube Field Effect Transistor Technology (2015) (1)
Reliable and Secure Chip Level Communication by residue number System Code (2008) (1)
Design of an energy-efficient CNFET Full Adder Cell (2012) (1)
A Novel Design of Ternary Galois Field Based on Carbon Nano Tube FETs (2009) (1)
A novel structure for realization of a pseudo two path band-pass filter (2008) (1)
Area-delay-power-aware adder placement method for RNS reverse converter design (2016) (1)
Four Moduli RNS Bases for Efficient Design of Modular Multiplication (2011) (1)
Dealing with mixed data types in the obsessive-compulsive disorder using ensemble classification (2019) (1)
Resource-aware system architecture model for implementation of quantum aided Byzantine agreement on quantum repeater networks (2017) (1)
Design of new NAND/NOR gates in QCA using single electron cells (2016) (1)
Full Adder and Full Subtractor Design in Quantum Cellular Automata (2021) (1)
On the Design of RNS Bases for Modular Multiplication (2014) (1)
DESIGN OF A LOW-PASS SWITCHED CAPACITOR FOURTH ORDER CHEBYSHEV FILTER USING AN IMPROVED AUTO ZERO INTEGRATOR (2007) (1)
An Energy- and Area-Efficient Approximate Ternary Adder Based on CNTFET Switching Logic (2017) (1)
Image encryption and decryption using exclusive-OR based on ternary value logic (2022) (1)
Single Electron Quantum-Dot Cellular Automata, A Novel Device for Nano Scale Computations (2016) (1)
Efficient forward and reverse converters for a new high-radix moduli set (2008) (1)
A Multiplier-Free Residue to Weighted Converter for the Moduli Set {3 n - 2, 3 n - 1, 3 n } (2008) (1)
Fast and energy-efficient FPGA realization of RNS reverse converter for the ternary 3-moduli set {3n–2, 3n–1, 3n} (2020) (1)
Design and Evaluation of an Efficient Carbon Nano-Tube Field Effect Transistor-Based Ternary Full Adder Cell for Nanotechnology (2014) (1)
Reconfigurable Quantum Circuits by Photonic Devices (2016) (0)
AN OPTIMUM ONE-HOT TWO-LEVEL REDUNDANT RESIDUE NUMBER SYSTEM BASED ERROR CORRECTION AND DETECTION (2011) (0)
A novel design approach for T‐XOR gate in ternary quantum‐dot cellular automata circuits (2022) (0)
Toffoli (CCNOT) reversible suggested gate based on Degenerate Four Wave Mixing method (2019) (0)
CAST-WSN: The Presentation of New Clustering Algorithm Based on Steiner Tree and C-Means Algorithm Improvement in Wireless Sensor Networks (2017) (0)
Resource-aware architecture for implementation of quantum aided Byzantine agreement on quantum repeater networks (2017) (0)
Reversible quantum communication & systems (2022) (0)
Autonomous Estimation of Patients’ Neuropsychological State Using Convolutional Neural Networks (2019) (0)
Ternary inverter gate designs using OPV5-based single-molecule field-effect transistors (2020) (0)
A NovelDCVSTreeReduction Algorithm (2006) (0)
A New Molecular 5:3 Compressor Cell Based on Benzene Rings (2013) (0)
A Novel Quantum-dot Cellular Automata Design for Two-input XOR Gate (2016) (0)
Configurable all-optical photonic crystal XOR/AND and XNOR/NAND logic gates (2020) (0)
A low-power high-speed hybrid multi-threshold full adder design in CNFET technology (2018) (0)
A NEW BICMOS CIRCUIT FOR DRIVING LARGE CAPACITIVE LOAD (2008) (0)
Efficient Implementation of RNS Montgomery Multiplication Using Balanced RNS Bases (2014) (0)
A low-power and robust quaternary SRAM cell for nanoelectronics (2022) (0)
Design and Evaluation of CNFET-Based Quaternary Circuits (2012) (0)
A capacitive multi-threshold threshold gate design to reach a high-performance PVT-tolerant 4:2 compressor by carbon nanotube FETs (2017) (0)
A novel low power Exclusive-OR via cell level-based design function in quantum cellular automata (2017) (0)
Design of High Speed and Low Power 32-bit Multiplier by using Compressor blocks in CNTFET Technology (2015) (0)
Quaternary full adder cells based on carbon nanotube FETs (2015) (0)
Pull Down Network Minimization, Based on Equivalent Functions Concept, in DCVS Circuit Design (2007) (0)
A novel ternary half adder and multiplier based on carbon nanotube field effect transistors (2017) (0)
Nonlinear effect of changing the temperature to overcome Covid-19 (2020) (0)
NOVEL DCVS REDUCTION ALGORITHM BASED ON A NEW LEVELS COUPLING RULE (2007) (0)
Energy-Efficient Approximate Compressor Design for Error-Resilient Digital Signal Processing (2022) (0)
A Novel Design Approach for Multi-input XOR Gate Using Multi-input Majority Function (2014) (0)
A novel single electron technology cell based on majority logic gate (2012) (0)
The nonlinear effect in the performance of 4:2 Compressor (2021) (0)
Design and analysis of carbon nanotube FET based quaternary full adders (2016) (0)
A HIGH SPEED MIXED MODE 4:2 COMPRESSOR (2006) (0)
A novel 3D three/five-input majority-based full adder in nanomagnetic logic (2019) (0)
High speed, low power and approximated current mode XOR in secure image applications based on CNT (2017) (0)
The Effect of Quantum Interferences on Emitter Current of Resonant Tunneling Diode and A New Definition for Quantum Capacitance (2013) (0)
ARGAN: Fast Converging GAN for Animation Style Transfer (2022) (0)
CNFET-Based Design of Energy-Efficient Symmetric Three-Input XOR and Full Adder Circuits (2013) (0)
A Novel Design Approach for Ternary Compressor Cells Based on CNTFETs (2015) (0)
High-Performance Mixed-Mode Universal Min-Max Circuits for Nanotechnology (2011) (0)
A New Bio Inspired Majority Device MAJ (A, B, C) (2019) (0)
Circuits multivalues en mode courant et operateurs arithmetiques (1995) (0)
Design and analysis of efficient QCA reversible adders (2018) (0)
Brain Functional Connectivity Changes During Learning of Time Discrimination (2022) (0)
Design of an energy--CNFET Full Adder Cell efficient CNFET Full Adder Cell efficient CNFET Full Adder Cell efficient CNFET Full Adder Cell (2012) (0)
Robust Coplanar Full Adder Based on Novel Inverter in Quantum Cellular Automata (2018) (0)
Novel efficient full adder and full subtractor designs in quantum cellular automata (2019) (0)
Identification of Asperger's from healthy individuals: Using a graph theoretical approach on the task-free fMRI data (2019) (0)
Optimized Reversible Square Root Circuit (2017) (0)
Analytical Review of Noise Margin in MVL: Clarification of a Deceptive Matter (2019) (0)

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