Michael Peter Kennedy
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Computer Science
Michael Peter Kennedy's Degrees
- PhD Computer Science Stanford University
- Masters Artificial Intelligence University of California, Berkeley
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(Suggest an Edit or Addition)Michael Peter Kennedy's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- Neural networks for nonlinear programming (1988) (1082)
- Chaos shift keying : modulation and demodulation of a chaotic carrier using self-sychronizing chua"s circuits (1993) (811)
- The role of synchronization in digital communications using chaos. II. Chaotic modulation and chaotic synchronization (1998) (457)
- Chaos in the Colpitts oscillator (1994) (399)
- Robust OP Amp Realization of Chua's Circuit (1992) (398)
- The role of synchronization in digital communications using chaos. I . Fundamentals of digital communications (1997) (351)
- Construction of classes of circuit-independent chaotic oscillators using passive-only nonlinear devices (2001) (247)
- Nonlinear analysis of the Colpitts oscillator and applications to design (1999) (238)
- Three steps to chaos. II. A Chua's circuit primer (1993) (210)
- Chaotic communications with correlator receivers: theory and performance limits (2002) (156)
- Digital communications using chaos (2000) (150)
- Performance evaluation of FM-DCSK modulation in multipath environments (2000) (134)
- Improved implementation of Chua's chaotic oscillator using current feedback op amp (2000) (128)
- FM-DCSK: A robust modulation scheme for chaotic communications (1998) (124)
- Creation of a complex butterfly attractor using a novel Lorenz-Type system (2002) (116)
- Unifying the Tank and Hopfield linear programming circuit and the canonical nonlinear programming circuit of Chua and Lin (1987) (107)
- Communications using chaos/spl Gt/MINUS. III. Performance bounds for correlation receivers (2000) (105)
- Van der Pol and chaos (1986) (102)
- Three steps to chaos. I. Evolution (1993) (99)
- Three Steps to Chaos-Part I: Evolution (1993) (95)
- Maximum Sequence Length MASH Digital Delta–Sigma Modulators (2007) (93)
- Nonsmooth bifurcations in a piecewise linear model of the Colpitts Oscillator (2000) (87)
- The role of synchronization in digital communications using chaos | Part III: Performance bounds for (2000) (84)
- Three Steps to Chaos-Part 11: A Chua's Circuit Primer (1993) (76)
- FM-DCSK: a novel method for chaotic communications (1998) (72)
- The Colpitts oscillator: Families of periodic solutions and their bifurcations (2000) (68)
- Experimental Verification of the Butterfly Attractor in a Modified Lorenz System (2002) (68)
- Hysteresis in electronic circuits: A circuit theorist's perspective (1991) (61)
- A Fast and Simple Implementation of Chua's oscillator with cubic-like Nonlinearity (2005) (59)
- Chaotic oscillator configuration using a frequency dependent negative resistor (1999) (54)
- An equation for Generating Chaos and its monolithic Implementation (2002) (52)
- On the relationship between the chaotic Colpitts oscillator and Chua's oscillator (1995) (51)
- Mathematical analysis of digital MASH delta-sigma modulators for fractional-N frequency synthesizers (2006) (50)
- Chaotic communications without synchronization (1998) (49)
- Chua's circuit decomposition: a systematic design approach for chaotic oscillators (2000) (49)
- Enhanced versions of DCSK and FM-DCSK data transmission systems (1999) (48)
- A Four-Wing Butterfly Attractor from a Fully Autonomous System (2003) (46)
- Minimizing Spurious Tones in Digital Delta-Sigma Modulators (2011) (45)
- A system for chaos generation and its implementation in monolithic form (2000) (45)
- On the robustness of R-2R ladder DACs (2000) (44)
- High frequency Wien-type chaotic oscillator (1998) (44)
- The devil's staircase - The electrical engineer's fractal (1989) (42)
- A semi-systematic procedure for producing chaos from sinusoidal oscillators using diode-inductor and FET-capacitor composites (2000) (41)
- Recent advances in communicating with chaos (1998) (38)
- Mathematical Analysis of a Prime Modulus Quantizer MASH Digital Delta–Sigma Modulator (2007) (35)
- Linear model-based testing of ADC nonlinearities (2004) (34)
- A CMOS Injection-Locked Frequency Divider Optimized for Divide-by-Two and Divide-by-Three Operation (2013) (33)
- Observations Concerning the Locking Range in a Complementary Differential $LC$ Injection-Locked Frequency Divider—Part I: Qualitative Analysis (2010) (32)
- A rigorous exposition of the LEMMA method for analog and mixed-signal testing (1999) (30)
- Chaotic Modulation for Robust Digital Communications over Multipath Channels (2000) (30)
- A family of Colpitts-like chaotic oscillators (1999) (30)
- Generic RC realizations of Chua's Circuit (2000) (29)
- Reduced Complexity MASH Delta–Sigma Modulator (2007) (29)
- Systematic realization of a class of hysteresis chaotic oscillators (2000) (28)
- Inductorless hyperchaos generator (1999) (28)
- Statistical Properties of First-Order Bang-Bang PLL With Nonzero Loop Delay (2008) (27)
- A general method to predict the amplitude of oscillation in nearly sinusoidal oscillators (2004) (26)
- Behavioral modeling of charge pump phase locked loops (1999) (25)
- Hardware Reduction in Digital Delta-Sigma Modulators Via Error Masking - Part I: MASH DDSM (2009) (25)
- On the Synchronization Condition for Superharmonic Coupled QVCOs (2011) (24)
- Experimental demonstration of binary chaos-shift keying using self-synchronising chua"s circuits (1993) (23)
- Chaotic Oscillators Derived from Sinusoidal Oscillators Based on the Current Feedback Op Amp (2000) (23)
- Hardware Reduction in Digital Delta-Sigma Modulators Via Bus-Splitting and Error Masking—Part I: Constant Input (2011) (22)
- The Role of Charge Pump Mismatch in the Generation of Integer Boundary Spurs in Fractional-N Frequency Synthesizers: Why Worse Can Be Better (2013) (21)
- Observations Concerning the Locking Range in a Complementary Differential $LC$ Injection-Locked Frequency Divider—Part II: Design Methodology (2011) (20)
- Prediction of Phase Noise and Spurs in a Nonlinear Fractional- ${N}$ Frequency Synthesizer (2019) (20)
- Secure communication via Chua"s circuit (1993) (20)
- Observations Concerning the Generation of Spurious Tones in Digital Delta-Sigma Modulators Followed by a Memoryless Nonlinearity (2011) (20)
- A low-voltage, low-power, chaotic oscillator, derived from a relaxation oscillator (2000) (19)
- Experimental chaos from autonomous electronic circuits (1995) (19)
- Calculation of sequence lengths in MASH 1-1-1 digital delta sigma modulators with a constant input (2007) (19)
- SYNCHRONIZATION THEOREM FOR A CHAOTIC SYSTEM (1995) (19)
- Chaotic Oscillators Derived from Saito’s Double-Screw Hysteresis Oscillator (1999) (18)
- Influence of noise intensity on the spectrum of an oscillator (2004) (18)
- Architectures for Maximum-Sequence-Length Digital Delta-Sigma Modulators (2008) (18)
- A fast and simple implementation of Chua's oscillator using a "cubic-like" Chua diode (2005) (18)
- Novel chaotic oscillator configuration using a diode-inductor composite (2000) (16)
- Masked Dithering of MASH Digital Delta-Sigma Modulators With Constant Inputs Using Multiple Linear Feedback Shift Registers (2017) (16)
- Accurate modeling and experimental validation of an injection-locked frequency divider (2005) (16)
- Hardware Reduction in Digital Delta-Sigma Modulators via Bus-Splitting and Error Masking—Part II: Non-Constant Input (2012) (15)
- Prediction of the Spectrum of a Digital Delta–Sigma Modulator Followed by a Polynomial Nonlinearity (2010) (14)
- Optimizing the design of an injection-locked frequency divider by means of nonlinear analysis (2007) (14)
- Analysis and Design of Injection-Locked Frequency Dividers by Means of a Phase-Domain Macromodel (2010) (13)
- Electronic chaos controller (1997) (13)
- A technique to reduce flicker noise up-conversion in CMOS LC voltage-controlled oscillators (2004) (12)
- Recent results for chaotic modulation schemes (2001) (12)
- Test Development Through Defect and Test Escape Level Estimation for Data Converters (2006) (12)
- Observations and Analysis of Wandering Spurs in MASH-Based Fractional- $N$ Frequency Synthesizers (2018) (12)
- Spurious tones in digital delta-sigma modulators resulting from pseudorandom dither (2015) (12)
- Calculation of Cycle Lengths in Higher Order Error Feedback Modulators With Constant Inputs (2011) (12)
- Synchronization of chaotic signals (1993) (11)
- Experimental characterization of Arnold tongues in injection-locked CMOS LC frequency dividers with tail and direct injection (2011) (11)
- Linear model-based error identification and calibration for data converters (2003) (11)
- Noise-Shaping All-Digital Phase-Locked Loops (2014) (11)
- Three-phase oscillator modified for chaos (1999) (10)
- Bispectral Analysis of Chua's Circuit (1993) (10)
- Masked Dithering of MASH Digital Delta-Sigma Modulators with Constant Inputs Using Linear Feedback Shift Registers (2016) (10)
- Observations concerning PFD/CP operating point offset strategies for combatting static charge pump mismatch in fractional-N frequency synthesizers with digital delta-sigma modulators (2014) (9)
- An approximate analytical approach for predicting period-doubling in the Colpitts oscillator (1998) (9)
- Comparison of ring and LC oscillator-based ILFDs in terms of phase noise, locking range, power consumption and quality factor (2009) (9)
- The Devil's Staircase as a method of comparing injection-locked frequency divider topologies (2005) (9)
- Hardware Reduction in Digital Delta–Sigma Modulators Via Error Masking—Part II: SQ-DDSM (2009) (9)
- 4.48-GHz Fractional- ${N}$ Frequency Synthesizer With Spurious-Tone Suppression via Probability Mass Redistribution (2019) (9)
- A novel implementation of dithered digital delta-sigma modulators via bus-splitting (2011) (9)
- 16.9 4.48GHz 0.18μm SiGe BiCMOS Exact-Frequency Fractional-N Frequency Synthesizer with Spurious-Tone Suppression Yielding a -80dBc In-Band Fractional Spur (2019) (8)
- A Spur-Free MASH DDSM With High-Order Filtered Dither (2011) (8)
- A fast charge pump PLL using a bang-bang frequency comparator with dead zone (2012) (8)
- Locking range analysis for injection-locked frequency dividers (2006) (8)
- Observations concerning noise floor and spurs caused by static charge pump mismatch in fractional-N frequency synthesizers (2014) (8)
- A NONLINEAR DYNAMICS INTERPRETATION OF ALGORITHMIC A/D CONVERSION (1995) (8)
- Influence of Initial Conditions on the Fundamental Periods of LFSR-Dithered MASH Digital Delta–Sigma Modulators With Constant Inputs (2017) (8)
- Jitter Minimization in Digital PLLs with Mid-Rise TDCs (2020) (8)
- Overcoming Test Setup Limitations by Applying Model-Based Testing to High-Precision ADCs (2005) (7)
- A spur-free MASH digital delta-sigma modulator with higher order shaped dither (2009) (7)
- A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs (2021) (7)
- Implementation of model-based testing for medium- to high-resolution Nyquist-rate ADCs (2002) (7)
- Modeling and Simulation of Delta-Sigma Fractional-N PLL Frequency Synthesizer in Verilog-AMS (2007) (7)
- The noise and spur delusion in fractional-N frequency synthesizer design (2015) (7)
- Determination of main system parameters of FM-DCSK telecommunications system (2000) (7)
- Analysis of Wandering Spur Patterns in a Fractional- $N$ Frequency Synthesizer With a MASH-Based Divider Controller (2020) (7)
- Spurious tones in digital delta sigma modulators with pseudorandom dither (2013) (7)
- Accurate baseband model for sampling phase-locked loop (1999) (6)
- Devaney Chaos in an Approximate One-Dimensional Model of the Colpitts Oscillator (1997) (6)
- Synthesis of continuous three-segment voltage-controlled piecewise-linear resistors for Chua's circuit family using operational amplifiers, diodes and linear resistors (1993) (6)
- Comments on efficient dithering in digital delta-sigma modulator (2014) (6)
- A feedback chaos controller: theory and implementation (1996) (6)
- Modelling and Verification of Nonlinear Electromechanical Coupling in Micro-Scale Kinetic Electromagnetic Energy Harvesters (2020) (6)
- LEMMA-ADC: the linear error mechanism modelling algorithm applied to A/D-converters (1999) (5)
- Comparison of a feed-forward phase domain model and a time domain behavioral model for predicting mismatch-related noise floor and spurs in fractional-N frequency synthesizers (2015) (5)
- Comparative spur performance of a fractional-N frequency synthesizer with a nested MASH-SQ3 divider controller in the presence of memoryless piecewise-linear and polynomial nonlinearities (2014) (5)
- Phenomenological study of an injection-locked CMOS LC frequency divider with direct injection (2011) (5)
- A qualitative analysis of a complementary differential LC injection-locked frequency divider based on direct injection (2010) (5)
- Testing ADCs for static and dynamic INL - killing two birds with one stone (2004) (5)
- Estimating the locking range of analog dividers through a phase-domain macromodel (2010) (5)
- Recent advances in the analysis, design and optimization of Digital Delta-Sigma Modulators (2012) (5)
- Wandering Spurs in MASH 1-1 Delta-Sigma Modulators (2019) (5)
- Ten Statement Fortran Plus Fortran IV (1970) (5)
- An enhanced model for thin film resistor matching (2009) (5)
- Simulation of the multipath performance of FM-DCSK digital communications using chaos (1999) (5)
- Innovation to overcome limitations of test equipment (2005) (5)
- A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter (2021) (4)
- A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping (2022) (4)
- Noise reduction in fractional-N frequency synthesizers with multiphase VCO (2007) (4)
- Design Methodology for Autonomous Chaotic Oscillators (2002) (4)
- Phase noise and spur performance limits for fractional-N frequency synthesizers (2015) (4)
- The optimum power conversion efficiency and associated gain of an LC CMOS oscillator (2006) (4)
- Digital Signal Processor-Based Investigation of Chua's Circuit Family (1993) (4)
- Synchronization of dynamical systems : recent progress, potential applications and limitations (1995) (4)
- The LEMMA developer's toolbox: semi-automated test development for analog and mixed-signal circuits (1998) (4)
- Influence of Initial Condition on Wandering Spur Pattern in a MASH-Based Fractional-N Frequency Synthesizer (2020) (4)
- A “divide-by-odd number” direct injection CMOS LC injection-locked frequency divider (2012) (4)
- First Order Noise Shaping Local-Oscillator Based Time-to-Digital Converter (2010) (4)
- 0.3–4.3 GHz Frequency-Accurate Fractional-$N$ Frequency Synthesizer With Integrated VCO and Nested Mixed-Radix Digital $\Delta$-$\Sigma$ Modulator-Based Divider Controller (2014) (4)
- ABC (ADVENTURES IN BIFURCATIONS AND CHAOS): A PROGRAM FOR STUDYING CHAOS (1994) (4)
- ELABORATION OF SYSTEM SPECIFICATION FOR A WLAN FM-DCSK TELECOMMUNICATIONS SYSTEM (2000) (3)
- A Design Method for Nested MASH-SQ Hybrid Divider Controllers for Fractional- $N$ Frequency Synthesizers (2018) (3)
- A high-throughput spur-free hybrid nested bus-splitting/HK-MASH digital delta-sigma modulator (2013) (3)
- Logic, Planning, and Computers: ProLog (1987) (3)
- Model-based testing of high-resolution ADCs (2000) (3)
- Structured PL/ZERO plus PL/ONE (1977) (3)
- Process Deviations and Spot Defects: Two Aspects of Test and Test Development for Mixed-Signal Circuits (2001) (3)
- Yet another spur mechanism in a charge-pump based Fractional-N PLL (2016) (3)
- Spur Immunity in MASH-Based Fractional-N CP-PLLs With Polynomial Nonlinearities (2021) (3)
- 32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays (2021) (3)
- Qualitative nonlinear circuit analysis using computers (1986) (3)
- Comparative analysis of differential colpitts and cross-coupled VCOs in 180 nm Si-Ge HBT technology (2016) (3)
- Applications of chaos in communications (1997) (3)
- Correlator-Based Chaotic Communications: Attainable Noise and Multipath Performance (2002) (3)
- Performance analysis of low power high speed pipelined adders for digital /spl Sigma//spl Delta/ modulators (2006) (3)
- Calculation of cycle lengths in higher-order MASH DDSMs with constant inputs (2010) (3)
- Mitigation of “Horn Spurs” in a MASH-Based Fractional-N CP-PLL (2020) (3)
- A high frequency “divide-by-odd number” CMOS LC injection-locked frequency divider (2013) (3)
- Comparison of analytical predictions of the noise floor due to static charge pump mismatch in fractional-n frequency synthesizers (2016) (3)
- A novel dual-loop multi-phase frequency synthesizer (2007) (3)
- A nested digital delta-sigma modulator architecture for fractional-N frequency synthesis (2010) (3)
- Effective (Spur-Free) dithering of digital delta-sigma modulators with pseudorandom dither (2015) (3)
- Maximum Sequence Length MASH Digital (2007) (3)
- An explicit expression for the output amplitude of the Colpitts oscillator (1999) (3)
- MASH-Based Divider Controllers for Mitigation of Wandering Spurs in a Fractional-N Frequency Synthesizer (2020) (3)
- Heterodimensional FET with split drain (2004) (3)
- Comparison of resistor matching performance of polysilicon films in a CMOS process (2009) (3)
- High speed, high accuracy fractional-N frequency synthesizer using nested mixed-radix digital Δ-Σ modulators (2013) (2)
- Hardware reduction in digital MASH delta-sigma modulators via error masking (2008) (2)
- Programmable analog frequency divider based on ρ-switching (2013) (2)
- High-Speed Nested Cascaded MASH Digital Delta-Sigma Modulator-Based Divider Controller (2018) (2)
- MASH DDSM-Induced Spurs in a Fractional-$N$ Frequency Synthesizer (2019) (2)
- Novel Approach to Modelling Electromechanical Coupling and Testing its Self-Consistency in Micro-Scale Kinetic Electromagnetic Energy Harvesters (2018) (2)
- Folded Noise Prediction in Nonlinear Fractional-N Frequency Synthesizers (2021) (2)
- An Eight-Phase 40GHz RTWO in 28nm CMOS with Phase Noise Reduction Via Head and Tail Filtering (2019) (2)
- Fat Sensing Using Low-Cost Near-Infrared Spectroscopy (2019) (2)
- A high-speed fourth-order nested bus-splitting error feedback modulator (2012) (2)
- Bifurcation and Chaos (2001) (2)
- Predicting the noise floor at the output of a memoryless piecewise-linear nonlinearity driven by a digital delta-sigma modulator (2012) (2)
- Experimental Confirmation of Wandering Spurs in a Commercial Fractional-N Frequency Synthesizer with a MASH 1-1-1 Divider Controller (2019) (2)
- On the statistical properties of phase noise in Fractional-N frequency synthesizers using successive requantizers (2016) (2)
- Chaotic Modulation Schemes (2018) (2)
- Switched Capacitor Charge Pump Voltage-Controlled Current Source (2018) (2)
- Ultra-fast simulator developed in Matlab environment to evaluate multipath performance of FM-DCSK RF system (1999) (2)
- Hardware reduction in delta-sigma digital-to-analog converters via bus-splitting (2011) (2)
- Comments on the effectiveness of the Szabo and Kolumban solution to false lock in sampling PLL frequency synthesizer (2005) (2)
- Another moving Spur Phenomenon observed in a MASH-based Fractional-N PLL (2019) (2)
- Overview of Digital Communications (2018) (2)
- Design of large signal set for DSCK modulations (1998) (2)
- On the Approximate One-d Map in Chua's oscillator (2005) (2)
- Simulation and experimental investigation of a nonlinear mechanism for spur generation in a fractional-N frequency synthesizer (2012) (2)
- Experimental Verification of Wandering Spur Suppression Technique in a 4.9 GHz Fractional-N Frequency Synthesizer (2021) (2)
- Observations concerning “Horn Spurs” in a MASH-based Fractional-N CP-PLL (2019) (2)
- Improved Nonlinear Model of a Second-Order Charge-Pump Pll (2000) (2)
- Hard-Fault Detection and Diagnosis During the Application of Model-Based Data Converter Testing (2007) (2)
- Ten Statement Fortran Plus Fortran IV: Sensible, Modular, and Structured Programming With Watfor and Watfiv (1974) (1)
- Nonlinearity-induced spurious tones and noise in digitally-assisted frequency synthesizers (2017) (1)
- Analysis of forward body biasing (FBB) in a complementary differential LC injection-locked frequency divider based on direct injection (2010) (1)
- Nonlinearity-Induced Spurs in Fractional-N Frequency Synthesizers (2022) (1)
- Testing ADCs for Static and Dynamic Nonlinearities — Killing two birds with one stone — (2002) (1)
- A method to quantify the dependence of spur heights on offset current in a CP-PLL (2016) (1)
- Incorporation of hard-fault-coverage in model-based testing of mixed-signal ICs (poster paper) (2000) (1)
- Calculation of the cycle length in a HK-MASH DDSM with multilevel quantizers (2010) (1)
- Performance Evaluation of FM-DCSK Modulation in (2000) (1)
- A Curious Result concerning Spur Generation in MASH 1-1-1 based Fractional-N CP-PLLs with a Second-Order Nonlinearity (2020) (1)
- HEALTH CARE REFORM--12 STEPS TO RECOVERY. (2016) (1)
- First order noise shaping in all digital PLLs (2011) (1)
- Design methodology for a divide-by-4 LC injection-locked frequency divider based on nonlinear analysis (2008) (1)
- Design equations and baseband model for double-sampling phase-locked loop (1999) (1)
- Comparison of Mathematical and Physical Phase Noise Performance in Fractional-N Synthesizers (2020) (1)
- Applications of bifurcation analysis to the design of a chaotic Colpitts oscillator (1998) (1)
- On the Robustness of - Ladder DAC's (2000) (1)
- Extending the servo-loop for ADC transition level measurements under dynamic input conditions (2001) (1)
- Nonlinearity-Induced Spurs in Fractional-$N$ Frequency Synthesizers: State of the Art (2019) (1)
- The Switched Injection-Locked Oscillator (SILO) Concept (2014) (1)
- Frequency domain analysis of double sampling phase-locked loop (2000) (1)
- Analysis and Prediction of Spurs in a Fractional-N Frequency Synthesizer with Discontinuous Nonlinearity (2020) (1)
- Chaotic Circuit Behavior (1999) (1)
- Wandering Spurs in MASH-Based Fractional-N Frequency Synthesizers - How They Arise and How to Get Rid of Them (2022) (1)
- Incorporation of hard-fault-coverage in model-based testing of mixed-signal ICs (2000) (1)
- On the synchronization condition of second-harmonic coupled QVCOs (2010) (1)
- Performance limits for open-loop fractional dividers (2017) (1)
- Method of reducing contactor effect when testing high-precision adcs (2003) (1)
- Number 3 (2017) (0)
- Performance Evaluation of FM-DCSK (2018) (0)
- Contributions to the study of nonlinear dynamics and neural networks (1992) (0)
- Comments on “folding of phase noise spectra in charge-pump phase-locked loops induced by frequency division” (2016) (0)
- Developing a strategic error source based design evaluation for ADC's (2005) (0)
- Calculation of cycle lengths in MASH 1-2-2 digital delta sigma modulators with a constant input (2009) (0)
- Comparison of algorithms for computing INL from sinewave histogram (2005) (0)
- Design methodology for a dithered reduced complexity Digital MASH Delta-Sigma Modulator (2008) (0)
- Phase noise in fractional-N frequency synthesizers employing successive requantizers and MASH-SQ hybrids (2017) (0)
- Maximizing Cycle Lengths by Architecture Modification (2011) (0)
- Observations of the differences between closed-loop behavioral and feed-forward model simulations of fractional-N frequency synthesizers (2017) (0)
- Phase Digitization in All-Digital PLLs (2014) (0)
- Maximizing the fundamental period of a dithered digital delta-sigma modulator with constant input (2016) (0)
- Observations on the resolution and tones in First Order Noise Shaping Time-to-Digital Converters (2011) (0)
- An LC CMOS injection-locked frequency divider for divide-by-two and divide-by-three operation (2013) (0)
- Implementation of a pulse-holding Time-to-Digital Converter on an FPGA (2013) (0)
- DDSM and Applications (2011) (0)
- Hardware reduction in higher order MASH Digital Delta-Sigma Modulators via error masking (2010) (0)
- A Family of ΔΣ Modulators With High Spur Immunity and Low Folded Nonlinearity Noise When Used in Fractional- Frequency Synthesizers (2022) (0)
- Technical memorandum. Digital linear transducer using a dynamic RAM (1986) (0)
- High frequency RC chaos generator (1998) (0)
- Influence of a "coupling factor" on the spectrum of a noisy oscillator (2005) (0)
- Structured PL-0 and PL-1 (1977) (0)
- Modelling of Electromagnetic Coupling in Micro-scale Electromagnetic Energy Harvester (2019) (0)
- Analysis and design of an LC oscillator-based injection-locked frequency divider (2008) (0)
- Method of Equivalent Currents for the Calculation of Magnetic Fields in Inductors and Magnets with Application to Electronics (2019) (0)
- Semi-Analytical Method for the Extraction of the System Parameters in Application to Kinetic Energy Harvesters (2019) (0)
- Conventional Techniques for Maximizing Cycle Lengths (2011) (0)
- Wandering Spur Suppression in a 4.9-GHz Fractional-N Frequency Synthesizer (2022) (0)
- Analytical Predictions of Phase Noise in ADPLLs (2014) (0)
- Advantages of Noise Shaping and Dither (2014) (0)
- Comparison of the simulated performance of two divider controllers in a fractional-N frequency synthesizer with a piecewise-linear charge-pump nonlinearity (2016) (0)
- Eight statement PL/C (PL/ZERO) plus PL/ONE (1972) (0)
- Anenhanced modelforthinfilmresistor matching (2009) (0)
- Efficient Modeling and Simulation of Accumulator-Based ADPLLs (2014) (0)
- Flexible Prototyping Platform for Synthesis of Constant Envelope Spread Spectrum (CE-SS) Waveforms (2004) (0)
- Dynamically Reconfigurable Switched-Capacitor DC-DC Converters (2014) (0)
- Modelling and Estimating Phase Noise with Matlab (2014) (0)
- Modelling and implementation of an accumulator-based ADPLL on a Virtex-5 (2012) (0)
- Observations on the relationship between energy transfer efficiency and phase noise in an LC oscillator (2005) (0)
- A high frequency “divide-by-odd number” CMOS LC injection-locked frequency divider (2013) (0)
- Architectures for Maximum-Sequence-Length Digital (2008) (0)
- Analysis of the Oscillator Spectrum to Understand the Effect of the "Coupling Factor" (2006) (0)
- A Unifying Framework for TDC Architectures (2014) (0)
- Use of the Step Invariant Transform to Design a 2nd Order Continuous Time Complex Sigma-Delta ADC (2006) (0)
- The low power and wide tuning range advantages of Armstrong VCOs in 180 nm Si-Ge HBT technology (2016) (0)
- PASCAL : program development with ten instruction PASCAL subset (TIPS) and standard PASCAL (1982) (0)
- Inductorles shyperchao sgenerator (1999) (0)
- Near-Limit Kinetic Energy Harvesting From Arbitrary Acceleration Waveforms: Feasibility Study by the Example of Human Motion (2020) (0)
- An Exposition of Fractional Spurs Resulting From Nonlinear Distortion (2021) (0)
- A random pulse modulation approach to modeling the flicker and white noise of the charge pump of a fractional‐N frequency synthesizer (2022) (0)
- HK-EFM and HK-SQ-DDSM (2011) (0)
- Optimized MASH-SR Divider Controller for Fractional-N Frequency Synthesizers (2023) (0)
- Experimental validation of DAC with nested bus-splitting EFM4 DDSM (2013) (0)
- An Algorithm for Implementing a Modulator Whose Output is Spur-Free After Nonlinear Distortion (2021) (0)
- A comparison of simulation strategies for estimating phase noise in oscillators (2017) (0)
- Measurement Technique for Experimentally Estimating the Phase Sensitivity Function of an Oscillator (2014) (0)
- Chaotic sychronization techniques applies to modulation and demodulation of a chaotic carriers (1993) (0)
- Qualitative analysis as a systematic tool for circuit design (2002) (0)
- Title Linear model-based testing of ADC nonlinearities (2016) (0)
- An improved method for determining the order of discrete-time single-output systems from input-output data (1993) (0)
- A dual-loop frequency synthesizer with a multi-phase VCO (2007) (0)
- Immunity of ENOP-based Fractional-N Frequency Synthesizer to Wandering and Horn Spurs (2022) (0)
- Hardware toolkit for studying chaos: a live demonstration of nonlinear dynamics instrumentation with audience participation (1991) (0)
- Design methodology for a reduced complexity single quantizer digital delta-sigma modulator (2008) (0)
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What Schools Are Affiliated With Michael Peter Kennedy?
Michael Peter Kennedy is affiliated with the following schools:
