Krishnendu Chakrabarty
#74,591
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Electrical and Computer Engineering researcher
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Electrical Engineering
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Krishnendu Chakrabartycomputer-science Degrees
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Engineering Computer Science
Krishnendu Chakrabarty's Degrees
- PhD Electrical Engineering Stanford University
- Masters Electrical Engineering Stanford University
Why Is Krishnendu Chakrabarty Influential?
(Suggest an Edit or Addition)According to Wikipedia, Krishnendu Chakrabarty is an Indian-American electrical and computer engineer. He is the Fulton Professor of Microelectronics at Arizona State University Ira A. Fulton Schools of Engineering. Before joining Arizona State, he was the John Cocke Distinguished Professor and was the Chair of the Department of Electrical and Computer Engineering at Duke University Pratt School of Engineering.
Krishnendu Chakrabarty's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- Sensor deployment and target localization based on virtual forces (2003) (1109)
- Grid Coverage for Surveillance and Target Location in Distributed Sensor Networks (2002) (994)
- Sensor placement for effective coverage and surveillance in distributed sensor networks (2003) (642)
- Sensor deployment and target localization in distributed sensor networks (2004) (561)
- On a New Class of Codes for Identifying Vertices in Graphs (1998) (438)
- Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip (2001) (398)
- System-on-a-chip test-data compression and decompressionarchitectures based on Golomb codes (2001) (370)
- Test Challenges for 3D Integrated Circuits (2009) (327)
- A set of benchmarks for modular testing of SOCs (2002) (324)
- A distributed coverage- and connectivity-centric technique for selecting active nodes in wireless sensor networks (2005) (296)
- On computing mobile agent routes for data fusion in distributed sensor networks (2004) (291)
- Multiresolution data integration using mobile agents in distributed sensor networks (2001) (251)
- Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) Codes (2003) (243)
- Droplet Routing in the Synthesis of Digital Microfluidic Biochips (2006) (234)
- Frequency-directed run-length (FDR) codes with application to system-on-a-chip test data compression (2001) (231)
- Microfluidics-Based Biochips: Technology Issues, Implementation Platforms, and Design-Automation Challenges (2006) (208)
- On using rectangle packing for SOC wrapper/TAM co-optimization (2002) (177)
- High-level synthesis of digital microfluidic biochips (2008) (175)
- Distributed Sensor Networks — a Review of Recent Research (2001) (173)
- A unified approach to reduce SOC test data volume, scan power and testing time (2003) (172)
- Computing reliability and message delay for Cooperative wireless distributed sensor networks subject to random failures (2005) (170)
- Architectural-level synthesis of digital microfluidics-based biochips (2004) (170)
- Energy-aware adaptive checkpointing in embedded real-time systems (2003) (159)
- Unified high-level synthesis and module placement for defect-tolerant microfluidic biochips (2005) (158)
- Nine-coded compression technique for testing embedded cores in SoCs (2005) (156)
- Digital Microfluidic Biochips - Synthesis, Testing, and Reconfiguration Techniques (2006) (156)
- Uncertainty-aware and coverage-oriented deployment for sensor networks (2004) (148)
- P2DAP — Sybil Attacks Detection in Vehicular Ad Hoc Networks (2011) (148)
- Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip (2003) (147)
- Test scheduling for core-based systems using mixed-integer linearprogramming (2000) (144)
- Broadcast electrode-addressing for pin-constrained multi-functional digital microfluidic biochips (2008) (139)
- IEEE Transactions on Circuits and Systems—II:Express Briefs publication information (2018) (133)
- Error Recovery in Cyberphysical Digital Microfluidic Biochips (2013) (130)
- Distributed Mobility Management for Target Tracking in Mobile Sensor Networks (2007) (130)
- Test data compression for system-on-a-chip using Golomb codes (2000) (128)
- Reduction of SOC test data volume, scan power and testing time using alternating run-length codes (2002) (126)
- Test-access mechanism optimization for core-based three-dimensional SOCs (2008) (124)
- Precedence-based, preemptive, and power-constrained test scheduling for system-on-a-chip (2001) (121)
- Combining low-power scan testing and test data compression for system-on-a-chip (2001) (120)
- Cross-contamination avoidance for droplet routing in digital microfluidic biochips (2009) (115)
- Pre-bond probing of TSVs in 3D stacked ICs (2011) (114)
- Module placement for fault-tolerant microfluidics-based biochips (2004) (113)
- Optimization of Dilution and Mixing of Biochemical Samples Using Digital Microfluidic Biochips (2010) (113)
- TSV open defects in 3D integrated circuits: Characterization, test, and optimal spare allocation (2012) (109)
- Location-aided flooding: an energy-efficient data dissemination protocol for wireless-sensor networks (2005) (109)
- Optimal test access architectures for system-on-a-chip (2001) (106)
- Test data compression using dictionaries with selective entries and fixed-length indices (2003) (103)
- Built-in test pattern generation for high-performance circuits using twisted-ring counters (1999) (101)
- Digital microfluidic biochips: A vision for functional diversity and more than moore (2010) (99)
- Design of system-on-a-chip test access architectures using integer linear programming (2000) (99)
- Fault-tolerant training with on-line fault detection for RRAM-based neural computing systems (2017) (98)
- System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints (2002) (98)
- Test Data Compression Using Dictionaries with Fixed-Length Indices (2003) (96)
- A unified approach for fault tolerance and dynamic power management in fixed-priority real-time embedded systems (2006) (96)
- Privacy-Preserving Detection of Sybil Attacks in Vehicular Ad Hoc Networks (2007) (96)
- Testing of droplet-based microelectrofluidic systems (2003) (95)
- Board-Level Functional Fault Diagnosis Using Artificial Neural Networks, Support-Vector Machines, and Weighted-Majority Voting (2013) (93)
- Design of system-on-a-chip test access architectures under place-and-route and power constraints (2000) (93)
- Coding theory framework for target location in distributed sensor networks (2001) (90)
- Parallel Scan-Like Test and Multiple-Defect Diagnosis for Digital Microfluidic Biochips (2007) (88)
- Adaptive Cooling of Integrated Circuits Using Digital Microfluidics (2007) (87)
- Efficient Wrapper/TAM co-optimization for large SOCs (2002) (86)
- Ensuring the operational health of droplet-based microelectrofluidic biosensor systems (2005) (86)
- Integrated control-path design and error recovery in the synthesis of digital microfluidic lab-on-chip (2010) (86)
- Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint (2009) (85)
- Design Automation and Test Solutions for Digital Microfluidic Biochips (2010) (85)
- Energy-conscious, deterministic I/O device scheduling in hard real-time systems (2003) (84)
- Test set embedding for deterministic BIST using a reconfigurable interconnection network (2004) (84)
- Test-Pattern Grading and Pattern Selection for Small-Delay Defects (2008) (83)
- Droplet-trace-based array partitioning and a pin assignment algorithm for the automated design of digital microfluidic biochips (2006) (83)
- Integrated Droplet Routing in the Synthesis of Microfluidic Biochips (2007) (82)
- Energy-aware target localization in wireless sensor networks (2003) (82)
- Design Tools for Digital Microfluidic Biochips: Toward Functional Diversification and More Than Moore (2010) (81)
- Scheduling of microfluidic operations for reconfigurabletwo-dimensional electrowetting arrays (2001) (81)
- Target localization based on energy considerations in distributed sensor networks (2003) (79)
- Test Planning and Test Resource Optimization for Droplet-Based Microfluidic Systems (2004) (79)
- Stuck-at Fault Tolerance in RRAM Computing Systems (2018) (78)
- Testing and Diagnosis of Realistic Defects in Digital Microfluidic Biochips (2007) (78)
- Test data compression for IP embedded cores using selective encoding of scan slices (2005) (78)
- Real-time task scheduling for energy-aware embedded systems (2001) (75)
- Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs (2002) (73)
- Low-power scan testing and test data compression forsystem-on-a-chip (2002) (73)
- A Reagent-Saving Mixing Algorithm for Preparing Multiple-Target Biochemical Samples Using Digital Microfluidics (2012) (72)
- Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis (2010) (71)
- Test-architecture optimization for TSV-based 3D stacked ICs (2010) (70)
- Design automation methods and tools for microfluidics-based biochips (2006) (69)
- Pruning-based, energy-optimal, deterministic I/O device scheduling for hard real-time systems (2005) (69)
- Built-in self testing of sequential circuits using precomputed test sets (1998) (69)
- Keynote Paper: From EDA to IoT eHealth: Promises, Challenges, and Solutions (2018) (67)
- Functional testing of digital microfluidic biochips (2007) (66)
- Dynamic adaptation for fault tolerance and power management in embedded real-time systems (2004) (66)
- Digital microfluidic biochips: Recent research and emerging challenges (2011) (66)
- Fault detection, real-time error recovery, and experimental demonstration for digital microfluidic biochips (2013) (66)
- Optimization methods for post-bond die-internal/external testing in 3D stacked ICs (2010) (66)
- Cooling of integrated circuits using droplet-based microfluidics (2003) (64)
- Integrated droplet routing and defect tolerance in the synthesis of digital microfluidic biochips (2008) (64)
- Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs (2011) (64)
- Multisensor Data Fusion in Distributed Sensor Networks Using Mobile Agents (2001) (63)
- Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling (2009) (63)
- Concurrent testing of droplet-based microfluidic systems for multiplexed biomedical assays (2004) (63)
- Test-Pattern Selection for Screening Small-Delay Defects in Very-Deep Submicrometer Integrated Circuits (2010) (63)
- TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test (2012) (62)
- A cyberphysical synthesis approach for error recovery in digital microfluidic biochips (2012) (62)
- Test scheduling for core-based systems (1999) (61)
- Digital Microfluidic Biochips - Design Automation and Optimization (2010) (61)
- Efficient test access mechanism optimization for system-on-chip (2003) (61)
- Waste-aware dilution and mixing of biochemical samples with digital microfluidic biochips (2011) (61)
- Automated design of pin-constrained digital microfluidic biochips under droplet-interference constraints (2007) (60)
- Design-Space Exploration and Optimization of an Energy-Efficient and Reliable 3-D Small-World Network-on-Chip (2016) (60)
- Fault recovery based on checkpointing for hard real-time embedded systems (2003) (60)
- Test response compaction using multiplexed parity trees (1996) (59)
- Testing of Flow-Based Microfluidic Biochips: Fault Modeling, Test Generation, and Experimental Demonstration (2014) (59)
- Fault Modeling and Functional Test Methods for Digital Microfluidic Biochips (2009) (58)
- Uncertainty-aware sensor deployment algorithms for surveillance applications (2003) (55)
- Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits (2006) (55)
- Design of fault-tolerant and dynamically-reconfigurable microfluidic biochips (2005) (55)
- IEEE Transactions on Biomedical Circuits and Systems (2018) (54)
- Defect-oriented testing and diagnosis of digital microfluidics-based biochips (2005) (53)
- Design automation for microfluidics-based biochips (2005) (53)
- High-level synthesis for micro-electrode-dot-array digital microfluidic biochips (2016) (52)
- SOC test planning using virtual test access architectures (2004) (52)
- A Cross-Referencing-Based Droplet Manipulation Method for High-Throughput and Pin-Constrained Digital Microfluidic Arrays (2007) (52)
- Deterministic Built-in Pattern Generation for Sequential Circuits (1999) (51)
- Test planning for modular testing of hierarchical SOCs (2005) (51)
- Zero-aliasing space compaction using linear compactors with bounded overhead (1998) (51)
- Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs (2009) (51)
- Accepted for Publication in Ieee Transactions on Computer-aided Design of Integrated Circuits and Systems Test Scheduling for Core-based Systems Using Mixed-integer Linear Programming (2000) (51)
- Test resource optimization for multi-site testing of SOCs under ATE memory depth constraints (2002) (50)
- Defect-Tolerant Design and Optimization of a Digital Microfluidic Biochip for Protein Crystallization (2010) (49)
- Optimal Zero-Aliasing Space Compaction of Test Responses (1998) (49)
- Rapid generation of thermal-safe test schedules (2005) (48)
- A Droplet-Manipulation Method for Achieving High-Throughput in Cross-Referencing-Based Digital Microfluidic Biochips (2008) (47)
- Reliability-oriented broadcast electrode-addressing for pin-constrained digital microfluidic biochips (2011) (47)
- Dynamic I/O power management for hard real-time systems (2001) (47)
- Concurrent testing of digital microfluidics-based biochips (2006) (47)
- Test data compression and decompression based on internal scanchains and Golomb coding (2002) (47)
- Energy-aware fault tolerance in fixed-priority real-time embedded systems (2003) (47)
- Interconnect-Aware and Layout-Oriented Test-Pattern Selection for Small-Delay Defects (2008) (46)
- Security Assessment of Cyberphysical Digital Microfluidic Biochips (2016) (46)
- Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns (2008) (46)
- Automated design of pin-constrained digital microfluidic arrays for lab-on-a-chip applications (2006) (46)
- Healthcare IoT (2020) (45)
- Machine Learning for Hardware Security: Opportunities and Risks (2018) (45)
- A general and exact routing methodology for Digital Microfluidic Biochips (2015) (45)
- Contactless Pre-Bond TSV Test and Diagnosis Using Ring Oscillators and Multiple Voltage Levels (2014) (44)
- Optimizing 3D NoC design for energy efficiency: A machine learning approach (2015) (44)
- Nine-coded compression technique with application to reduced pin-count testing and flexible on-chip decompression (2004) (43)
- Synchronization of washing operations with droplet routing for cross-contamination avoidance in digital microfluidic biochips (2010) (43)
- Board-Level Functional Fault Diagnosis Using Multikernel Support Vector Machines and Incremental Learning (2014) (43)
- Control-Layer Routing and Control-Pin Minimization for Flow-Based Microfluidic Biochips (2017) (43)
- Microelectrofluidic Systems: Modeling and Simulation (2002) (43)
- Biochip Synthesis and Dynamic Error Recovery for Sample Preparation Using Digital Microfluidics (2014) (42)
- Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling (2006) (42)
- Synthesis of Cyberphysical Digital-Microfluidic Biochips for Real-Time Quantitative Analysis (2017) (41)
- Real-Time Error Recovery in Cyberphysical Digital-Microfluidic Biochips Using a Compact Dictionary (2013) (41)
- Secure Randomized Checkpointing for Digital Microfluidic Biochips (2018) (41)
- Supply-Chain Security of Digital Microfluidic Biochips (2016) (41)
- Test Resource Partitioning for System-on-a-Chip (2002) (41)
- Layout-Aware Solution Preparation for Biochemical Analysis on a Digital Microfluidic Biochip (2011) (40)
- On effective and efficient in-field TSV repair for stacked 3D ICs (2013) (40)
- Exact routing for micro-electrode-dot-array digital microfluidic biochips (2017) (40)
- Scan-chain design and optimization for three-dimensional integrated circuits (2009) (39)
- A unified approach for SoC testing using test data compression and TAM optimization (2003) (39)
- Testing microfluidic Fully Programmable Valve Arrays (FPVAs) (2017) (39)
- Multicast-Based Testing and Thermal-Aware Test Scheduling for 3D ICs with a Stacked Network-on-Chip (2016) (39)
- Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding (2001) (38)
- Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip (2009) (38)
- Task feasibility analysis and dynamic voltage scaling in fault-tolerant real-time embedded systems (2004) (38)
- IEEE P1500-compliant test wrapper design for hierarchical cores (2004) (38)
- Design of pin-constrained general-purpose digital microfluidic biochips (2012) (37)
- A Digital-Microfluidic Approach to Chip Cooling (2008) (37)
- Representative critical-path selection for aging-induced delay monitoring (2013) (37)
- Experimental demonstration of error recovery in an integrated cyberphysical digital-microfluidic platform (2015) (37)
- On-Chip Sample Preparation for Multiple Targets Using Digital Microfluidics (2014) (37)
- Broadcast Electrode-Addressing and Scheduling Methods for Pin-Constrained Digital Microfluidic Biochips (2011) (37)
- Computation-oriented fault-tolerance schemes for RRAM computing systems (2017) (36)
- Droplet Size-Aware High-Level Synthesis for Micro-Electrode-Dot-Array Digital Microfluidic Biochips (2017) (36)
- Investigating the effect of voltage-switching on low-energy task scheduling in hard real-time systems (2001) (36)
- Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels (2013) (36)
- Test and Diagnosis for Small-Delay Defects (2011) (36)
- Using built-in self-test and adaptive recovery for defect tolerance in molecular electronics-based nanofabrics (2005) (36)
- Design of built-in test generator circuits using width compression (1998) (35)
- How effective are compression codes for reducing test data volume? (2002) (34)
- Board-level fault diagnosis using Bayesian inference (2010) (34)
- Test width compression for built-in self testing (1997) (34)
- Behavioral modeling and performance evaluation of microelectrofluidics-based PCR systems using SystemC (2004) (34)
- Test Resource Partitioning for SOCs (2001) (34)
- Microfluidic encryption of on-chip biochemical assays (2016) (34)
- Dictionary-based error recovery in cyberphysical digital-microfluidic biochips (2012) (33)
- Test Bus Sizing for System-on-a-Chip (2002) (33)
- Error recovery in a micro-electrode-dot-array digital microfluidic biochip (2016) (33)
- Error-Correcting Sample Preparation with Cyberphysical Digital Microfluidic Lab-on-Chip (2016) (33)
- Scalable infrastructure for distributed sensor networks (2005) (33)
- High Performance Sensor Integration in Distributed Sensor Networks Using Mobile Agents (2002) (32)
- Frequency-Directed Run-Length (FDR) Codes (2002) (32)
- On-Chip Sample Preparation with Multiple Dilutions Using Digital Microfluidics (2012) (32)
- Efficient space/time compression to reduce test data volume and testing time for IP cores (2005) (31)
- Test Data Compression Using Selective Encoding of Scan Slices (2008) (31)
- Efficient Error Recovery in Cyberphysical Digital-Microfluidic Biochips (2015) (31)
- Deviation-Based LFSR Reseeding for Test-Data Compression (2009) (31)
- Towards fault-tolerant digital microfluidic lab-on-chip: Defects, fault modeling, testing, and reconfiguration (2008) (30)
- On-chip biochemical sample preparation using digital microfluidics (2011) (30)
- COPLANAR DIGITAL MICROFLUIDICS USING STANDARD PRINTED CIRCUIT BOARD PROCESSES (2005) (30)
- Design and Optimization of a Cyberphysical Digital-Microfluidic Biochip for the Polymerase Chain Reaction (2015) (30)
- Design methodology for sample preparation on digital microfluidic biochips (2012) (30)
- Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands (2012) (30)
- Digital Microfluidic Logic Gates and Their Application to Built-in Self-Test of Lab-on-Chip (2010) (30)
- Automated, accurate, and inexpensive solution-preparation on a digital microfluidic biochip (2008) (30)
- Smart diagnosis: Efficient board-level diagnosis and repair using artificial neural networks (2011) (30)
- On Using Twisted-Ring Counters for Test Set Embedding in BIST (2001) (29)
- On the Covering of Vertices for Fault Diagnosis in Hypercubes (1999) (29)
- Fault-Tolerant Training Enabled by On-Line Fault Detection for RRAM-Based Neural Computing Systems (2019) (28)
- A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST (2008) (28)
- System-level hardware failure prediction using deep learning (2019) (28)
- Adaptive Board-Level Functional Fault Diagnosis Using Decision Trees (2012) (28)
- Test data compression using dictionaries with fixed-length indices [SOC testing] (2003) (28)
- Energy-aware deterministic fault tolerance in distributed real-time embedded systems (2004) (28)
- Control-layer optimization for flow-based mVLSI microfluidic biochips (2014) (28)
- Efficient test response compression for multiple-output circuits (1994) (28)
- Acoustic streaming vortices enable contactless, digital control of droplets (2020) (28)
- Acoustohydrodynamic tweezers via spatial arrangement of streaming vortices (2021) (27)
- Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip (2007) (27)
- Micro-Electrode-Dot-Array Digital Microfluidic Biochips: Technology, Design Automation, and Test Techniques (2019) (27)
- Aging- and Variation-Aware Delay Monitoring Using Representative Critical Path Selection (2015) (27)
- Identification of Defective TSVs in Pre-Bond Testing of 3D ICs (2011) (27)
- Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling (2008) (27)
- Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns (2008) (27)
- Design automation and testing of monolithic 3D ICs: Opportunities, challenges, and solutions: (Invited paper) (2017) (26)
- Failing vector identification based on overlapping intervals of test vectors in a scan-BIST environment (2003) (26)
- Optimal space compaction of test responses (1995) (26)
- RT-Level Deviation-Based Grading of Functional Test Sequences (2009) (26)
- Defect-Aware High-Level Synthesis and Module Placement for Microfluidic Biochips (2008) (26)
- Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint (2012) (25)
- Impact of Electrostatic Coupling and Wafer-Bonding Defects on Delay Testing of Monolithic 3D Integrated Circuits (2017) (25)
- Optimization of Test Pin-Count, Test Scheduling, and Test Access for NoC-Based Multicore SoCs (2014) (25)
- Crosstalk- and Process Variations-Aware High-Quality Tests for Small-Delay Defects (2013) (25)
- Test-Cost Modeling and Optimal Test-Flow Selection of 3-D-Stacked ICs (2015) (25)
- Defect tolerance for gracefully-degradable microfluidics-based biochips (2005) (25)
- Recent advances in test planning for modular testing of core-based SOCs (2002) (25)
- High-quality pattern selection for screening small-delay defects considering process variations and crosstalk (2010) (25)
- Reliability-Driven Pipelined Scan-Like Testing of Digital Microfluidic Biochips (2014) (25)
- Optimization Methods for Post-Bond Testing of 3D Stacked ICs (2012) (24)
- Built-in Self-Test and Fault Diagnosis for Lab-on-Chip Using Digital Microfluidic Logic Gates (2008) (24)
- Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization (2012) (24)
- Continuous-Flow Biochips: Technology, Physical-Design Methods, and Testing (2015) (24)
- Efficient Board-Level Functional Fault Diagnosis With Missing Syndromes (2016) (24)
- Testing of flow-based microfluidic biochips (2013) (23)
- Built-in self-test for micro-electrode-dot-array digital microfluidic biochips (2016) (23)
- An interval-based diagnosis scheme for identifying failing vectors in a scan-BIST environment (2002) (23)
- Design and optimization of multi-level TAM architectures for hierarchical SOCs (2003) (23)
- Fine-Grained Aging-Induced Delay Prediction Based on the Monitoring of Run-Time Stress (2018) (23)
- Efficient and Adaptive Error Recovery in a Micro-Electrode-Dot-Array Digital Microfluidic Biochip (2018) (23)
- Hardware/Software Co-Design and Optimization for Cyberphysical Integration in Digital Microfluidic Biochips (2014) (23)
- Run-time hardware trojan detection using performance counters (2017) (23)
- Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets (2003) (23)
- Diagnostic system based on support-vector machines for board-level functional diagnosis (2012) (23)
- Design and optimization of a digital microfluidic biochip for protein crystallization (2008) (23)
- Adaptive Hot-Spot Cooling of Integrated Circuits Using Digital Microfluidics (2005) (23)
- Space compaction of test responses for IP cores using orthogonal transmission functions (2000) (23)
- Yield enhancement of reconfigurable microfluidics-based biochips using interstitial redundancy (2006) (23)
- Redundancy modelling and array yield analysis for repairable embedded memories (2005) (22)
- Locking of biochemical assays for digital microfluidic biochips (2018) (22)
- Layout-Aware Mixture Preparation of Biochemical Fluids on Application-Specific Digital Microfluidic Biochips (2015) (22)
- Space compression revisited (1999) (22)
- Advances in Design Automation Techniques for Digital-Microfluidic Biochips (2015) (22)
- Design, testing, and applications of digital microfluidics-based biochips (2005) (22)
- Circuit Topology-Based Test Pattern Generation for Small-Delay Defects (2010) (22)
- Defect aware X-filling for low-power scan testing (2010) (22)
- A general testing method for digital microfluidic biochips under physical constraints (2015) (22)
- A novel hybrid method for SDD pattern grading and selection (2010) (22)
- An Efficient Test Pattern Selection Method for Improving Defect Coverage with Reduced Test Data Volume and Test Application Time (2006) (22)
- Test generation and design-for-testability for flow-based mVLSI microfluidic biochips (2014) (22)
- Pruning-based energy-optimal device scheduling for hard real-time systems (2002) (22)
- Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches (2014) (21)
- Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs (2013) (21)
- Simultaneous Optimization of Droplet Routing and Control-Pin Mapping to Electrodes in Digital Microfluidic Biochips (2012) (21)
- Fault tolerance in neuromorphic computing systems (2019) (21)
- Adaptive error recovery in MEDA biochips based on droplet-aliquot operations and predictive analysis (2017) (21)
- MVP: Capture-power reduction with minimum-violations partitioning for delay testing (2010) (21)
- Ping-pong test: Compact test vector generation for reversible circuits (2012) (21)
- Datacollection in Event-Driven Wireless Sensor Networks with Mobile Sinks (2010) (21)
- Depletion layer resistance and its effect on I-V characteristics of fully- and partially-illuminated silicon solar cells (1996) (21)
- Compact dictionaries for fault diagnosis in scan-BIST (2004) (21)
- Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip (2018) (21)
- Design of cyberphysical digital microfluidic biochips under completion-time uncertainties in fluidic operations (2013) (20)
- Monolithic 3D-Enabled High Performance and Energy Efficient Network-on-Chip (2017) (20)
- Test-time optimization in NOC-based manycore SOCs using multicast routing (2014) (20)
- Test compaction for small-delay defects using an effective path selection scheme (2013) (20)
- Contactless pre-bond TSV fault diagnosis using duty-cycle detectors and ring oscillators (2015) (20)
- Hybrid BIST Based on Repeating Sequences and Cluster Analysis (2005) (20)
- Accurate anomaly detection using correlation-based time-series analysis in a core router system (2016) (20)
- Test response compaction for built-in self testing (1996) (20)
- Test infrastructure design for mixed-signal SOCs with wrapped analog cores (2006) (20)
- Scan Test of Die Logic in 3-D ICs Using TSV Probing (2015) (19)
- Efficient mixture preparation on digital microfluidic biochips (2013) (19)
- Test-cost optimization and test-flow selection for 3D-stacked ICs (2013) (19)
- Droplet Size-Aware and Error-Correcting Sample Preparation Using Micro-Electrode-Dot-Array Digital Microfluidic Biochips (2017) (19)
- Adaptive and Roll-Forward Error Recovery in MEDA Biochips Based on Droplet-Aliquot Operations and Predictive Analysis (2018) (19)
- Design and Testing of Digital Microfluidic Biochips (2012) (19)
- CoSyn: Efficient single-cell analysis using a hybrid microfluidic platform (2017) (19)
- Parallel Scan-Like Testing and Fault Diagnosis Techniques for Digital Microfluidic Biochips (2007) (19)
- Synthesis of Error-Recovery Protocols for Micro-Electrode-Dot-Array Digital Microfluidic Biochips (2017) (19)
- Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits (2014) (19)
- Security implications of cyberphysical digital microfluidic biochips (2015) (19)
- Wash Optimization and Analysis for Cross-Contamination Removal Under Physical Constraints in Flow-Based Microfluidic Biochips (2016) (19)
- Structural and Functional Test Methods for Micro-Electrode-Dot-Array Digital Microfluidic Biochips (2018) (18)
- On Using Exponential-Golomb Codes and Subexponential Codes for System-on-a-Chip Test Data Compression (2004) (18)
- Test cost reduction for SOCs using TAMs and Lagrange multipliers (2003) (18)
- Theory and analysis of generalized mixing and dilution of biochemical fluids using digital microfluidic biochips (2014) (18)
- Optimization of polymerase chain reaction on a cyberphysical digital microfluidic biochip (2013) (18)
- Security Implications of Cyberphysical Flow-Based Microfluidic Biochips (2017) (18)
- Built-In Self-Test and Test Scheduling for Interposer-Based 2.5D IC (2015) (18)
- Optimization of 3D Digital Microfluidic Biochips for the Multiplexed Polymerase Chain Reaction (2016) (18)
- At-speed interconnect testing and test-path optimization for 2.5D ICs (2014) (18)
- Yield enhancement of digital microfluidics-based biochips using space redundancy and local reconfiguration (2005) (18)
- Thermal effects on droplet transport in digital microfluidics with applications to chip cooling (2004) (18)
- Contactless, programmable acoustofluidic manipulation of objects on water. (2019) (18)
- Diverse Routing: Exploiting Social Behavior for Routing in Delay-Tolerant Networks (2009) (18)
- Massive signal tracing using on-chip DRAM for in-system silicon debug (2014) (18)
- Test and Design-for-Testability Solutions for 3D Integrated Circuits (2014) (18)
- On-chip voltage-droop prediction using support-vector machines (2014) (18)
- Design-for-Testability for Digital Microfluidic Biochips (2009) (18)
- Fine-grained aging prediction based on the monitoring of run-time stress using DfT infrastructure (2015) (18)
- Soft error-aware design optimization of low power and time-constrained embedded systems (2010) (17)
- Built-in self testing of high-performance circuits using twisted-ring counters (2000) (17)
- Error recovery in digital microfluidics for personalized medicine (2015) (17)
- Zero-aliasing space compaction of test responses using multiple parity signatures (1998) (17)
- Network flow techniques for dynamic voltage scaling in hard real-time systems (2004) (17)
- Analysis of the Impact of Process Variations and Manufacturing Defects on the Performance of Carbon-Nanotube FETs (2020) (17)
- Co-optimization of droplet routing and pin assignment in disposable digital microfluidic biochips (2011) (17)
- Synthesis of single-output space compactors for scan-based sequential circuits (2002) (17)
- Efficient modular testing of SoCs using dual-speed TAM architectures (2004) (17)
- Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands (2011) (16)
- On Producing Linear Dilution Gradient of a Sample with a Digital Microfluidic Biochip (2013) (16)
- A Seed-Selection Method to Increase Defect Coverage for LFSR-Reseeding-Based Test Compression (2007) (16)
- Experiences in implementing an energy-driven task scheduler in RT-Linux (2002) (16)
- Digital-Microfluidic Biochips (2006) (16)
- A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction (2008) (16)
- Toward Secure and Trustworthy Cyberphysical Microfluidic Biochips (2019) (16)
- Test Planning in Digital Microfluidic Biochips Using Efficient Eulerization Techniques (2011) (16)
- Modeling Silicon-Photonic Neural Networks under Uncertainties (2020) (16)
- Editorial on the Opening of the New Editorial Year - The State of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2018) (16)
- Defect-Oriented LFSR Reseeding to Target Unmodeled Defects Using Stuck-at Test Sets (2011) (16)
- Test pin count reduction for NoC-based Test delivery in multicore SOCs (2012) (16)
- An online thermal-constrained task scheduler for 3D multi-core processors (2015) (16)
- A programmable method for low-power scan shift in SoC integrated circuits (2016) (15)
- Test resource partitioning and reduced pin-count testing based on test data compression (2002) (15)
- Correctness Checking of Bio-chemical Protocol Realizations on a Digital Microfluidic Biochip (2014) (15)
- Pre-Bond Probing of Through-Silicon Vias in 3-D Stacked ICs (2013) (15)
- Analysis of electrostatic coupling in monolithic 3D integrated circuits and its impact on delay testing (2016) (15)
- A dynamic programming solution for optimizing test delivery in multicore SOCs (2012) (15)
- Timing-Driven Flow-Channel Network Construction for Continuous-Flow Microfluidic Biochips (2020) (15)
- Scan-Based Testing of Post-Bond Silicon Interposer Interconnects in 2.5-D ICs (2014) (15)
- High temperature crystallized poly-Si on Mo substrates for TFT application (2003) (15)
- Synthesis of transparent circuits for hierarchical and system-on-a-chip test (2001) (15)
- Sample Preparation on Micro-Electrode-Dot-Array Digital Microfluidic Biochips (2017) (15)
- On residue removal in digital microfluidic biochips (2011) (15)
- Reconfiguration Techniques for Digital Microfluidic Biochips (2005) (15)
- Hierarchy-Aware and Area-Efficient Test Infrastructure Design for Core-Based System Chips (2006) (15)
- Integrated hierarchical design of microelectrofluidic systems using SystemC (2002) (14)
- Test-set embedding based on width compression for mixed-mode BIST (2000) (14)
- Bio-Protocol Watermarking on Digital Microfluidic Biochips (2019) (14)
- Defect Tolerance Based on Graceful Degradation and Dynamic Reconfiguration for Digital Microfluidics-Based Biochips (2006) (14)
- Testing of Digital Microfluidic Biochips Using Improved Eulerization Techniques and the Chinese Postman Problem (2010) (14)
- On-Chip Droop-Induced Circuit Delay Prediction Based on Support-Vector Machines (2016) (14)
- A Robust and Reconfigurable Multi-mode Power Gating Architecture (2011) (14)
- Generation of compact test sets with high defect coverage (2009) (14)
- Changepoint-based anomaly detection in a core router system (2017) (14)
- Fault Diagnosis for Leakage and Blockage Defects in Flow-Based Microfluidic Biochips (2016) (14)
- An Efficient Finite-State Machine Implementation of Huffman Decoders (1997) (14)
- Cumulative balance testing of logic circuits (1995) (14)
- TSV Stress-Aware ATPG for 3D Stacked ICs (2012) (14)
- Adaptive Droplet Routing in Digital Microfluidic Biochips Using Deep Reinforcement Learning (2020) (14)
- Pin-count-aware online testing of digital microfluidic biochips (2010) (14)
- Energy-efficient and reliable 3D Network-on-Chip (NoC): Architectures and optimization algorithms (2016) (14)
- Huffman encoding of test sets for sequential circuits (1998) (14)
- Board-Level Functional Fault Diagnosis Using Learning Based on Incremental Support-Vector Machines (2012) (14)
- Testing and Design-for-Testability Techniques for 3D Integrated Circuits (2011) (14)
- Cross-Contamination Avoidance for Droplet Routing (2013) (14)
- High-throughput dilution engine for sample preparation on digital microfluidic biochips (2014) (14)
- RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage (2010) (14)
- Real-Time Production Scheduler for Digital-Print-Service Providers Based on a Dynamic Incremental Evolutionary Algorithm (2015) (14)
- Thermal-aware test scheduling for NOC-based 3D integrated circuits (2013) (14)
- Physical defect modeling for fault insertion in system reliability test (2009) (14)
- Execution of provably secure assays on MEDA biochips to thwart attacks (2019) (13)
- Deterministic BIST based on a reconfigurable interconnection network (2003) (13)
- Fault Tolerance for RRAM-Based Matrix Operations (2018) (13)
- Knowledge discovery and knowledge transfer in board-level functional fault diagnosis (2014) (13)
- Security Assessment of Micro-Electrode-Dot-Array Biochips (2019) (13)
- Test Set Enrichment using a Probabilistic Fault Model and the Theory of Output Deviations (2006) (13)
- Post-bond Testing of the Silicon Interposer and Micro-bumps in 2.5D ICs (2013) (13)
- A Design-for-Test Solution Based on Dedicated Test Layers and Test Scheduling for Monolithic 3-D Integrated Circuits (2019) (13)
- TAM optimization for mixed-signal SOCs using analog test wrappers (2003) (13)
- Scan test of die logic in 3D ICs using TSV probing (2012) (13)
- Automated design of digital microfluidic lab-on-chip under pin-count constraints (2008) (13)
- Three-stage compression approach to reduce test data volume and testing time for IP cores in SOCs (2005) (13)
- Diagnosis of Board-Level Functional Failures Under Uncertainty Using Dempster–Shafer Theory (2012) (13)
- Optimization of Multi-Target Sample Preparation On-Demand With Digital Microfluidic Biochips (2019) (13)
- Test-Pattern Ordering for Wafer-Level Test-During-Burn-In (2008) (13)
- On-Line Testing of Lab-on-Chip Using Reconfigurable Digital-Microfluidic Compactors (2009) (13)
- Design of parameterizable error-propagating space compactors for response observation (2001) (13)
- Detection, Diagnosis, and Recovery From Clock-Domain Crossing Failures in Multiclock SoCs (2013) (13)
- Time-Division Multiplexing for Testing DVFS-Based SoCs (2015) (13)
- Cyber–Physical Digital-Microfluidic Biochips: Bridging the Gap Between Microfluidics and Microbiology (2018) (13)
- Acoustoelectronic nanotweezers enable dynamic and large-scale control of nanomaterials (2021) (13)
- Design Automation Challenges for Microfluidics-Based Biochips* (2005) (13)
- Test-Delivery Optimization in Manycore SOCs (2014) (12)
- Adaptive Board-Level Functional Fault Diagnosis Using Incremental Decision Trees (2016) (12)
- Microfluidic very large-scale integration for biochips: Technology, testing and fault-tolerant design (2015) (12)
- SoC Testing Using LFSR Reseeding, and Scan-Slice- Based TAM Optimization and Test Scheduling (2007) (12)
- Distributed sensor networks for real-time systems with adaptive configuration (2001) (12)
- Re-using BIST for circuit aging monitoring (2015) (12)
- Waste-aware single-target dilution of a biochemical fluid using digital microfluidic biochips (2015) (12)
- Multi-Tenant FPGA-based Reconfigurable Systems: Attacks and Defenses (2019) (12)
- Low-Cost Dilution Engine for Sample Preparation in Digital Microfluidic Biochips (2012) (12)
- Demand-driven mixture preparation and droplet streaming using digital microfluidic biochips (2014) (12)
- Wash optimization for cross-contamination removal in flow-based microfluidic biochips (2014) (12)
- Redundancy Analysis and a Distributed Self-Organization Protocol for Fault-Tolerant Wireless Sensor Networks∗ (2007) (12)
- Low-cost modular testing and test resource partitioning for SOCs (2005) (12)
- Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs (2009) (12)
- Accelerated Functional Testing of Digital Microfluidic Biochips (2008) (11)
- On combining pinpoint test set relaxation and run-length codes for reducing test data volume (2003) (11)
- Seed selection in LFSR-reseeding-based test compression for the detection of small-delay defects (2009) (11)
- Delay Test for Diagnosis of Power Switches (2014) (11)
- Test-cost optimization in a scan-compression architecture using support-vector regression (2017) (11)
- Information-theoretic syndrome and root-cause analysis for guiding board-level fault diagnosis (2013) (11)
- AccuReD: High Accuracy Training of CNNs on ReRAM/GPU Heterogeneous 3-D Architecture (2020) (11)
- Power-Aware Test Data Compression for Embedded IP Cores (2006) (11)
- Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process Variation (2011) (11)
- Design of fault-tolerant neuromorphic computing systems (2018) (11)
- PREEMPT: PReempting Malware by Examining Embedded Processor Traces (2019) (11)
- Pre-bond testing of the silicon interposer in 2.5D ICs (2016) (11)
- Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains (2007) (11)
- Physical-Defect Modeling and Optimization for Fault-Insertion Test (2012) (11)
- Integrated and real-time quantitative analysis using cyberphysical digital-microfluidic biochips (2016) (11)
- Exploring the Mysteries of System-Level Test (2020) (11)
- Multi-Objective Optimization of ReRAM Crossbars for Robust DNN Inferencing under Stochastic Noise (2021) (11)
- Time-division multiplexing for testing SoCs with DVS and multiple voltage islands (2012) (11)
- Accelerated Functional Testing of Digital Microfluidic Biochips (2008) (11)
- Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression (2017) (11)
- Multitarget Sample Preparation Using MEDA Biochips (2020) (11)
- Synthesis of a Cyberphysical Hybrid Microfluidic Platform for Single-Cell Analysis (2019) (11)
- Digital microfluidic biochip design for protein crystallization (2007) (11)
- A synthesis-for-transparency approach for hierarchical and system-on-a-chip test (2003) (11)
- Built-in self-test of molecular electronics-based nanofabrics (2005) (11)
- Balanced Boolean functions (1998) (11)
- A real-time digital-microfluidic platform for epigenetics (2016) (11)
- Hardware Trojan Detection Using Changepoint-Based Anomaly Detection Techniques (2019) (11)
- Interconnect Testing and Test-Path Scheduling for Interposer-Based 2.5-D ICs (2015) (10)
- Analysis of Process Variations, Defects, and Design-Induced Coupling in Memristors (2018) (10)
- Testing for SoCs with advanced static and dynamic power-management capabilities (2013) (10)
- Computer-Aided Design of Microfluidic Very Large Scale Integration (mVLSI) Biochips (2017) (10)
- Efficient Generation of Dilution Gradients With Digital Microfluidic Biochips (2019) (10)
- C-Testing and Efficient Fault Localization for AI Accelerators (2022) (10)
- Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs (2007) (10)
- Testing of Clock-Domain Crossing Faults in Multi-core System-on-Chip (2011) (10)
- A unified test and fault-tolerant multicast solution for network-on-chip designs (2016) (10)
- Desieve the Attacker: Thwarting IP Theft in Sieve-Valve-based Biochips (2019) (10)
- Security Trade-Offs in Microfluidic Routing Fabrics (2017) (10)
- Optimization of the IEEE 1687 access network for hybrid access schedules (2016) (10)
- Counter-Based Output Selection for Test Response Compaction (2013) (10)
- Fault Diagnosis in Lab-on-Chip Using Digital Microfluidic Logic Gates (2011) (10)
- A partition-based approach for identifying failing scan cells in scan-BIST with applications to system-on-chip fault diagnosis (2003) (10)
- Fault diagnosis for flow-based microfluidic biochips (2015) (10)
- Multi-site test optimization for multi-Vdd SoCs using space- and time- division multiplexing (2014) (10)
- Board-Level Functional Fault Identification using Streaming Data (2019) (10)
- Reliability and performance trade-offs for 3D NoC-enabled multicore chips (2016) (10)
- Design-for-Testability for Continuous-Flow Microfluidic Biochips (2018) (10)
- Test planning for mixed-signal SOCs with wrapped analog cores (2005) (10)
- Power Management Using Test-Pattern Ordering for Wafer-Level Test During Burn-In (2009) (10)
- Functional Criticality Classification of Structural Faults in AI Accelerators (2020) (10)
- Toward Secure Microfluidic Fully Programmable Valve Array Biochips (2019) (10)
- CAD-Base (2019) (10)
- Fault-Tolerant Unicast-Based Multicast for Reliable Network-on-Chip Testing (2018) (10)
- Changepoint-Based Anomaly Detection for Prognostic Diagnosis in a Core Router System (2019) (10)
- Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints (2009) (10)
- Defect-Aware Synthesis of Droplet-Based Microfluidic Biochips (2007) (10)
- A design-for-test solution for monolithic 3D integrated circuits (2016) (10)
- Computer-aided Design Techniques for Flow-based Microfluidic Lab-on-a-chip Systems (2021) (10)
- Optimization Techniques for the Synchronization of Concurrent Fluidic Operations in Pin-Constrained Digital Microfluidic Biochips (2012) (10)
- Tamper-Resistant Pin-Constrained Digital Microfluidic Biochips (2018) (10)
- Data compression in space under generalized mergeability based on concepts of cover table and frequency ordering (2000) (10)
- Broadcast-based minimization of the overall access time for the IEEE 1687 network (2018) (10)
- Defect Clustering-Aware Spare-TSV Allocation in 3-D ICs for Yield Enhancement (2019) (9)
- Identification of error-capturing scan cells in scan-BIST with applications to system-on-chip (2004) (9)
- Efficient LFSR Reseeding Based on Internal-Response Feedback (2014) (9)
- Test generation for clock-domain crossing faults in integrated circuits (2012) (9)
- Built-in Self-test and Defect Tolerance in Molecular Electronics-based Nanofabrics (2007) (9)
- Design and analysis of compact dictionaries for diagnosis in scan-BIST (2005) (9)
- Biochemistry Synthesis on a Cyberphysical Digital Microfluidics Platform Under Completion-Time Uncertainties in Fluidic Operations (2014) (9)
- DROPLET-BASED HOT SPOT COOLING USING TOPLESS DIGITAL MICROFLUIDICS ON A PRINTED CIRCUIT BOARD (2005) (9)
- Synchronization of Concurrently-Implemented Fluidic Operations in Pin-Constrained Digital Microfluidic Biochips (2010) (9)
- Detecting Sybil Attacks in Vehicular Ad Hoc Networks (2012) (9)
- Securing digital microfluidic biochips by randomizing checkpoints (2016) (9)
- Improving thermal-safe test scheduling for core-based systems-on-chip using shift frequency scaling (2005) (9)
- On-Line Error Detection in Digital Microfluidic Biochips (2012) (9)
- Integrated Control-Path Design and Error Recovery (2013) (9)
- Sample preparation for multiple-reactant bioassays on micro-electrode-dot-array biochips (2019) (9)
- RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences (2009) (9)
- Generalized network flow techniques for dynamic voltage scaling in hard real-time systems (2003) (9)
- On the quality of accumulator-based compaction of test responses (1997) (9)
- Programmable Daisychaining of Microelectrodes to Secure Bioassay IP in MEDA Biochips (2020) (9)
- Sensor-Array Optimization Based on Time-Series Data Analytics for Sanitation-Related Malodor Detection (2020) (9)
- Adaptation of Biochemical Protocols to Handle Technology-Change for Digital Microfluidics (2017) (9)
- ReGraphX: NoC-enabled 3D Heterogeneous ReRAM Architecture for Training Graph Neural Networks (2021) (9)
- A cocktail approach on random access scan toward low power and high efficiency test (2005) (9)
- Machine Learning-based Prediction of Test Power (2019) (9)
- Securing IJTAG against data-integrity attacks (2018) (9)
- Test-wrapper optimisation for embedded cores in through-silicon via-based three-dimensional system on chips (2011) (9)
- Signature Analysis for Testing, Diagnosis, and Repair of Multi-mode Power Switches (2011) (9)
- Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits (2013) (9)
- Randomized Checkpoints: A Practical Defense for Cyber-Physical Microfluidic Systems (2019) (9)
- Congestion-aware layout design for high-throughput digital microfluidic biochips (2012) (8)
- GRAMARCH: A GPU-ReRAM based Heterogeneous Architecture for Neural Image Segmentation (2020) (8)
- Gate-Sizing-Based Single $V_{\rm dd}$ Test for Bridge Defects in Multivoltage Designs (2010) (8)
- Optimizing Coherent Integrated Photonic Neural Networks under Random Uncertainties (2021) (8)
- Offline Error Detection in MEDA-Based Digital Microfluidic Biochips Using Oscillation-Based Testing Methodology (2017) (8)
- Testing of Low-cost Digital Microfluidic Biochips with Non-Regular Array Layouts (2010) (8)
- Impact of wafer-bonding defects on Monolithic 3D integrated circuits (2016) (8)
- Droplet Size-Aware High-Level Synthesis (2018) (8)
- Toward Hardware-Based IP Vulnerability Detection and Post-Deployment Patching in Systems-on-Chip (2021) (8)
- Toward Predictive Fault Tolerance in a Core-Router System: Anomaly Detection Using Correlation-Based Time-Series Analysis (2018) (8)
- How Useful are the ITC 02 SoC Test Benchmarks? (2002) (8)
- Reproduction and Detection of Board-Level Functional Failure (2012) (8)
- Fine-Grained Adaptive Testing Based on Quality Prediction (2018) (8)
- Compact dictionaries for fault diagnosis in BIST (2003) (8)
- Efficient observation-point insertion for diagnosability enhancement in digital circuits (2015) (8)
- Robust TSV-based 3D NoC design to counteract electromigration and crosstalk noise (2017) (8)
- Multi-frequency wrapper design and optimization for embedded cores under average power constraints (2005) (8)
- Power Management for Wafer-Level Test During Burn-In (2008) (8)
- Testing Methodology (2018) (8)
- Fault Modeling and Efficient Testing of Memristor-Based Memory (2021) (8)
- Shadow Attacks on MEDA Biochips (2018) (8)
- Face-to-face bus design with built-in self-test in 3D ICs (2013) (8)
- An Energy-Efficient Data Delivery Scheme for Delay-Sensitive Traffic in Wireless Sensor Networks (2010) (8)
- Balance testing and balance-testable design of logic circuits (1996) (8)
- A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs (2016) (7)
- Exact Synthesis of Biomolecular Protocols for Multiple Sample Pathways on Digital Microfluidic Biochips (2018) (7)
- Failure Prediction Based on Anomaly Detection for Complex Core Routers (2018) (7)
- Demand-Driven Single- and Multitarget Mixture Preparation Using Digital Microfluidic Biochips (2018) (7)
- Generation of Compact Stuck-At Test Sets Targeting Unmodeled Defects (2011) (7)
- Design of reconfigurable composite microsystems based on hardware/software codesign principles (2002) (7)
- Power-aware SoC test planning for effective utilization of port-scalable testers (2008) (7)
- REGENT: A Heterogeneous ReRAM/GPU-based Architecture Enabled by NoC for Training CNNs (2019) (7)
- A BIST scheme for testing and repair of multi-mode power switches (2011) (7)
- SOC (System-on-a-Chip) Testing for Plug and Play Test Automation (2011) (7)
- Online Soft-Error Vulnerability Estimation for Memory Arrays and Logic Cores (2018) (7)
- Pin-Constrained Designs of Digital Microfluidic Biochips for High-Throughput Bioassays (2010) (7)
- Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC (2012) (7)
- Board-level fault diagnosis using an error-flow dictionary (2010) (7)
- Algorithms for Sample Preparation with Microfluidic Lab-on-Chip (2019) (7)
- Thermal-aware TSV repair for electromigration in 3D ICs (2016) (7)
- A deterministic scan-BIST architecture with application to field testing of high-availability systems (2001) (7)
- C-Testing of AI Accelerators * (2020) (7)
- A Noise-Aware Hybrid Method for SDD Pattern Grading and Selection (2010) (7)
- Functional Test-Sequence Grading at Register-Transfer Level (2012) (7)
- Impact of Electrostatic Coupling on Monolithic 3D-enabled Network on Chip (2019) (7)
- Routing-aware resource allocation for mixture preparation in digital microfluidic biochips (2013) (7)
- Sortex: Efficient timing-driven synthesis of reconfigurable flow-based biochips for scalable single-cell screening (2017) (7)
- LSTM-based Analysis of Temporally- and Spatially-Correlated Signatures for Intermittent Fault Detection (2020) (7)
- Mimicking of Functional State Space with Structural Tests for the Diagnosis of Board-Level Functional Failures (2010) (7)
- Predicting ${X}$ -Sensitivity of Circuit-Inputs on Test-Coverage: A Machine-Learning Approach (2019) (7)
- Heterogeneous Systems on Chip and Systems in Package (2007) (7)
- Modular Testing and Built-In Self-Test of Embedded Cores in System-on-Chip Integrated Circuits (2005) (6)
- Synthesis of single-output space compactors with application to scan-based IP cores (2001) (6)
- INVITED: RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs (2019) (6)
- Wafer-Level Modular Testing of Core-Based SoCs (2007) (6)
- Generation of Effective 1-Detect TDF Patterns for Detecting Small-Delay Defects (2013) (6)
- Ranking of Suspect Faulty Blocks Using Dataflow Analysis and Dempster-Shafer Theory for the Diagnosis of Board-Level Functional Failures (2011) (6)
- On-Line Testing of Lab-on-Chip Using Digital Microfluidic Compactors (2008) (6)
- A Resilient and Hierarchical IoT-Based Solution for Stress Monitoring in Everyday Settings (2021) (6)
- Reliable Power Delivery and Analysis of Power-Supply Noise During Testing in Monolithic 3D ICs (2019) (6)
- Optimization of heaters in a digital microfluidic biochip for the polymerase chain reaction (2014) (6)
- Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICs (2019) (6)
- BioCyBig: A Cyberphysical System for Integrative Microfluidics-Driven Analysis of Genomic Association Studies (2020) (6)
- Security Assessment of Microfluidic Fully-Programmable-Valve-Array Biochips (2019) (6)
- 3D IC test scheduling using simulated annealing (2012) (6)
- Perspectives on Emerging Computation-in-Memory Paradigms (2021) (6)
- Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs (2005) (6)
- Fault-tolerant valve-based microfluidic routing fabric for droplet barcoding in single-cell analysis (2018) (6)
- Defect clustering-aware spare-TSV allocation for 3D ICs (2015) (6)
- Robust sample preparation on digital microfluidic biochips (2019) (6)
- Fault Isolation and Diagnosis in Multiprocessor Systems with Point-to-Point Communication Links (1998) (6)
- Information-Theoretic Syndrome Evaluation, Statistical Root-Cause Analysis, and Correlation-Based Feature Selection for Guiding Board-Level Fault Diagnosis (2015) (6)
- Performance analysis of microelectrofluidic systems using hierarchical modeling and simulation (2001) (6)
- Connecting fabrication defects to fault models and SPICE simulations for DNA self-assembled nanoelectronics (2009) (6)
- Digital print workflow optimization under due-dates, opportunity cost and resource constraints (2011) (6)
- Reuse-Based Optimization for Prebond and Post-Bond Testing of 3-D-Stacked ICs (2015) (6)
- Built-In Self-Test, Diagnosis, and Repair of MultiMode Power Switches (2014) (6)
- Test pattern generation for width compression in BIST (1999) (5)
- Software-Based Self-Testing Using Bounded Model Checking for Out-of-Order Superscalar Processors (2020) (5)
- A Signature Analysis Technique for the Identification of Failing Vectors with Application to Scan-BIST* (2004) (5)
- Output-bit selection with X-avoidance using multiple counters for test-response compaction (2014) (5)
- Adaptation and Evaluation of the Output-Deviations Metric to Target Small-Delay Defects in Industrial Circuits (2010) (5)
- Self-learning and adaptive board-level functional fault diagnosis (2015) (5)
- On-Chip Dilution from Multiple Concentrations of a Sample Fluid Using Digital Microfluidics (2013) (5)
- Bio-chemical Assay Locking to Thwart Bio-IP Theft (2019) (5)
- Fault-Tolerant Self-organization in Sensor Networks (2005) (5)
- Microfluidic Trojan Design in Flow-based Biochips (2020) (5)
- Automated path planning for washing in digital microfluidic biochips (2012) (5)
- Algorithms for Producing Linear Dilution Gradient with Digital Microfluidics (2013) (5)
- Handling Missing Syndromes in Board-Level Functional-Fault Diagnosis (2013) (5)
- A Model and Algorithm for Computing Minimum-Size Test Patterns (1998) (5)
- Synthesis of Tamper-Resistant Pin-Constrained Digital Microfluidic Biochips (2020) (5)
- Abetting Planned Obsolescence by Aging 3D Networks-on-Chip (2018) (5)
- Test Resource Partitioning (2002) (5)
- Uncertainty-aware robust optimization of test-access architectures for 3D stacked ICs (2013) (5)
- Test-wrapper designs for the detection of signal-integrity faults on core-external interconnects of SoCs (2007) (5)
- Knowledge Transfer in Board-Level Functional Fault Identification using Domain Adaptation (2019) (5)
- Digital-microfluidic biochips for quantitative analysis: Bridging the Gap between microfluidics and microbiology (2017) (5)
- Space compaction of test responses using orthogonal transmission functions [logic testing] (2003) (5)
- Wafer-Level Defect Screening for “Big-D/Small-A” Mixed-Signal SoCs (2009) (5)
- Security Assessment of Cyberphysical Digital Microfluidic Biochips. (2016) (5)
- SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects (2009) (5)
- Built-In Self-Diagnosis and Fault-Tolerant Daisy-Chain Design in MEDA Biochips* (2018) (5)
- Data-Driven Resiliency Solutions for Boards and Systems (2018) (5)
- Black-Box Test-Coverage Analysis and Test-Cost Reduction Based on a Bayesian Network Model (2019) (5)
- Adaptive Checkpointing with Dynamic Voltage Scaling in Embedded Real-Time Systems (2003) (5)
- Efficient and Adaptive Error Recovery (2018) (5)
- Efficient Fault-Criticality Analysis for AI Accelerators using a Neural Twin∗ (2021) (5)
- On Designing All-Optical Multipliers Using Mach-Zender Interferometers (2018) (5)
- Robust optimization of test-architecture designs for core-based SoCs (2013) (5)
- Jump test for metallic CNTs in CNFET-based SRAM (2015) (5)
- Synthesis of Reconfigurable Flow-Based Biochips for Scalable Single-Cell Screening (2019) (5)
- ExTest scheduling for 2.5D system-on-chip integrated circuits (2015) (5)
- AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs (2007) (5)
- Symbol-based health-status analysis in a core router system (2017) (5)
- MVP: Minimum-Violations Partitioning for Reducing Capture Power in At-Speed Delay-Fault Testing (2011) (5)
- A Distributed, Reconfigurable, and Reusable BIST Infrastructure for Test and Diagnosis of 3-D-Stacked ICs (2016) (5)
- Digital microfluidic biochips: Functional diversity, More than Moore, and cyberphysical systems (2011) (5)
- Prebond Testing and Test-Path Design for the Silicon Interposer in 2.5-D ICs (2017) (5)
- Reliability-Oriented IEEE Std. 1687 Network Design and Block-Aware High-Level Synthesis for MEDA Biochips* (2020) (5)
- Software-based online self-testing of network-on-chip using bounded model checking (2017) (5)
- Test-access-mechanism optimization for multi-Vdd SoCs (2015) (5)
- Advances in Design and Test of Monolithic 3-D ICs (2020) (5)
- System-level design automation tools for digital microfluidic biochips (2005) (5)
- Distributed sensor networksFa review of recent research (2001) (5)
- Learning to Mitigate Rowhammer Attacks (2022) (5)
- Hardware Fault Tolerance for Binary RRAM Crossbars (2019) (5)
- Aliasing-free error detection (ALFRED) (1993) (5)
- - Designing Energy-Aware Sensor Systems (2012) (5)
- Extending the Lifetime of MEDA Biochips by Selective Sensing on Microelectrodes (2020) (5)
- Robust Optimization of Test-Access Architectures Under Realistic Scenarios (2015) (5)
- SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects (2007) (5)
- Information-Theoretic Framework for Evaluating and Guiding Board-Level Functional-Fault Diagnosis (2014) (5)
- Algorithmic Fault Detection for RRAM-based Matrix Operations (2020) (5)
- Yield analysis for repairable embedded memories (2003) (5)
- Secure Assay Execution on MEDA Biochips to Thwart Attacks Using Real-Time Sensing (2020) (4)
- Graph Neural Network-based Delay-Fault Localization for Monolithic 3D ICs (2022) (4)
- Testing and Diagnosis (2010) (4)
- Characterizing Coherent Integrated Photonic Neural Networks Under Imperfections (2022) (4)
- Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs (2008) (4)
- Machine Learning-Based Aging Analysis (2019) (4)
- An ECO Technique for Removing Crosstalk Violations in Clock Networks (2007) (4)
- Test Access Mechanism Optimization (2002) (4)
- Design and optimization of 3D digital microfluidic biochips for the polymerase chain reaction (2015) (4)
- Fault-Tolerant Neuromorphic Computing Systems (2019) (4)
- Deterministic test for the reproduction and detection of board-level functional failures (2011) (4)
- Pruning Coherent Integrated Photonic Neural Networks Using the Lottery Ticket Hypothesis (2021) (4)
- A Metric to Target Small-Delay Defects in Industrial Circuits (2011) (4)
- CHAMP: Coherent Hardware-Aware Magnitude Pruning of Integrated Photonic Neural Networks (2021) (4)
- Security Against Data-Sniffing and Alteration Attacks in IJTAG (2021) (4)
- Online soft-error vulnerability estimation for memory arrays (2016) (4)
- Power-Supply Noise Analysis for Monolithic 3D ICs Using Electrical and Thermal Co-Simulation (2018) (4)
- An inter-layer interconnect BIST solution for monolithic 3D ICs (2018) (4)
- An Optimal Two-Mixer Dilution Engine with Digital Microfluidics for Low-Power Applications (2014) (4)
- Two-dimensional time-division multiplexing for 3D-SoCs (2016) (4)
- System/Network-On-Chip Test Architectures (2008) (4)
- Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs (2022) (4)
- Test Data Compression Using Golomb Codes (2002) (4)
- Defect Coverage-Driven Window-Based Test Compression (2010) (4)
- Factorization based dilution of biochemical fluids with micro-electrode-dot-array biochips (2019) (4)
- Testing 3D-SoCs Using 2-D Time-Division Multiplexing (2018) (4)
- Runtime Identification of Hardware Trojans by Feature Analysis on Gate-Level Unstructured Data and Anomaly Detection (2020) (4)
- Digital Microfluidic Logic Gates (2008) (4)
- On Designing Efficient and Reliable Nonvolatile Memory-Based Computing-In-Memory Accelerators (2019) (4)
- Techniques to Reduce Communication and Computation Energy in Wireless Sensor Networks (2006) (4)
- 3D-ReG (2020) (4)
- Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation (2005) (4)
- Defect-Oriented and Time-Constrained Wafer-Level Test-Length Selection for Core-Based Digital SoCs (2006) (4)
- Design Technologies for Green and Sustainable Computing Systems (2013) (4)
- High-Throughput Training of Deep CNNs on ReRAM-Based Heterogeneous Architectures via Optimized Normalization Layers (2022) (4)
- Pruning of Deep Neural Networks for Fault-Tolerant Memristor-based Accelerators (2021) (4)
- Delay Test and Small-Delay Defects (2011) (4)
- DARe: DropLayer-Aware Manycore ReRAM architecture for Training Graph Neural Networks (2021) (4)
- Sensor-Array Optimization Based on Mutual Information for Sanitation-Related Malodor Alerts (2019) (4)
- Knowledge Transfer in Board-Level Functional Fault Diagnosis Enabled by Domain Adaptation (2021) (4)
- The hype, myths, and realities of testing 3D integrated circuits (2016) (4)
- Access-Time Minimization in the IEEE 1687 Network Using Broadcast and Hardware Parallelism (2018) (4)
- Performance and Accuracy Tradeoffs for Training Graph Neural Networks on ReRAM-Based Architectures (2021) (4)
- Access-Time Minimization for the IJTAG Network Using Data Broadcast and Hardware Parallelism (2021) (3)
- Functional Criticality Analysis of Structural Faults in AI Accelerators (2022) (3)
- Security Assessment of Microfluidic Immunoassays (2019) (3)
- Stool Image Analysis for Precision Health Monitoring by Smart Toilets (2021) (3)
- Balance testing of logic circuits (1993) (3)
- Unsupervised Two-Stage Root-Cause Analysis for Integrated Systems (2022) (3)
- Output selection for test response compaction based on multiple counters (2014) (3)
- VFI-Based Power Management to Enhance the Lifetime of High-Performance 3D NoCs (2017) (3)
- A New LFSR Reseeding Scheme via Internal Response Feedback (2013) (3)
- Data-Driven Optimization of Order Admission Policies in a Digital Print Factory (2015) (3)
- Programmable Daisychaining of Microelectrodes for IP Protection in MEDA Biochips (2019) (3)
- Can Multi-Layer Microfluidic Design Methods Aid Bio-Intellectual Property Protection? (2019) (3)
- Test-Length Selection and TAM Optimization for Wafer-Level, Reduced Pin-Count Testing of Core-Based Digital SoCs (2007) (3)
- Detection of Rowhammer Attacks in SoCs with FPGAs (2020) (3)
- Thwarting Bio-IP Theft Through Dummy-Valve-Based Obfuscation (2021) (3)
- Characterization and Optimization of Coherent MZI-Based Nanophotonic Neural Networks Under Fabrication Non-Uniformity (2022) (3)
- Fault Recovery in Micro-Electrode-Dot-Array Digital Microfluidic Biochips Using an IJTAG NetworkBehaviors (2019) (3)
- System-Level Design Methodology (2014) (3)
- Post-DfT-insertion retiming for delay recovery on inter-die paths in 3D ICs (2013) (3)
- Secure and Trustworthy Cyberphysical Microfluidic Biochips (2019) (3)
- Cyberphysical Microfluidic Biochips (2019) (3)
- Retiming for Delay Recovery After DfT Insertion on Interdie Paths in 3-D ICs (2014) (3)
- Multicast Test Architecture and Test Scheduling for Interposer-Based 2.5D ICs (2016) (3)
- The role of EDA in digital print automation and infrastructure optimization (2011) (3)
- Digital microfluidic biochip security (2017) (3)
- How Secure Are Checkpoint-Based Defenses in Digital Microfluidic Biochips? (2021) (3)
- Built-in self-test for interposer-based 2.5D ICs (2014) (3)
- Tackling Test Challenges for Interposer-Based 2.5-D Integrated Circuits (2017) (3)
- Enhancing the Reliability of MEDA Biochips Using IJTAG and Wear Leveling (2021) (3)
- Formal Synthesis of Adaptive Droplet Routing for MEDA Biochips* (2021) (3)
- 3D-Scalable Adaptive Scan (3D-SAS) (2012) (3)
- Efficient Pattern Generation for Small-Delay Defects Using Selection of Critical Faults (2013) (3)
- Offline Washing Schemes for Residue Removal in Digital Microfluidic Biochips (2015) (3)
- Screen printed contacts formation by rapid thermal annealing in multicrystalline silicon solar cells (2002) (3)
- Testing of interposer-based 2.5D integrated circuits (2017) (3)
- Test and Design-for-Testability Solutions for Monolithic 3D Integrated Circuits (2019) (3)
- Test Generation for Flow-Based Microfluidic Biochips With General Architectures (2020) (3)
- Fault-Criticality Assessment for AI Accelerators using Graph Convolutional Networks (2021) (3)
- Emerging Circuit Technologies: An Overview on the Next Generation of Circuits (2018) (3)
- LoCI: An Analysis of the Impact of Optical Loss and Crosstalk Noise in Integrated Silicon-Photonic Neural Networks (2022) (3)
- Unsupervised Root-Cause Analysis for Integrated Systems (2020) (3)
- Test-Access Solutions for Three-Dimensional SOCs (2008) (3)
- Power-Aware Test Data Compression and BIST (2010) (3)
- Learning to Train CNNs on Faulty ReRAM-based Manycore Accelerators (2021) (3)
- Design and optimization methods for digital microfluidic biochips: A vision for functional diversity and more than moore (2011) (3)
- Automated Design of Microfluidics-Based Biochips: Connecting Biochemistry to Electronics CAD (2006) (3)
- Fabrication Defects and Fault Models for DNA Self-Assembled Nanoelectronics (2008) (3)
- Unsupervised Root-Cause Analysis with Transfer Learning for Integrated Systems (2021) (3)
- Cyberphysical adaptation in digital-microfluidic biochips (2016) (3)
- Dual-threshold pass-transistor logic design (2009) (3)
- Chip Health Monitoring Using Machine Learning (2014) (3)
- Variation-Aware Delay Fault Testing for Carbon-Nanotube FET Circuits (2021) (3)
- The Internet of Microfluidic Things: Perspectives on System Architecture and Design Challenges: Invited Paper (2019) (3)
- Optimization and Selection of Diagnosis-Oriented Fault-Insertion Points for System Test (2010) (3)
- An Interlayer Interconnect BIST and Diagnosis Solution for Monolithic 3-D ICs (2020) (3)
- A Design-for-Test Solution for Monolithic 3D Integrated Circuits (2017) (2)
- ExTest Scheduling and Optimization for 2.5-D SoCs With Wrapped Tiles (2017) (2)
- Pre-bond testing of die logic and TSVs in high performance 3D-SICs (2012) (2)
- Online Fault Detection in ReRAM-Based Computing Systems by Monitoring Dynamic Power Consumption (2020) (2)
- A flexible design methodology for analog test wrappers in mixed-signal SOCs (2005) (2)
- Workload-Aware Static Aging Monitoring and Mitigation of Timing-Critical Flip-Flops (2018) (2)
- Authentication of sensor network flooding based on neighborhood cooperation (2006) (2)
- DFBT: A Design-for-Testability Method Based on Balance Testing (1994) (2)
- Test Generation of Path Delay Faults Induced by Defects in Power TSV (2013) (2)
- Testing of digital microfluidic biochips with arbitrary layouts (2015) (2)
- Computer-Aided Design of Microfluidic Very Large Scale Integration (Mvlsi) Biochips: Design Automation, Testing, and Design-For-Testability (2017) (2)
- BioScan: Parameter-Space Exploration of Synthetic Biocircuits Using MEDA Biochips∗ (2019) (2)
- Mixing Models as Integer Factorization: A Key to Sample Preparation With Microfluidic Biochips (2022) (2)
- NodeRank: Observation-Point Insertion for Fault Localization in Monolithic 3D ICs∗ (2020) (2)
- Black-Box Test-Cost Reduction Based on Bayesian Network Models (2021) (2)
- Fluorescent detection of nucleosomes using functionalized magnetic beads on a digital microfluidic device (2021) (2)
- A Branch-&-Bound Test-Access-Mechanism Optimization Method for Multi- $V_{\mathrm{ dd}}$ SoCs (2017) (2)
- A distributed, reconfigurable, and reusable bist infrastructure for 3D-stacked ICs (2014) (2)
- Diagnosis Using Support Vector Machines (SVM) (2017) (2)
- Introduction to VLSI Testing (2011) (2)
- Test and debug solutions for 3D-stacked integrated circuits (2015) (2)
- Compressing Test Data for Deterministic BIST Using a Reconfigurable Scan Arhcitecture (2006) (2)
- Unified design and optimization tools for digital microfluidic biochips (2011) (2)
- Anomaly Detection and Health-Status Analysis in a Core Router System (2019) (2)
- Advances in nanoelectronics circuits and systems [Editorial] (2009) (2)
- Bit-Operation-Based Seed Augmentation for LFSR Reseeding with High Defect Coverage (2009) (2)
- An Efficient Fault-Tolerant Valve-Based Microfluidic Routing Fabric for Droplet Barcoding in Single-Cell Analysis (2020) (2)
- Pre-bond Testing of the Silicon Interposer (2017) (2)
- Design Automation and Test Solutions for Monolithic 3D ICs (2022) (2)
- Analysis and Design of Tamper-Mitigating Microfluidic Routing Fabrics (2020) (2)
- Adaptive Droplet Routing for MEDA Biochips via Deep Reinforcement Learning (2022) (2)
- Cyber-physical integration in programmable microfluidic biochips (2015) (2)
- Critical Fault-Based Pattern Generation for Screening SDDs (2011) (2)
- Introduction to Diagnosis (2011) (2)
- Reduced-Complexity Transition-Fault Test Generation for Non-scan Circuits through High-Level Mutant Injection (2012) (2)
- Optimization of droplet routing for an n-plex bioassay on a digital microfluidic lab-on-chip (2009) (2)
- A branch-&-bound algorithm for TAM optimization in multi-Vdd SoCs (2015) (2)
- Power Supply Noise-Aware Scan Test Pattern Reshaping for At-Speed Delay Fault Testing of Monolithic 3D ICs * (2020) (2)
- Functional-Like Transition Delay Fault Test-Pattern Generation using a Bayesian-Based Circuit Model (2020) (2)
- Current Status of Layer Transfer Process in Thin Silicon Solar Cell : a review (2004) (2)
- ESSENCE: Exploiting Structured Stochastic Gradient Pruning for Endurance-aware ReRAM-based In-Memory Training Systems (2022) (2)
- On-line Functional Testing of Memristor-mapped Deep Neural Networks using Backdoored Checksums (2021) (2)
- Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes (2004) (2)
- Hardware Design and Experimental Demonstrations for Digital Acoustofluidic Biochips (2019) (2)
- Guest Editors' Introduction: Biochips and Integrated Biosensor Platforms (2007) (2)
- RTL-to-GDS Design Tools for Monolithic 3D ICs (2020) (2)
- Study on Combined Test-Data Compression and Test Planning for Testing of Modular SoCs (2010) (2)
- SOC Test Optimization with Compression-Technique Selection (2008) (2)
- Hardware Design and Fault-Tolerant Synthesis for Digital Acoustofluidic Biochips (2020) (2)
- Molecular Barcoding as a Defense Against Benchtop Biochemical Attacks on DNA Fingerprinting and Information Forensics (2020) (2)
- Fault Modeling, Testing, and Design for Testability (2017) (2)
- Lotus: A New Topology for Large-scale Distributed Machine Learning (2020) (2)
- Efficient Identification of Critical Faults in Memristor-Based Inferencing Accelerators (2022) (2)
- Anomaly-Detection-Based Failure Prediction in a Core Router System (2016) (2)
- Structural Test and Functional Test for Digital Acoustofluidic Biochips (2019) (2)
- Novel low-cost technique of emitter-junction optimization in silicon solar cells (2005) (2)
- Cost model driven test resource partitioning for socs (2006) (2)
- Toward Secure Checkpointing for Micro-Electrode-Dot-Array Biochips (2020) (2)
- Special session paper: data analytics enables energy- efficiency and robustness: from mobile to manycores, datacenters, and networks (2017) (2)
- Inexact Silicon Photonics: From Devices to Applications (2021) (2)
- Test-Architecture Optimization and Test Scheduling (2014) (2)
- Fine-grained Adaptive Testing Based on Quality Prediction (2020) (2)
- Biochemistry Synthesis Under Completion-Time Uncertainties in Fluidic Operations (2015) (1)
- Self-awareness and self-learning for resiliency in real-time systems (2015) (1)
- Fusion of IoT, AI, Edge–Fog–Cloud, and Blockchain: Challenges, Solutions, and a Case Study in Healthcare and Medicine (2023) (1)
- An evaluation of the impact of gate oxide tunneling on dual-Vt-based leakage reduction techniques (2006) (1)
- Exact Routing for MicroElectrode-Dot-Array Digital Microfluidic Biochips (2016) (1)
- A BIST-based Dynamic Obfuscation Scheme for Resilience against Removal and Oracle-guided Attacks* (2021) (1)
- Built-In Self Test and Diagnosis (2013) (1)
- Machine Learning-Based Rowhammer Mitigation (2023) (1)
- Towards Functionally Robust AI Accelerators (2021) (1)
- ExTest Scheduling and Optimization (2017) (1)
- Automatic Structural Test Generation for Analog Circuits using Neural Twins (2022) (1)
- Accurate Anomaly Detection Using Correlation-Based Time-Series Analysis (2019) (1)
- IJTAG-Based Fault Recovery and Robust Microelectrode-Cell Design for MEDA Biochips (2020) (1)
- Digital Microfluidics: Connecting Biochemistry to Electronic System Design (2007) (1)
- Data analytics enables energy-efficiency and robustness: from mobile to manycores, datacenters, and networks (special session paper) (2017) (1)
- Adaptive Methods for Machine Learning-Based Testing of Integrated Circuits and Boards (2021) (1)
- Defect Tolerance Based on Graceful Degradation (2006) (1)
- 1 Generation of Compact Single-Detect Stuck-At Test Sets Targeting Unmodeled Defects (2010) (1)
- Testing of Interposer-Based 2.5D Integrated Circuits: Challenges and Solutions (2016) (1)
- Adaptive and reconfiguration-based error recovery in cyberphysical biochips (2015) (1)
- Test-Cost Reduction for 2.5D ICs Using Microspring Technology for Die Attachment and Rework (2019) (1)
- Design and Test of Microfluidic Biochips (2007) (1)
- Accumulator-based output selection for test response compaction (2012) (1)
- Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs (2018) (1)
- Multicast Testing of Interposer-Based 2.5D ICs (2018) (1)
- Board-Level Functional Fault Identification Using Streaming Data (2021) (1)
- Optimal Two-Mixer Scheduling in Dilution Engine on a Digital Microfluidic Biochip (2013) (1)
- Architectural-Level Synthesis (2006) (1)
- Editorial (2017) (1)
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- Hierarchical Symbol-Based Health-Status Analysis Using Time-Series Data in a Core Router System (2020) (1)
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- Workload-aware static aging monitoring of timing-critical flip-flops (2017) (1)
- Probabilistic Fault Grading for AI Accelerators using Neural Twins (2022) (1)
- Core-Level Expansion of Compressed Test Patterns (2008) (1)
- Core-Level Compression Technique Selection and SOC Test Architecture Design (2008) (1)
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- Toward fault-tolerant and reconfigurable digital microfluidic biochips (2010) (1)
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- Advances in Testing and Design-for-Test Solutions for M3D Integrated Circuits* (2021) (1)
- Learning Malicious Circuits in FPGA Bitstreams (2023) (1)
- Securing Biochemical Samples Using Molecular Barcoding on Digital Microfluidic Biochips* (2021) (1)
- Fault Modeling, Structural Testing, and Functional Testing (2018) (1)
- Editorial to special issue DAC 2006 (2007) (1)
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- Quo Vadis Test? The Past, the Present, and the Future: No Longer a Necessary Evil (2017) (1)
- Advances in Target Tracking and Active Surveillance Using Wireless Sensor Networks (2005) (1)
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- Runtime Malware Detection Using Embedded Trace Buffers (2022) (1)
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- Re-using chip level DFT at board level (2012) (0)
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- SYSTEMS WITH POINT-TO-POINT COMMUNICATION LINKS (1998) (0)
- Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies (2008) (0)
- Defect-Oriented Testing and Diagnosis (2006) (0)
- Information-Theoretic Syndrome and Root-Cause Evaluation (2017) (0)
- Conclusion and Future Outlook (2020) (0)
- Pre-assembly testing of interconnects in embedded multi-die interconnect bridge (EMIB) dies (2018) (0)
- TaintLock: Preventing IP Theft through Lightweight Dynamic Scan Encryption using Taint Bits* (2022) (0)
- Optimization of Order-Admission Policies (2015) (0)
- Improved Test Bus Partitioning (2002) (0)
- Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning (VLSI設計技術) (2007) (0)
- Adaptive Mitigation of Parameter Variations (2014) (0)
- Defect-Tolerant and Routing-Aware Synthesis (2010) (0)
- Testing of Low-cost Digital Microfluidic Biochips with Non-Regular Array Layouts (2011) (0)
- Predictive Analytics for Anomaly Detection and Failure Prediction in Complex Core Routers (2018) (0)
- Metal Surface Treatment Effects on Screen Printed Silicon Solar Cells (2003) (0)
- Observation-Point Selection at the Register-Transfer Level to Enhance Defect Coverage for Functional Test Sequences ∗ (2015) (0)
- Fault-Tolerant Realization of Biomolecular Assays (2020) (0)
- Supplementary Document: Parallel Droplet Control in MEDA Biochips using Multi-Agent Reinforcement Learning (2021) (0)
- Enhanced Built-In Self-Diagnosis and Self-Repair Techniques for Daisy-Chain Design in MEDA Digital Microfluidic Biochips (2023) (0)
- Can assay outcomes of digital microfluidic biochips be manipulated (2015) (0)
- Robust Fault-Recovery Method for MEDA Biochips Using an IJTAG Network (2020) (0)
- Mobility Management with Integrated Coverage and Connectivity (2014) (0)
- Wash Optimization for Cross-Contamination Removal (2017) (0)
- Special session on machine learning for test and diagnosis (2018) (0)
- Circuit-level Optimization (2002) (0)
- Editorial (2017) (0)
- Design automation for biochemistry synthesis on a digital microfluidic lab-on-a-chip (2014) (0)
- Synterface: Efficient Chip-to-World Interfacing for Flow-Based Microfluidic Biochips Using Pin-Count Minimization (2019) (0)
- A Proposal to Adjust the Time-Keeping Systems for Savings in Cycling Operation and Carbon Emission (2019) (0)
- Efficient Test Application for Core-Based Systems Using Twisted-Ring Counters (2001) (0)
- Cytoskeletal Participation in Reciprocal Translocation of Arrestin in Rod Photoreceptor Cells (2002) (0)
- Guest Editorial (2002) (0)
- Pin-Count Minimization for Application-Independent Chips (2015) (0)
- Test Wrapper and TAM Co-Optimization (2002) (0)
- Long Path-Based Hybrid Method (2011) (0)
- Table of Contents: ATS 2006 Proceedings of the 15 th Asian Test Symposium (2006) (0)
- Introduction to DAC 2007 special section (2008) (0)
- Structural Test Generation for AI Accelerators using Neural Twins (2022) (0)
- Test Planning (2018) (0)
- Guest Editorial (2011) (0)
- A Survey of Energy-Efficient Self-Organization and Data Dissemination Protocols for Ad Hoc Sensor Networks (2004) (0)
- Message from the ATS 2014 General Co-Chairs (2014) (0)
- Maximizing Crosstalk Effect on Critical Paths (2011) (0)
- Deep Neural Network Piration without Accuracy Loss (2022) (0)
- Digital Microfluidic Biochips: Towards Functional Diversity, More than Moore, and Cyberphysical Integration (2015) (0)
- Production Workflow Optimization (2015) (0)
- Efficient Regulation of Synthetic Biocircuits Using Droplet-Aliquot Operations on MEDA Biochips (2021) (0)
- Report from Dagstuhl Seminar 19152 Emerging Hardware Techniques and EDA Methodologies for Neuromorphic Computing (2019) (0)
- A Framework for Automated Correctness Checking of Biochemical Protocol Realizations on Digital Microfluidic Biochips (2022) (0)
- Test resource partitioning and test data compression for system-on-a-chip (2002) (0)
- Design of a Reliable Power Delivery Network for Monolithic 3D ICs* (2020) (0)
- Optimization of On-Chip Polymerase Chain Reaction (2015) (0)
- Deep Reinforcement Learning-Based Approach for Efficient and Reliable Droplet Routing on MEDA Biochips (2023) (0)
- Design of Microfluidic Biochips (Dagstuhl Seminar 15352) (2015) (0)
- Test Technology Newsletter (2011) (0)
- Unsupervised Two-Stage Root-Cause Analysis With Transfer Learning for Integrated Systems (2023) (0)
- Application to Protein Crystallization (2010) (0)
- Structural Attacks and Defenses for Flow-Based Microfluidic Biochips (2022) (0)
- SystemC-based Hierarchical Design Environment (2002) (0)
- Security Vulnerabilities of Quantitative-Analysis Frameworks (2020) (0)
- Wafer Stacking and 3D Memory Test (2014) (0)
- Optimization of Test‐Access Architectures and Test Scheduling for 3D ICs (2019) (0)
- Timing-Driven Synthesis with Pin Constraints: Single-Cell Screening (2020) (0)
- Accurate and Robust Malware Detection: Running XGBoost on Runtime Data From Performance Counters (2021) (0)
- Synthesis of Protocols with Indexed Samples: Single-Cell Analysis (2020) (0)
- ’ Introduction : Biochips and Integrated Biosensor Platforms (2007) (0)
- TECHNICAL CO-SPONSORING SOCIETIES Computational Intelligence (2008) (0)
- Concurrent Testing (2018) (0)
- Machine Learning for Testing Machine-Learning Hardware: A Virtuous Cycle∗ (2022) (0)
- CISCO IP Routing Protocols (2005) (0)
- TRP for Low-Power Scan Testing (2002) (0)
- Making Analog & Mixed Signal Testing As Robust As Digital (2007) (0)
- ReaLPrune: ReRAM Crossbar-Aware Lottery Ticket Pruning for CNNs (2022) (0)
- Error-Tolerant Digital Microfluidic Lab-on-Chip (2012) (0)
- On-Line Testing and Test Generation (2013) (0)
- Pruning Coherent Integrated Photonic Neural Networks (2023) (0)
- Security of Biochip Cyberphysical Systems (2022) (0)
- Power Supply Noise-Aware At-Speed Delay Fault Testing of Monolithic 3-D ICs (2021) (0)
- Synthesis for Multiple Sample Pathways: Gene-Expression Analysis (2020) (0)
- Graph Neural Network-based Delay-Fault Localization for Monolithic 3D ICs (2022) (0)
- Session details: Tutorial 2 (2011) (0)
- Prevention: Tamper-Resistant Pin-Constrained Digital Microfluidic Biochips (2019) (0)
- Mitigation: Tamper-Mitigating Routing Fabrics (2019) (0)
- A Programmable Method for Low-Power Scan Shift in SoC Dies (2017) (0)
- 2.2 Physical Attacks (2019) (0)
- Microfluidic Device Security (2020) (0)
- Guest Editorial - Selected Papers from the IEEE International Mixed-Signals, Sensors, and Systems Test Workshop (IMS3TW), 2008 (2009) (0)
- Self-learning and Efficient Health-Status Analysis (2019) (0)
- Knowledge Discovery and Knowledge Transfer (2017) (0)
- An Efficient Energy-Optimal Device-Scheduling Algorithm for Hard Real-Time Systems (2004) (0)
- Looking ahead at the role of electronic design automation in synthetic biology [From the EIC] (2012) (0)
- Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor (0)
- Testing bio-chips (2009) (0)
- Test Infrastructure Design (2011) (0)
- Synthesis of Protocols with Temporal Constraints: Epigenetic Analysis (2020) (0)
- Predictions of Process-Execution Time and Process-Execution Status (2015) (0)
- Editorial (2015) (0)
- A Hierarchical Design Platform for Microelectrofluidic Systems (MEFS) (2006) (0)
- Testing and design-for-testability solutions for 3D integrated circuits (2011) (0)
- Sensor-based evaluation of a Urine Trap toilet in a shared bathroom (2022) (0)
- Machine Learning for Hardware Security: Opportunities and Risks (2018) (0)
- BISTLock: Efficient IP Piracy Protection using BIST (2020) (0)
- Detection: Randomizing Checkpoints on Cyberphysical Digital Microfluidic Biochips (2019) (0)
- Special Session: Fault Criticality Assessment in AI Accelerators (2022) (0)
- Enhanced fluorescent detection of nucleosomes using functionalized magnetic beads on a digital microfluidic device (2022) (0)
- Accelerating Graph Neural Network Training on ReRAM-based PIM Architectures via Graph and Model Pruning (2022) (0)
- Pin-Constrained Chip Design (2010) (0)
- H$^2$OEIN: A Hierarchical Hybrid Optical/Electrical Interconnection Network for Exascale Computing Systems (2018) (0)
- Reconfigurable Microfluidic System Architecture Based on Two-Dimensional Electrowetting Arrays (2005) (0)
- Analysis and Prediction of Enterprise Service-Level Performance (2015) (0)
- Machine Learning for Test, Diagnosis, Post-Silicon Validation and Yield Optimization (2022) (0)
- Detection and Classification of Malicious Bitstreams for FPGAs In Cloud Computing (2023) (0)
- Electronic Design Methods and Technologies for Green Buildings (2012) (0)
- Synchronization of Concurrently-Implemented Fluidic Operations in Pin-Constrained Biochips (2013) (0)
- Tutorials [2 abstracts] (2013) (0)
- Chapter 33 ADAPTIVE CHECKPOINTING WITH DYNAMIC VOLTAGE SCALING IN EMBEDDED REAL-TIME SYSTEMS (0)
- Diagnosis of Malicious Bitstreams in Cloud Computing FPGAs* (2023) (0)
- Dynamic I/O power management in real-time systems with multiple-state I/O devices (2002) (0)
- Generalized Error-Correcting Sample Preparation (2018) (0)
- Foreword (2016) (0)
- Test Scheduling Using Mixed-Integer Linear Programming (2002) (0)
- 2012 JETTA Reviewers (2013) (0)
- Mathematical Modeling of Intellectual Property Protection Using Partially-Mergeable Cores (2000) (0)
- Overcoming the Timing Overhead of Test Architectures on Inter-Die Critical Paths (2014) (0)
- Self-Learning Health-Status Analysis for a Core Router System (2018) (0)
- A Microuidics-Driven Cloud Service: Genomic Association Studies (2020) (0)
- Test Architecture and Test-Path Scheduling (2017) (0)
- Post-bond Scan-Based Testing of Interposer Interconnects (2017) (0)
- Real-Time Error Recovery Using a Compact Dictionary (2015) (0)
- Built-In Self-Test for TSVs (2014) (0)
- Conclusions and New Directions (2018) (0)
- Editorial First TVLSI Best AE and Reviewer Awards (2016) (0)
- Emerging Hardware Techniques and EDA Methodologies for Neuromorphic Computing (Dagstuhl Seminar 19152) (2019) (0)
- Testing and Fault-Localization Solutions for Monolithic 3D ICs* (2021) (0)
- Micro-Electrode-Dot-Array Digital Microfluidic Biochips (2018) (0)
- Special Session: Continuous-Flow Biochips: Current Platforms and Emerging Research Challenges (2015) (0)
- Reconfiguration-Based Defect Tolerance for Microfluidic Biochips (2006) (0)
- SSCS Becomes Copublisher of IEEE Design & Test of Computers Magazine [Society News] (2012) (0)
- Security and Trust (2019) (0)
- Towards more digital content in wireless systems [From the EiC] (2012) (0)
- Engineering in Medicine and Biology B. HE, President TECHNICAL CO-SPONSORING SOCIETIES Computational Intelligence (2009) (0)
- Diagnosis Using Multiple Classifiers and Majority-Weighted Voting (WMV) (2017) (0)
- Conclusions and Future Work (2018) (0)
- ParaMitE: Mitigating Parasitic CNFETs in the Presence of Unetched CNTs (2021) (0)
- Techniques for Fault Diagnosis (2017) (0)
- Software-based test and diagnosis of SoCs using embedded and wide-I/O DRAM (2015) (0)
- Pre-bond Scan Test Through TSV Probing (2014) (0)
- Test-Architecture Optimization for 3 D Stacked ICs (2013) (0)
- Continuous-flow biochips: Current platforms and emerging research challenges: Special Session (2015) (0)
- PriRecT: Privacy-preserving Job Recommendation Tool for GPU Sharing (2022) (0)
- Editorial (2008) (0)
- Self-Learning and Efficient Health-Status Analysis for a Core Router System (2020) (0)
- Formal Synthesis of Adaptive Droplet Routing for MEDA Biochips (2022) (0)
- Improvement of Commercial Silicon Solar Cells with N + -P-N + Structure using Halogenic Oxide Passivation (2003) (0)
- Microfluidic Biochips: Bridging Biochemistry with Computer Science and Engineering (NII Shonan Meeting 2017-1) (2017) (0)
- Post-Bond Test Wrappers and Emerging Test Standards (2014) (0)
- Handling Missing Syndromes (2017) (0)
- Hierarchical Intellectual Property Protection Using Partially-Mergeable Cores (2001) (0)
- Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies (2008) (0)
- Maximizing Power Supply Noise on Critical Paths (2011) (0)
- Microelectrofluidic Systems: Modeling & Simulation [Book Review] (2004) (0)
- Security Countermeasures of Quantitative-Analysis Frameworks (2020) (0)
- Faster-Than-At-Speed Test (2011) (0)
- The Quest for High-Yield IC Manufacturing (2012) (0)
- Defect Tolerance Based on Space Redundancy (2006) (0)
- An efficient fault-tolerant valve-based microfluidic routing fabric for single-cell analysis (2018) (0)
- Feasibility Analysis and Dynamic Voltage Scaling in Fault-Tolerant Real-Time Embedded Systems (2005) (0)
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