Krste Asanovic̀

Q: What Schools Are Affiliated With Krste Asanovic̀

Krste Asanovic̀ is affiliated with the following schools: University of California, Berkeley, Massachusetts Institute of Technology

Krste Asanovic̀'s AcademicInfluence.com Rankings

Krste Asanovic̀

Engineering

#7164

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#8527

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Electrical Engineering

#2214

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#2320

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Krste Asanovic̀

Computer Science

#9643

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#10120

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Parallel Computing

#53

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#55

Historical Rank

Computer Architecture

#61

World Rank

#63

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Database

#6606

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#6841

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computer-science Degrees

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Engineering
Computer Science

Krste Asanovic̀'s Degrees

Bachelors Electrical Engineering and Computer Science University of California, Berkeley

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Krste Asanovic̀'s Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

The Landscape of Parallel Computing Research: A View from Berkeley (2006) (2362)
Single-chip microprocessor that communicates directly using light (2015) (937)
Chisel: Constructing hardware in a Scala embedded language (2012) (688)
A view of the parallel computing landscape (2009) (653)
Unbounded transactional memory (2005) (554)
Optimizing matrix multiply using PHiPAC: a portable, high-performance, ANSI C coding methodology (1997) (495)
The Rocket Chip Generator (2016) (424)
Direction-optimizing Breadth-First Search (2012) (411)
Energy-aware lossless data compression (2006) (380)
Victim replication: maximizing capacity while hiding wire delay in tiled chip multiprocessors (2005) (364)
Reducing power density through activity migration (2003) (340)
Silicon-photonic clos networks for global on-chip communication (2009) (333)
Mondrian memory protection (2002) (323)
The GAP Benchmark Suite (2015) (276)
Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics (2008) (273)
PHANTOM: practical oblivious computation in a secure processor (2013) (234)
Scalable Processors in the Billion-Transistor Era: IRAM (1997) (223)
Dynamic zero compression for cache energy reduction (2000) (223)
Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics (2009) (220)
RAMP: Research Accelerator for Multiple Processors (2007) (215)
Keystone: an open framework for architecting trusted execution environments (2020) (196)
The vector-thread architecture (2004) (194)
Optimizing matrix multiply using PHiPAC: a portable, high-performance, ANSI C coding methodology (1997) (190)
Vector microprocessors (1998) (170)
Energy Aware Lossless Data Compression (2003) (170)
Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks (2008) (164)
Locality Exists in Graph Processing: Workload Characterization on an Ivy Bridge Server (2015) (149)
Banked multiported register files for high-frequency superscalar microprocessors (2003) (140)
The Berkeley Out-of-Order Machine (BOOM): An Industry-Competitive, Synthesizable, Parameterized RISC-V Processor (2015) (136)
Dynamic fine-grain leakage reduction using leakage-biased bitlines (2002) (133)
A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness (2013) (129)
RAMP gold: An FPGA-based architecture simulator for multiprocessors (2010) (127)
FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud (2018) (123)
Mondrix: memory isolation for linux using mondriaan memory protection (2005) (123)
Re-architecting DRAM memory systems with monolithically integrated silicon photonics (2010) (123)
Tessellation: space-time partitioning in a manycore client OS (2009) (122)
SEJITS: Getting Productivity and Performance With Selective Embedded JIT Specialization (2010) (120)
A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators (2014) (120)
FireBox: A Hardware Building Block for 2020 Warehouse-Scale Computers (2014) (120)
Spert-II: A Vector Microprocessor System (1996) (112)
The RISC-V Instruction Set Manual Volume 2: Privileged Architecture Version 1.7 (2015) (95)
Highly-Associative Caches for Low-Power Processors (2000) (94)
Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators (2013) (93)
Parallelizing the web browser (2009) (85)
Designing Chip-Level Nanophotonic Interconnection Networks (2012) (84)
A case for FAME: FPGA architecture model execution (2010) (82)
An Agile Approach to Building RISC-V Microprocessors (2016) (81)
Direct addressed caches for reduced power consumption (2001) (80)
Composing parallel software efficiently with lithe (2010) (79)
Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs (2020) (77)
Trash Day: Coordinating Garbage Collection in Distributed Systems (2015) (75)
Energy-efficient register access (2000) (70)
Replacing global wires with an on-chip network: a power analysis (2005) (68)
SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS (2012) (66)
Tessellation: Refactoring the OS around explicit resource containers with continuous adaptation (2013) (65)
Convergence and scalarization for data-parallel architectures (2013) (65)
Distributed Memory Breadth-First Search Revisited: Enabling Bottom-Up Search (2013) (65)
The Parallel Computing Laboratory at U.C. Berkeley: A Research Agenda Based on the Berkeley View (2008) (65)
Taurus: A Holistic Language Runtime System for Coordinating Distributed Managed-Language Applications (2016) (64)
NeuroVectorizer: end-to-end vectorization with deep reinforcement learning (2019) (61)
Reducing Pagerank Communication via Propagation Blocking (2017) (61)
Intelligent RAM (IRAM): the industrial setting, applications, and architectures (1997) (61)
Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators (2011) (60)
Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors (2015) (59)
Rethinking Hardware Support for Network Analysis and Intrusion Prevention (2006) (56)
A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC–DC Converters in 28 nm FDSOI (2016) (56)
The design of a neuro-microprocessor (1993) (56)
Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy (2001) (55)
Research accelerator for multiple processors (2006) (53)
Way Memoization to Reduce Fetch Energy in Instruction Caches (2001) (53)
Leakage-biased domino circuits for dynamic fine-grain leakage reduction (2002) (52)
Accelerating Multiprocessor Simulation with a Memory Timestamp Record (2005) (51)
Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration (2019) (50)
Gemmini: An Agile Systolic Array Generator Enabling Systematic Evaluations of Deep-Learning Architectures (2019) (49)
Victim Migration: Dynamically Adapting Between Private and Shared CMP Caches (2005) (46)
Resource Management in the Tessellation Manycore OS ∗ (2010) (45)
A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI (2015) (43)
Searching for a Parent Instead of Fighting Over Children : A Fast Breadth-First Search Implementation for Graph 500 (2011) (43)
Controlling program execution through binary instrumentation (2005) (42)
Keystone: A Framework for Architecting TEEs (2019) (41)
METERG: Measurement-Based End-to-End Performance Estimation Technique in QoS-Capable Multiprocessors (2006) (40)
Activity-sensitive flip-flop and latch selection for reduced energy (2007) (38)
Using PHiPAC to speed error back-propagation learning (1997) (35)
Parallel neural network training on Multi-Spert (1997) (35)
Virtual Local Stores: Enabling Software-Managed Memory Hierarchies in Mainstream Computing Environments (2009) (33)
Keystone: An Open Framework for Architecting TEEs (2019) (32)
Lithe: enabling efficient composition of parallel libraries (2009) (32)
Versatility and VersaBench: A New Metric and a Benchmark Suite for Flexible Architectures (2004) (32)
FPGA Accelerated INDEL Realignment in the Cloud (2019) (32)
Cache Refill/Access Decoupling for Vector Machines (2004) (32)
Distributed-Memory Breadth-First Search on Massive Graphs (2017) (31)
Power-optimal pipelining in deep submicron technology (2004) (31)
A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI (2017) (29)
AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement Learning (2020) (28)
Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures (2014) (28)
A Hardware Accelerator for Tracing Garbage Collection (2018) (28)
AutoPhase: Compiler Phase-Ordering for HLS with Deep Reinforcement Learning (2019) (27)
The RISC-V instruction set (2013) (27)
Load-sensitive flip-flop characterizations (2001) (27)
Strober: Fast and Accurate Sample-Based Energy Simulation for Arbitrary RTL (2016) (27)
Invited: Co-Design of Deep Neural Nets and Neural Net Accelerators for Embedded Vision Applications (2018) (26)
Fine-grain CAM-tag cache resizing using miss tags (2002) (25)
SCALABLE PROCESSORS IN THE BILLION-TRANSISTOR THE BILLION-TRANSISTOR ERA :IRAM (1997) (25)
Low Power Design (2008) (24)
A View on Deep Reinforcement Learning in System Optimization (2019) (23)
Heads and tails: a variable-length instruction format supporting parallel fetch and decode (2001) (23)
The PHiPAC v1.0 Matrix-Multiply Distribution (1998) (23)
GPUs as an opportunity for offloading garbage collection (2012) (21)
T0: A Single-Chip Vector Microprocessor with Reconfigurable Pipelines (1996) (20)
DIABLO: A Warehouse-Scale Computer Network Simulator using FPGAs (2015) (19)
Designing multi-socket systems using silicon photonics (2009) (19)
A speculative control scheme for an energy-efficient banked register file (2005) (19)
A Double-Pulsed Set-Conditional-Reset Flip-Flop (2002) (18)
Compiling for vector-thread architectures (2008) (18)
Torrent Architecture Manual (1997) (18)
Simmani: Runtime Power Modeling for Arbitrary RTL with Automatic Signal Selection (2019) (18)
Branch trace compression for snapshot-based simulation (2006) (17)
CNS-1 Architecture Specification (1993) (17)
The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V (2016) (16)
SPERT: a VLIW/SIMD microprocessor for artificial neural network computations (1992) (16)
A supercomputer for neural computation (1994) (16)
Genesis: A Hardware Acceleration Framework for Genomic Data Analysis (2020) (16)
Context-centric Security (2012) (16)
A Hardware Accelerator for Computing an Exact Dot Product (2017) (16)
FASED: FPGA-Accelerated Simulation and Evaluation of DRAM (2019) (16)
Using simulations of reduced precision arithmetic to design a neuro-microprocessor (1993) (16)
The RAMP Architecture & Description Language (2006) (16)
Multithreading decoupled architectures for complexity-effective general purpose computing (2001) (16)
Sanctorum: A lightweight security monitor for secure enclaves (2018) (16)
Evaluation of RISC-V RTL with FPGA-Accelerated Simulation (2017) (15)
BROOM: An Open-Source Out-of-Order Processor With Resilient Low-Voltage Operation in 28-nm CMOS (2019) (14)
SPERT-II: a vector microprocessor system and its application to large problems in backpropagation training (1995) (14)
Implementing the scale vector-thread processor (2008) (14)
DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of Cycles (2018) (13)
Hammer (2022) (13)
Implementing virtual memory in a vector processor with software restart markers (2006) (13)
SyCHOSys: Compiled Energy-Performance Cycle Simulation (2000) (13)
FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud (2019) (13)
Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking (2015) (12)
FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design (2020) (12)
Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC (2016) (12)
Vector Processors for Energy-Efficient Embedded Systems (2016) (12)
Keystone (2020) (11)
Manycore processor networks with monolithic integrated CMOS photonics (2009) (11)
A Hardware Accelerator for Protocol Buffers (2021) (11)
Hardware Works, Software Doesn't: Enforcing Modularity with Mondriaan Memory Protection (2003) (11)
Designing A Connectionist Network Supercomputer (1993) (11)
A Fast Kohonen Net Implementation for Spert-II (1997) (10)
Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes (2019) (10)
Return of the Runtimes: Rethinking the Language Runtime System for the Cloud 3.0 Era (2017) (10)
Generating the Next Wave of Custom Silicon (2018) (9)
Energy-exposed instruction sets (2002) (9)
Joint impact of random variations and RTN on dynamic writeability in 28nm bulk and FDSOI SRAM (2014) (9)
Re-architecting DRAM with Monolithically Integrated Silicon Photonics (2009) (8)
Energy-Exposed Instruction Set Architectures (2000) (8)
Direction-optimizing breadth-first search 1 (2014) (8)
Real-time Musical Applications on an Experimental Operating System for Multi-Core Processors (2011) (8)
Verifying RISC-V Physical Memory Protection (2022) (8)
Author retrospective for optimizing matrix multiply using PHiPAC: a portable high-performance ANSI C coding methodology (2014) (8)
A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI (2020) (8)
RLDRM: Closed Loop Dynamic Cache Allocation with Deep Reinforcement Learning for Network Function Virtualization (2020) (8)
Invited: Open-Source EDA Tools and IP, A View from the Trenches (2019) (7)
Evaluation of a 'stall' cache: an efficient restricted onchip instruction cache (1992) (7)
T0 Engineering Data (1997) (7)
Centrifuge: Evaluating full-system HLS-generated heterogenous-accelerator SoCs using FPGA-Acceleration (2019) (7)
GAIL: the graph algorithm iron law (2015) (7)
Grail Quest : A New Proposal for Hardware-assisted Garbage Collection (2016) (6)
A 16mm2 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET (2021) (6)
An FPGA Host-Multithreaded Functional Model for SPARC v 8 (2008) (6)
4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET (2021) (6)
SPERT: a VLIW/SIMD neuro-microprocessor (1992) (6)
Design-space exploration for CMOS photonic processor networks (2010) (5)
Guest Editors' Introduction: Hot Chips 21 (2010) (5)
Reprogrammable Redundancy for SRAM-Based Cache $V_{\min }$ Reduction in a 28-nm RISC-V Processor (2017) (5)
RingScalar: A Complexity-Effective Out-of-Order Superscalar Microarchitecture (2006) (5)
AutoPhase: Compiler Phase-Ordering for High Level Synthesis with Deep Reinforcement Learning (2019) (5)
Accelerating architectural exploration using canonical instruction segments (2006) (5)
MEMOCODE 2008 Co-Design Contest (2008) (5)
SPERT: a neuro-microprocessor (1995) (4)
Dynamically Resizable Static CMOS Logic for Fine-Grain Leakage (2004) (4)
The T0 Vector Microprocessor (2011) (4)
Hwacha Preliminary Evaluation Results , Version 3 . 8 (2015) (4)
Transactors for parallel hardware and software co-design (2007) (4)
Deep Reinforcement Learning in System Optimization (2019) (4)
An Energy-Efficient RISC-V RV32IMAC Microcontroller for Periodical-Driven Sensing Applications (2020) (3)
SPACE: symbolic processing in associative computing elements (1995) (3)
Hardware Transactional Memory (2004) (3)
Learning to Vectorize Using Deep Reinforcement Learning (2019) (3)
Microprocessor chip with photonic I/O (2017) (3)
An Out-of-Order RISC-V Processor with Resilient Low-Voltage Operation in 28NM CMOS (2018) (3)
Accelerating Genomic Data Analytics With Composable Hardware Acceleration Framework (2021) (3)
The RISC-V Compressed Instruction Set Manual Version 1 . 9 Warning ! (2015) (3)
The Case for Malleable Stream Architectures (2008) (3)
Full-System Simulation of Java Workloads with RISC-V and the Jikes Research Virtual Machine (2017) (3)
Versatile Tiled-Processor Architectures: The Raw Approach (2004) (3)
CMOS photonic processor-memory networks (2010) (3)
Scale Control Processor Test-Chip (2007) (3)
The Parallel Computing Laboratory at U . C . (2008) (3)
An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET (2022) (3)
Programmable Fine-Grained Power Management and System Analysis of RISC-V Vector Processors in 28-nm FD-SOI (2020) (2)
Accessible, FPGA Resource-Optimized Simulation of Multiclock Systems in FireSim (2021) (2)
Next Generation On-chip Communication Networks (2000) (2)
Debugging RISC-V Processors with FPGA-Accelerated RTL Simulation in the FPGA Cloud (2018) (2)
Vertically Integrated Computing Labs Using Open-Source Hardware Generators and Cloud-Hosted FPGAs (2021) (2)
Development of a Connectionist Network Supercomputer (1993) (2)
Big Chips (2011) (2)
Software-Based Off-Chip Memory Protection for RISC-V Trusted Execution Environments (2020) (2)
Tessellation operating system: Building a real-time, responsive, high-throughput client OS for many-core architectures (2011) (2)
Building an Adaptive Operating System for Predictability and Efficiency (2014) (2)
Spert-II: A Vector Microprocessor (1996) (2)
Limits and Opportunities for Designing Manycore Processor-to-Memory Networks using Monolithic Silicon Photonics (2009) (2)
Building Open Trusted Execution Environments (2020) (2)
Reprogrammable redundancy for cache Vmin reduction in a 28nm RISC-V processor (2016) (2)
The SCALE Architecture (2003) (1)
Computer Architecture and Design (2008) (1)
Reducing Instruction Cache Energy Using Gated Wordlines (2013) (1)
COBRA: A Framework for Evaluating Compositions of Hardware Branch Predictors (2021) (1)
FASED (2019) (1)
Future Systems (2020) (1)
Specialization for energy efficiency using agile development (2015) (1)
A Hardware Accelerator for Tracing Garbage Collection (2019) (1)
Design for MOSIS Educational Program ( Research ) Testchip for AHIP protocol , ASIC flow , and Leakage Control Through Body Biasing (1)
Invited: Chipyard - An Integrated SoC Research and Implementation Environment (2020) (1)
Vectorizing SPECint95 (1)
Hammer: a modular and reusable physical design flow tool: invited (2022) (1)
Photonic Many-Core Architecture Study (2008) (1)
Using FireSim to Enable Agile End-to-End RISC-V Computer Architecture Research (2019) (1)
Field-Programmable Gate Array (FPGA) Emulation for Computer Architecture (2009) (1)
Hardware Acceleration of Key-Value Stores (2014) (1)
Continual hashing for efficient fine-grain state inconsistency detection (2007) (1)
Simmani (2019) (1)
Measuring the gap between programmable and fixed-function accelerators: A case study on speech recognition (2013) (1)
Traditional Vector (2013) (0)
Evaluation of a Stall Cache: An Efficient Restricted On-chip (1991) (0)
Advantages of Silicon Photonics for Multi-socket Systems (2009) (0)
The Rocket Chip Generator Krste (2016) (0)
Fine-Grain Cache Resizing (2003) (0)
GitHub Version 0.0.1 (2020) (0)
DIABLO (2015) (0)
Cerberus (2022) (0)
CEDA currents: IEEE/ACM MEMOCODE Contest Update (2008) (0)
Die Photos ( 3 classes of cores ) A 45 nm 1 . 3 GHz 16 . 7 Double-Precision GFLOPS / W RISC-V Processor with Vector Accelerator (2017) (0)
Circuits for high-performance low-power vlsi logic (2006) (0)
MoCA: Memory-Centric, Adaptive Execution for Multi-Tenant Deep Neural Networks (2023) (0)
Circuit and architectural techniques for minimum-energy operation of SRAM-based caches (2016) (0)
Fine-Grain Dynamic Leakage Reduction (2003) (0)
PACE: Power-Aware Computing Engines (2005) (0)
Intel Sandy Bridge : IDF 2010 All on chip : 4 x 86 cores GPU North Bridge DRAM controller On chip ring network 2 (2010) (0)
The Heads and Tails Instruction Format (2003) (0)
Cyclist: Accelerating hardware development (2017) (0)
Banked Register Files for SMT Processors (0)
Spoken natural language understanding as a parallel application (1989) (0)
Banked Multiported Register File for Superscalar Microprocessors (2003) (0)
Fast Fourier Transform on a 3D FPGA (2006) (0)
Designing manycore processor networks using silicon photonics (2009) (0)
Simulation of Multi-Clock Systems in FireSim (2021) (0)
Power Density through Activity Migration (2003) (0)
Designing Multi-socket Systems Using Silicon Photonics 1 (2009) (0)
Lawrence Berkeley National Laboratory Recent Work Title Distributed-Memory Breadth-First Search on Massive Graphs Permalink (2017) (0)
Welcome from general chairs (2013) (0)
Accelerating General-Purpose Linear Algebra on DNN Accelerators (2022) (0)
The Maven vector-thread architecture (2011) (0)
A Low-Cost High-Capacity Associative Memory Design Using Cellular Automata (1995) (0)
Session details: Logic and microarchitecture (2005) (0)
Program committee (2018) (0)
Today ’ s lecture : More on power and energy Histogram filters Face detection Diffusion processing (2012) (0)
GENESIS: A COMPOSABLE HARDWARE ACCELERATION FRAMEWORK FOR GENOME ANALYSIS (2021) (0)
Analysis and Design of Manycore Processor-to-DRAM Opto-Electrical Networks with Integrated Silicon Photonics (2009) (0)
The Extreme Benchmark Suite: High-Performance Embedded Systems (2006) (0)
G.1 Why Vector Processors? G-2 (1998) (0)
6.823 Computer System Architecture, Spring 2002 (2002) (0)
System Integration of RISC-V Processors with FD-SOI (2020) (0)
Nested-Parallelism PageRank on RISC-V Vector MultiProcessors by Alon Amid Research Project (2019) (0)
Constellation: An Open-Source SoC-Capable NoC Generator (2022) (0)
Specialized versus general-purpose hardware (2011) (0)
Theme Feature Spert-II : A Vector Microprocessor System (1996) (0)
Instruction sets want to be free (2017) (0)
FirePerf (2020) (0)
The Par Lab Perspective on Computer Architecture (2013) (0)
Session details: Transactions and synchronization (2007) (0)
Mondriaan Memory Protection : Fine-Grained Protection with Translation (2003) (0)

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What Schools Are Affiliated With Krste Asanovic̀?

Krste Asanovic̀ is affiliated with the following schools:

Krste Asanovic̀'s Academic­Influence.com Rankings

Krste Asanovic̀'s Degrees

Why Is Krste Asanovic̀ Influential?

Krste Asanovic̀'s Published Works

Published Works

What Schools Are Affiliated With Krste Asanovic̀?

Krste Asanovic̀'s AcademicInfluence.com Rankings