Lizy John

Q: What Schools Are Affiliated With Lizy John

Lizy John is affiliated with the following schools: University of Texas at Austin, California Institute of Technology, Stanford University, Pennsylvania State University

Lizy John's AcademicInfluence.com Rankings

Lizy John

Engineering

#5457

World Rank

#6716

Historical Rank

Electrical Engineering

#2220

World Rank

#2326

Historical Rank

engineering Degrees

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Engineering

Lizy John's Degrees

Bachelors Electrical Engineering Stanford University
Masters Electrical Engineering Stanford University

Why Is Lizy John Influential?

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According to Wikipedia, Lizy Kurian John is an Indian American electrical engineer, who is currently the Cullen Trust for Higher Education Endowed Professor in the Department of Electrical and Computer Engineering at the University of Texas at Austin. She received her Ph.D. in computer engineering from The Pennsylvania State University in 1993. She joined The University of Texas Austin faculty in 1996. Her research is in the areas of computer architecture, multicore processors, memory systems, performance evaluation and benchmarking, workload characterization, and reconfigurable computing.

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Lizy John's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Scaling to the end of silicon with EDGE architectures (2004) (370)
Run-time modeling and estimation of operating system power consumption (2003) (260)
A novel low power energy recovery full adder cell (1999) (252)
Using complete machine simulation for software power estimation: the SoftWatt approach (2002) (234)
Complete System Power Estimation Using Processor Performance Events (2012) (214)
Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite (2007) (209)
Complete System Power Estimation: A Trickle-Down Approach Based on Performance Events (2007) (201)
Digital Systems Design Using VHDL (1998) (193)
Measuring Program Similarity: Experiments with SPEC CPU Benchmark Suites (2005) (171)
Performance prediction based on inherent program similarity (2006) (165)
Minimalist open-page: A DRAM page-mode scheduling policy for the many-core era (2011) (161)
Performance Evaluation and Benchmarking (2005) (149)
The virtual write queue: coordinating DRAM and last-level cache policies (2010) (139)
Efficient program scheduling for heterogeneous multi-core processors (2009) (134)
Measuring benchmark similarity using inherent program characteristics (2006) (134)
Control flow modeling in statistical simulation for accurate and efficient processor design studies (2004) (130)
Bottlenecks in Multimedia Processing with SIMD Style Extensions and Architectural Enhancements (2003) (114)
Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory (2010) (113)
Runtime identification of microprocessor energy saving opportunities (2005) (112)
Evaluating MMX technology using DSP and multimedia applications (1998) (105)
ESKIMO - energy savings using semantic knowledge of inconsequential memory occupancy for DRAM subsystem (2009) (98)
Is Compiling for Performance — Compiling for Power? (2001) (97)
Exploiting SIMD parallelism in DSP and multimedia algorithms using the AltiVec technology (1999) (91)
Improved automatic testcase synthesis for performance model validation (2005) (86)
Java Runtime Systems: Characterization and Architectural Implications (2001) (79)
Analysis of dynamic power management on multi-core processors (2008) (79)
Automated microprocessor stressmark generation (2008) (69)
Workload characterization: motivation, goals and methodology (1998) (69)
Architectural issues in Java runtime systems (2000) (66)
Wait of a Decade: Did SPEC CPU 2017 Broaden the Performance Horizon? (2018) (66)
AUDIT: Stress Testing the Automatic Way (2012) (66)
NpBench: a benchmark suite for control plane and data plane applications for network processors (2003) (64)
The future of simulation: a field of dreams (2006) (63)
Rethinking TLB designs in virtualized environments: A very large part-of-memory TLB (2017) (61)
Benchmarking Big Data Systems: A Review (2018) (61)
High-level synthesis of approximate hardware under joint precision and voltage scaling (2017) (60)
Performance characterization of SPEC CPU benchmarks on intel's core microarchitecture based processor (2007) (60)
Efficient Prediction of Network Traffic for Real-Time Applications (2019) (58)
Performance Cloning: A Technique for Disseminating Proprietary Applications as Benchmarks (2006) (58)
Using complete system simulation to characterize SPECjvm98 benchmarks (2000) (58)
Subsetting the SPEC CPU2006 benchmark suite (2007) (57)
Accurate phase-level cross-platform power and performance estimation (2016) (56)
Synthesizing memory-level parallelism aware miniature clones for SPEC CPU2006 and ImplantBench workloads (2010) (54)
Predictive coordination of multiple on-chip resources for chip multiprocessors (2011) (51)
Evaluating signal processing and multimedia applications on SIMD, VLIW and superscalar architectures (2000) (48)
More on finding a single number to indicate overall performance of a benchmark suite (2004) (48)
Modeling program resource demand using inherent program characteristics (2011) (43)
Distilling the essence of proprietary workloads into miniature benchmarks (2008) (43)
Characterization of Java applications at bytecode and ultra-SPARC machine code levels (1999) (42)
The Role of Return Value Prediction in Exploiting Speculative Method-Level Parallelism (2003) (41)
Allowing for ILP in an embedded Java processor (2000) (39)
BLRL: Accurate and Efficient Warmup for Sampled Processor Simulation (2005) (39)
A bandwidth-aware memory-subsystem resource management using non-invasive resource profilers for large CMP systems (2010) (39)
Data partitioning strategies for graph workloads on heterogeneous clusters (2015) (39)
Improving dynamic cluster assignment for clustered trace cache processors (2003) (38)
System-level Max POwer (SYMPO) - a systematic approach for escalating system-level power consumption using synthetic benchmarks (2010) (37)
Memory Latency Effects in Decoupled Architectures (1994) (37)
A first-order mechanistic model for architectural vulnerability factor (2012) (37)
Evaluating Benchmark Subsetting Approaches (2006) (37)
Understanding and improving operating system effects in control flow prediction (2002) (36)
Bank-aware Dynamic Cache Partitioning for Multicore Architectures (2009) (35)
The Return of Synthetic Benchmarks (2008) (35)
Design and performance evaluation of a cache assist to implement selective caching (1997) (35)
Workload characterization of multithreaded java servers (2001) (35)
Simulation points for SPEC CPU 2006 (2008) (34)
Cost-effective hardware acceleration of multimedia applications (2001) (34)
AVF Stressmark: Towards an Automated Methodology for Bounding the Worst-Case Vulnerability to Soft Errors (2010) (33)
Program balance and its impact on high performance RISC architectures (1995) (32)
Automatic Generation of Miniaturized Synthetic Proxies for Target Applications to Efficiently Design Multicore Processors (2014) (31)
Automated di/dt stressmark generation for microprocessor power delivery networks (2011) (30)
Effective Use of Performance Monitoring Counters for Run-Time Prediction of Power (2004) (30)
MAximum Multicore POwer (MAMPO) — An automatic multithreaded synthetic power virus generation framework for multicore systems (2011) (29)
Improving Java performance using hardware translation (2001) (29)
Learning-based analytical cross-platform performance prediction (2015) (29)
Latency and energy aware value prediction for high-frequency processors (2002) (29)
Store-Load-Branch (SLB) predictor: A compiler assisted branch prediction for data dependent branches (2013) (28)
Performance impact of virtual machine placement in a datacenter (2012) (28)
Cache Friendliness-Aware Managementof Shared Last-Level Caches for HighPerformance Multi-Core Systems (2014) (27)
PowerTrain: A learning-based calibration of McPAT power models (2015) (27)
Self-monitored adaptive cache warm-up for microprocessor simulation (2004) (27)
Statistical quality modeling of approximate hardware (2016) (26)
Predictive power management for multi-core processors (2010) (25)
CSALT: Context Switch Aware Large TLB* (2017) (25)
Start Late or Finish Early: A Distributed Graph Processing System with Redundancy Reduction (2018) (25)
A Performance Counter Based Workload Characterization on Blue Gene/P (2008) (24)
Energy-aware application scheduling on a heterogeneous multi-core system (2008) (22)
Execution characteristics of multimedia applications on a Pentium II processor (2000) (22)
SILC-FM: Subblocked InterLeaved Cache-Like Flat Memory Organization (2016) (22)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2018) (21)
Accurately modeling speculative instruction fetching in trace-driven simulation (1999) (20)
Value Based BTB Indexing for indirect jump prediction (2010) (20)
Efficiently Evaluating Speedup Using Sampled Processor Simulation (2004) (20)
Memory Latency Effects in Decoupled Architectures with a Single Data Memory Module (1992) (19)
Evaluating the efficacy of statistical simulation for design space exploration (2006) (19)
Archer: A Community Distributed Computing Infrastructure for Computer Architecture Research and Education (2008) (19)
GPGPU-MiniBench: Accelerating GPGPU Micro-Architecture Simulation (2015) (19)
On load latency in low-power caches (2003) (19)
Dynamic power and performance back-annotation for fast and accurate functional hardware simulation (2015) (19)
Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue (2011) (19)
Generation, Validation and Analysis of SPEC CPU2006 Simulation Points Based on Branch, Memory and TLB Characteristics (2009) (19)
Performance Evaluation : Techniques , Tools and Benchmarks (2004) (19)
Benchmarking Internet Servers on Superscalar Machines (2003) (19)
Automatic testcase synthesis and performance model validation for high performance PowerPC processors (2006) (19)
Proxy Benchmarks for Emerging Big-Data Workloads (2017) (19)
Proxy-Guided Load Balancing of Graph Processing Workloads on Heterogeneous Clusters (2016) (18)
Execution characteristics of object oriented programs on the UltraSPARC-II (1998) (18)
Data analytics workloads: Characterization and similarity analysis (2014) (18)
Locality-based online trace compression (2004) (18)
Learning-based power modeling of system-level black-box IPs (2015) (17)
A Tale of Two Processors: Revisiting the RISC-CISC Debate (2009) (17)
Source-Level Performance, Energy, Reliability, Power and Thermal (PERPT) Simulation (2017) (17)
Performance model for a prioritized multiple-bus multiprocessor system (1994) (16)
Adapting branch-target buffer to improve the target predictability of java code (2005) (16)
GPU Triggered Networking for Intra-KerneI Communications (2017) (16)
Deconstructing and Improving Statistical Simulation in HLS (2004) (15)
Effective adaptive computing environment management via dynamic optimization (2005) (15)
Exploiting compiler-generated schedules for energy savings in high-performance processors (2003) (14)
Power and performance analysis of network traffic prediction techniques (2012) (14)
Performance Characterization of Modern Databases on Out-of-Order CPUs (2015) (14)
Efficient traffic aware power management for multicore communications processors (2012) (14)
On the representativeness of embedded Java benchmarks (2008) (14)
Performance prediction using program similarity (2006) (13)
Efficient power analysis using synthetic testcases (2005) (13)
Understanding control flow transfer and its predictability in java processing (2001) (13)
Core-Level Activity Prediction for Multicore Power Management (2011) (12)
The Case for Automatic Synthesis of Miniature Benchmarks (2005) (12)
MediaBreeze: a decoupled architecture for accelerating multimedia applications (2001) (12)
Modeling program resource demand using inherent program characteristics (2011) (12)
Effective management of multiple configurable units using dynamic optimization (2006) (11)
Hamamu: Specializing FPGAs for ML Applications by Adding Hard Matrix Multiplier Blocks (2020) (11)
Implications of programmable general purpose processors for compression/encryption applications (2002) (11)
FOUR GENERATIONS OF SPEC CPU BENCHMARKS : WHAT HAS CHANGED AND WHAT HAS NOT (2004) (11)
Performance boosting under reliability and power constraints (2013) (11)
Statistical pattern based modeling of GPU memory access streams (2017) (11)
Exploring Heterogeneous-ISA Core Architectures for High-Performance and Energy-Efficient Mobile SoCs (2017) (11)
A dynamically reconfigurable interconnect for array processors (1998) (10)
Can we trust profiling results?: understanding and fixing the inaccuracy in modern profilers (2019) (10)
Neuro-Symbolic AI: An Emerging Class of AI Workloads and their Characterization (2021) (10)
Classification and performance evaluation of instruction buffering techniques (1991) (10)
BigDataBench-MT: A Benchmark Tool for Generating Realistic Mixed Data Center Workloads (2015) (10)
Architectural enhancements for network congestion control applications (2006) (10)
Microarchitectural techniques to enable efficient java execution (2000) (10)
Workload Characterization for Computer System Design (2000) (10)
Confusion by All Means (2006) (10)
LACross: Learning-Based Analytical Cross-Platform Performance and Power Prediction (2017) (10)
Accelerating GPGPU architecture simulation (2013) (10)
Watt Watcher: Fine-Grained Power Estimation for Emerging Workloads (2015) (10)
Tensor Slices to the Rescue: Supercharging ML Acceleration on FPGAs (2021) (10)
Prefetching Techniques for Near-memory Throughput Processors (2016) (10)
Prefetching for cloud workloads: An analysis based on address patterns (2017) (10)
Understanding the impact of X86/NT computing on microarchitecture (2001) (10)
Design Space Exploration for Softmax Implementations (2020) (9)
Operating system power minimization through run-time processor resource adaptation (2006) (9)
Rehashable BTB: An Adaptive Branch Target Buffer to Improve the Target Predictability of Java Code (2002) (9)
Accurate address streams for LLC and beyond (SLAB): A methodology to enable system exploration (2017) (9)
ADir_pNB: A Cost-Effective Way to Implement Full Map Directory-Based Cache Coherence Protocols (2001) (9)
Measuring program similarity for efficient benchmarking and performance analysis of computer systems (2007) (9)
Routine based OS-aware microprocessor resource adaptation for run-time operating system power saving (2003) (9)
Analyzing and improving clustering based sampling for microprocessor simulation (2005) (9)
Low-power, low-complexity instruction issue using compiler assistance (2005) (9)
TSS: Applying two-stage sampling in micro-architecture simulations (2009) (8)
Avoiding store misses to fully modified cache blocks (2006) (8)
Module Partitioning and Interlaced Data Placement Schemes to Reduce Conflicts in Interleaved Memories (1994) (8)
Demystifying the MLPerf Benchmark Suite (2019) (8)
Measuring Program Similarity (2005) (8)
Performance Evaluation and Benchmarking of Native Signal Processing (1999) (8)
A Case for Granularity Aware Page Migration (2018) (8)
GPGPU Benchmark Suites: How Well Do They Sample the Performance Spectrum? (2015) (8)
Extended Task Queuing: Active Messages for Heterogeneous Systems (2016) (8)
Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research (2021) (7)
Issues in the design of store buffers in dynamically scheduled processors (2000) (7)
Workload Characterization of Emerging Computer Applications (2001) (7)
Formal verification of a snoop-based cache coherence protocol using symbolic model checking (1999) (7)
Impact of virtual execution environments on processor energy consumption and hardware adaptation (2006) (7)
Host-Compiled Reliability Modeling for Fast Estimation of Architectural Vulnerabilities (2015) (7)
Power Phase Variation in a Commercial Server Workload (2006) (7)
Sampling-based binary-level cross-platform performance estimation (2017) (7)
Constructing adaptable and scalable synthetic benchmarks for microprocessor performance evaluation (2007) (7)
A novel memory bus driver/receiver architecture for higher throughput (1998) (7)
BUQS: Battery- and user-aware QoS scaling for interactive mobile devices (2018) (7)
HALO: A Hierarchical Memory Access Locality Modeling Technique For Memory System Explorations (2018) (6)
CantorSim: Simplifying Acceleration of Micro-architecture Simulations (2010) (6)
VaWiRAM: a variable width random access memory module (1996) (6)
Contrasting branch characteristics and branch predictor performance of C++ and C programs (1999) (6)
Characterization of MMX-enhanced DSP and Multimedia Applications on a General Purpose Processor (1998) (6)
Workload Characterization of Java Server Applications on Two PowerPC Processors (2002) (6)
Mechanistic Modeling of Architectural Vulnerability Factor (2015) (6)
Demystifying the MLPerf Training Benchmark Suite (2020) (6)
Invited Paper for the Hot Workloads Special Session Hot Regions in SPEC CPU2017 (2018) (6)
FastSpot: Host-compiled thermal estimation for early design space exploration (2014) (6)
SMA: A Self-Monitored Adaptive Cache Warm-Up Scheme for Microprocessor Simulation (2005) (6)
A comparative evaluation of software techniques to hide memory latency (1995) (6)
Fine-grained power analysis of emerging graph processing workloads for cloud operations management (2016) (6)
CAMP: Accurate modeling of core and memory locality for proxy generation of big-data applications (2018) (5)
Cloud-Guided QoS and Energy Management for Mobile Interactive Web Applications (2017) (5)
Flow Migration on Multicore Network Processors: Load Balancing While Minimizing Packet Reordering (2013) (5)
Reducing server data traffic using a hierarchical computation model (2005) (5)
Predictive Heterogeneity-Aware Application Scheduling for Chip Multiprocessors (2014) (5)
i-MIRROR: A Software Managed Die-Stacked DRAM-Based Memory Subsystem (2015) (5)
Improving Transaction Processing using a Hierarchical Computing Server (2002) (5)
Simulator calibration for accelerator-rich architecture studies (2016) (5)
A Performance Study of Modern Web Server Applications (1999) (5)
Dynamic Core Allocation and Packet Scheduling in Multicore Network Processors (2016) (5)
Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures (2008) (4)
Genesys: Automatically generating representative training sets for predictive benchmarking (2016) (4)
Access time and energy tradeoffs for caches in high frequency microprocessors (2002) (4)
Investigating the Effectiveness of a Third Level Cache (1998) (4)
Simulating commercial Java throughput workloads: a case study (2005) (4)
An Evolutionary Computation Embedded IIR LMS Algorithm (1999) (4)
Value Prediction Design for High-Frequency Microprocessors (2002) (4)
SelSMaP: A Selective Stride Masking Prefetching Scheme (2017) (4)
OS-aware tuning: improving instruction cache energy efficiency on system workloads (2006) (4)
MCFQ: Leveraging Memory-level Parallelism and Application's Cache Friendliness for Efficient Management of Quasi-partitioned Last-level Caches (2011) (4)
Characterizing operating system activity in SPECjvm98 Benchmarks (2001) (4)
Hybrid tree: a scalable optoelectronic interconnection network for parallel computing (1998) (4)
Automatic workload synthesis for early design studies and performance model validation (2005) (4)
Exploring the Application Behavior Space Using Parameterized Synthetic Benchmarks (2007) (3)
Annex cache: a cache assist to implement selective caching (1999) (3)
Simulating Java Commercial Throughput Workload : A Case Study (2005) (3)
Program Chair's Message (2004) (3)
Applying Statistical Sampling for Fast and Efficient Simulation of Commercial Workloads (2007) (3)
Hardware Support to Reduce Overhead in Fine-Grain Media Codes (2001) (3)
On the Object Orientedness of C + + programs in SPEC CPU 2006 (3)
Modeling and evaluation of control flow prediction schemes using complete system simulation and Java workloads (2002) (3)
CMP/CMT Scaling of SPECjbb2005 on UltraSPARC T1 (2005) (3)
OS-Aware Branch Prediction: Improving Microprocessor Control Flow Prediction for Operating Systems (2007) (3)
Cache Capacity and Memory Bandwidth Scaling Limits of Highly Threaded Processors (3)
Architectural support for accelerating congestion control applications in network processors (2005) (3)
Workload Characterization: Methodology and Case Studies. Based on the First Workshop on Workload Characterization (1998) (3)
Power Modeling of SDRAMs (2004) (3)
Less is More : Leveraging Belady ’ s Algorithm with Demand-based Learning (2017) (3)
Tera-Op Reliable Intelligently Adaptive Processing System (TRIPS) (2004) (3)
Modeling and analysis of the difference-bit cache (1998) (3)
Accelerating Force-directed Graph Layout with Processing-in-Memory Architecture (2020) (3)
Implications of executing compression and encryption applications on general purpose processors (2005) (3)
Workload Synthesis for a Communications SoC (2011) (3)
Exploring Opportunities for Heterogeneous-ISA Core Architectures in High-Performance Mobile SoCs (2017) (3)
CoMeFa: Compute-in-Memory Blocks for FPGAs (2022) (2)
Optimizing GPGPU Kernel Summation for Performance and Energy Efficiency (2016) (2)
Reducing Data Movement and Energy in Multilevel Cache Hierarchies without Losing Performance: Can you have it all? (2019) (2)
Aggregating Performance Metrics Over a Benchmark Suite (2018) (2)
Improving CNN performance on FPGA clusters through topology exploration (2021) (2)
Thermal-Aware Design Space Exploration of 3-D Systolic ML Accelerators (2021) (2)
Effect of Hot Spots on Multiprocessor Systems Using Circuit Switched Interconnection Networks (1991) (2)
A Study of Core Utilization and Residency in Heterogeneous Smart Phone Architectures (2019) (2)
Virtual-Link: A Scalable Multi-Producer Multi-Consumer Message Queue Architecture for Cross-Core Communication (2020) (2)
Basic Block Simulation Granularity, Basic Block Maps, and Benchmark Synthesis Using Statistical Simulation (2003) (2)
Cluster Assignment Strategies for a Clustered Trace Cache Processor (2003) (2)
Automating Stressmark Generation for Testing Processor Voltage Fluctuations (2013) (2)
- 1-Mapping of Applications to Heterogeneous Multi-cores Based on Microarchitecture Independent Characteristics (2007) (2)
Improving server performance on transaction processing workloads by enhanced data placement (2004) (2)
Design of a highly reconfigurable interconnect for array processors (1995) (2)
Proprietary code to non-proprietary benchmarks: synthesis techniques for scalable benchmarks (2011) (2)
ComP-net: command processor networking for efficient intra-kernel communications on GPUs (2018) (2)
Identifying performance bottlenecks in Hive: Use of processor counters (2016) (2)
Wave-PIM: Accelerating Wave Simulation Using Processing-in-Memory (2021) (2)
Loop-Aware Instruction Scheduling with Dynamic Contention Tracking for Tiled Dataflow Architectures (2009) (1)
Infinity Stream: Portable and Programmer-Friendly In-/Near-Memory Fusion (2023) (1)
Hardware Efficient Piecewise Linear Branch Predictor (2007) (1)
Puzzle Memory: Multifractional Partitioned Heterogeneous Memory Scheme (2018) (1)
Memristor-Based Computing (2018) (1)
Machine learning for performance and power modeling/prediction (2017) (1)
Hardware Acceleration for Media/Transaction Applications in Network Processors (2009) (1)
Agile Hardware Design (2020) (1)
Hierarchically characterizing CUDA program behavior (2011) (1)
A Decoupled Architecture for Accelerating Multimedia Applications (2001) (1)
On the use of pseudorandom sequences for high speed resource allocators in superscalar processors (1999) (1)
SimTrace: Capturing over Time Program Phase Behavior (2020) (1)
Performance Modeling and Measurement Techniques (2005) (1)
Compiler Support for Value-Based Indirect Branch Prediction (2012) (1)
On sampling unit size in sampled microprocessor simulation (2005) (1)
GAPS: GPU-acceleration of PDE solvers for wave simulation (2022) (1)
A Case Study of 3 Internet Benchmarks on 3 Superscalar Machines (2001) (1)
Hybrid-Scheduling for Reduced Energy Consumption in High-Performance Processors (2006) (1)
Wor kload Character ization of M ultithreaded Java Servers (2001) (1)
Connectivity! Connectivity! Connectivity! May You Be More Connected Than Ever!! (2020) (1)
Performance evaluation of configurable hardware features on the AMD-K5 (1999) (1)
Hardware Accelerator Integration Tradeoffs for High-Performance Computing: A Case Study of GEMM Acceleration in N-Body Methods (2021) (1)
Performance analysis of HPC applications with irregular tree data structures (2014) (1)
Branch Behavior of Java Runtime Systems and its Microarchitectural Implications (2000) (1)
Rethinking TLB Designs in Virtualized Environments (2017) (1)
Using Statistical Theory to Study Issues in Microprocessor Simulation (2004) (1)
Performance Impact of NVMe-Over-TCP on HDFS Workloads (2022) (0)
Performance of Java in Function-as-a-Service Computing (2022) (0)
EfficientPredictionofNetworkTraffic forReal-TimeApplications (2019) (0)
Special Issue on Cool Chips and Hot Interconnects (2022) (0)
To the Era of Intelligent Chips and Systems (2019) (0)
Quantum Computing and More! (2021) (0)
Capturing the Essence of Benchmarks : A New Approach to Benchmark Synthesis (2005) (0)
Hot Chips 33 and More! (2022) (0)
Did ML Chips Heat Up the Chip Design Arena? (2020) (0)
Emerging System Interconnects Enabling More Opportunities Than Ever! (2023) (0)
Design and VLSI implementation of an access processor for a decoupled architecture (1992) (0)
HALO (2018) (0)
CPUs, GPUs, and More From Hot Chips'32 (2021) (0)
Microprocessor at 50: A Time to Celebrate and Energize for the Future (2021) (0)
The Case for Hard Matrix Multiplier Blocks in an FPGA (2020) (0)
Understanding and Designing for Dependent Store/Load Pairs in High Performance Microprocessors (2000) (0)
Bit-Slice Computers (1999) (0)
Improving the parallelism and concurrency in decoupled architectures (1996) (0)
EMBEDDED SIGNAL PROCESSING ON MICROCONTROLLERS APPROVED BY SUPERVISING COMMITTEE: (1998) (0)
Stressing Microarchitectures Through Custom Benchmark Synthesis (2008) (0)
Top Picks from 2021 Computer Architecture Conferences! (2022) (0)
Investigating the Use of Cache as a Local Memory (2007) (0)
Performance Monitoring on the POWER5™ Microprocessor (2018) (0)
Intel Wins in Four Decades, but AMD Catches Up (2021) (0)
Automatically Selecting Representative Traces for Simulation Based on Cluster Analysis of Instruction Address Hashes (2004) (0)
Enhanced Hierarchical Instruction Scheduling For Tiled Dataflow Architectures (0)
Automatic Compilation Will Be Key for Success of the Accelerator Revolution! (2022) (0)
From the Memory Lane! (2021) (0)
Artificial Intelligence at the Edge: Designs and Architectures for Pervasive Intelligence (2022) (0)
HRM: H-tree based reconfiguration mechanism in reconfigurable homogeneous PE array (2020) (0)
Weightless Neural Networks for Efficient Edge Inference (2022) (0)
Enjoy These Top Picks, While You Work From Home! (2020) (0)
Exploiting Instruction Reuse to Enhance Microprocessor Simulation (1999) (0)
Automated di / dt Stressmark Generation for Microprocessor Power Distribution Networks (2012) (0)
Memory Chips with Adjustable Configurations (1999) (0)
SPAMeR: Speculative Push for Anticipated Message Requests in Multi-Core Systems (2022) (0)
Koios 2.0: Open-Source Deep Learning Benchmarks for FPGA Architecture and CAD Research (2023) (0)
Machine Learning for Systems, Biological Computing, and More (2020) (0)
1 Archer : A Community Distributed Computing Infrastructure for Computer Architecture Research and Education (2008) (0)
Microarchitectural Performance Evaluation of AV1 Video Encoding Workloads (2022) (0)
Improving Branch Predictability in Java Processing (2001) (0)
Microprocessor at 50: Looking Back and Looking Forward (2021) (0)
Improving Java Performance in Embedded and General-Purpose Processors (2002) (0)
Smart Agriculture and Smart Memories (2022) (0)
SelSMaP (2018) (0)
Letter from the general chairs (2015) (0)
POWSER: A novel user-experience based power management metric (2017) (0)
GAPS (2022) (0)
HLSDataset: Open-Source Dataset for ML-Assisted FPGA Design using High Level Synthesis (2023) (0)
ATTC (@C): Addressable-TLB based Translation Coherence (2020) (0)
Chip Design 2020 (2020) (0)
Characterization of Web Server Workloads on Three Generations of IBM PowerPC Microarchitectures (2000) (0)
Tensor Slices: FPGA Building Blocks For The Deep Learning Era (2022) (0)
Compute RAMs: Adaptable Compute and Storage Blocks for DL-Optimized FPGAs (2021) (0)
THE EASE BRANCH PREDICTOR (2000) (0)
Capturing Locality of Reference and Branch Predictability of Programs in Synthetic Workloads (2006) (0)
L G ] 2 4 A ug 2 01 9 Demystifying the MLPerf Benchmark Suite (2019) (0)
Secure Architectures (2019) (0)
Measurement-based Power Phase Analysis (2007) (0)
MathRAMs (2022) (0)
A High-throughput Self-timed Fpga Core Architecture (2007) (0)
Performance Model for ized Mu It i ple-Bus Mu It i proce (1996) (0)
The effects of memory-access ordering on multiple-issue uniprocessor performance (1999) (0)
Emerging Hot Chips and Systems (2019) (0)
Hardware-aware 3D Model Workload Selection and Characterization for Graphics and ML Applications (2022) (0)
Analysis of the execution of a next generation application on superscalar and grid processors (2004) (0)
Top Picks (2019) (0)
FPGA Computing and More! (2021) (0)
Characterization of Smartphone Governor Strategies (2018) (0)
MathRAMs: Configurable Fused Compute-Memory Blocks for FPGAs (2022) (0)
An FPGA-Based Weightless Neural Network for Edge Network Intrusion Detection (2023) (0)
Front-End Bound L 1 Bound L 2 Bound L 3 Bound DRAM Bound Others Retiring (2018) (0)
3-D Chips! Chips are Getting Denser and Taller Than Ever!! (2019) (0)
Fine-Grain Program Snippets Generator for Mobile Core Design (2017) (0)
Autocorrelation analysis: a new and improved method for measuring branch predictability (2011) (0)
LAWS: Large-Scale Accelerated Wave Simulations on FPGAs (2023) (0)
Demystifying graph processing frameworks and benchmarks (2020) (0)
Control flow behavior of cloud workloads (2014) (0)
Top Picks From Year 2020 (2021) (0)
Interface design techniques for single-chip systems (2003) (0)
Machine Learning Accelerators and More (2019) (0)
Impact of compiler optimizations on voltage droops and reliability of an SMT, multi-core processor (2012) (0)
The undergraduate curriculum in the electrical and computer engineering department at the University of Texas at Austin (1998) (0)
ULEEN: A Novel Architecture for Ultra Low-Energy Edge Neural Networks (2023) (0)
Traveling Speculations: An Integrated Prediction Strategy for Wide-Issue Microprocessors (2002) (0)
Connectivity - More Needed Than Ever Before (2021) (0)
LogicWiSARD: Memoryless Synthesis of Weightless Neural Networks (2022) (0)
LogGen: A Parameterized Generator for Designing Floating-Point Logarithm Units for Deep Learning (2022) (0)
Autocorrelation analysis: A new and improved method for branch predictability characterization (2011) (0)
Program Committee for International Workshop on High-Performance Big Data Computing (HPBDC 2015) (2015) (0)
Introduction to Analytical Models (2018) (0)
Exploring the potential of a hierarchical computing model for a commercial server (2004) (0)
WattWatcher : Fine-Grained Power Estimation on Live Multicore Systems Using Configurable Models (2015) (0)
Microprocessor at 50: Industry Leaders Speak (2021) (0)
Embedded Java benchmark analysis on the ARM processor (2009) (0)
Demystifying graph processing frameworks and benchmarks (2020) (0)
Environmentally Sustainable Computing (2023) (0)
LACross: Learning-Based Analytical Cross-Platform Performance and Power Prediction (2017) (0)

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