M. Jagadesh Kumar
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Indian academician
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M. Jagadesh Kumarengineering Degrees
Engineering
#1295
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#1941
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Electrical Engineering
#312
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#353
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Applied Physics
#3250
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#3334
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Engineering
M. Jagadesh Kumar's Degrees
- Bachelors Electrical Engineering IIT Madras
- Masters Electrical Engineering IIT Delhi
Why Is M. Jagadesh Kumar Influential?
(Suggest an Edit or Addition)According to Wikipedia, Mamidala Jagadesh Kumar is an Indian academician, electrical engineer, education administrator. He is currently the chairman of University Grants Commission, since February 2022. He is a professor in the Department of Electrical Engineering at IIT Delhi. Kumar also served as the VC of JNU from in January 2016 to 2022.
M. Jagadesh Kumar's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- Doping-Less Tunnel Field Effect Transistor: Design and Investigation (2013) (471)
- Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field-Effect Transistor (2011) (375)
- Controlling Ambipolar Current in Tunneling FETs Using Overlapping Gate-on-Drain (2014) (244)
- Bipolar Charge-Plasma Transistor: A Novel Three Terminal Device (2012) (190)
- Impact of Strain on Drain Current and Threshold Voltage of Nanoscale Double Gate Tunnel Field Effect Transistor: Theoretical Investigation and Analysis (2009) (127)
- Compact Analytical Model of Dual Material Gate Tunneling Field-Effect Transistor Using Interband Tunneling and Channel Transport (2014) (111)
- Dielectric-Modulated Impact-Ionization MOS Transistor as a Label-Free Biosensor (2013) (100)
- Compact Analytical Drain Current Model of Gate-All-Around Nanowire Tunneling FET (2014) (87)
- Dielectric modulated overlapping gate-on-drain tunnel-FET as a label-free biosensor (2015) (69)
- A Pseudo-2-D-Analytical Model of Dual Material Gate All-Around Nanowire Tunneling FET (2014) (66)
- Estimation and Compensation of Process-Induced Variations in Nanoscale Tunnel Field-Effect Transistors for Improved Reliability (2010) (62)
- Extended-$\hbox{p}^{+}$ Stepped Gate LDMOS for Improved Performance (2010) (49)
- Schottky Collector Bipolar Transistor Without Impurity Doped Emitter and Base: Design and Performance (2013) (47)
- A full-range dual material gate tunnel field effect transistor drain current model considering both source and drain depletion region band-to-band tunneling (2015) (42)
- Vertical Bipolar Charge Plasma Transistor with Buried Metal Layer (2015) (41)
- Extended-p + Stepped Gate LDMOS for Improved Performance (2010) (38)
- 2-D Analytical Model for the Threshold Voltage of a Tunneling FET With Localized Charges (2014) (38)
- Thin-Film Bipolar Transistors on Recrystallized Polycrystalline Silicon Without Impurity Doped Junctions: Proposal and Investigation (2014) (35)
- PNPN tunnel FET with controllable drain side tunnel barrier width: Proposal and analysis (2015) (29)
- Collector design tradeoffs for low voltage applications of advanced bipolar transistors (1993) (29)
- Molecular diodes and applications. (2007) (28)
- Improving the breakdown voltage, ON-resistance and gate-charge of InGaAs LDMOS power transistors (2012) (27)
- Effect of the Ge mole fraction on the formation of a conduction path in cylindrical strained-silicon-on-SiGe MOSFETs (2008) (27)
- A new 4H-SiC lateral merged double Schottky (LMDS) rectifier with excellent forward and reverse characteristics (2001) (26)
- QUANTUM CONFINEMENT EFFECTS IN STRAINED SILICON MOSFETS (2008) (26)
- Analytical drain current model for nanoscale strained‐Si/SiGe MOSFETs (2009) (24)
- Nanoscale SOI MOSFETs with electrically induced source/drain extension: Novel attributes and design considerations for suppressed short-channel effects (2006) (23)
- A new lateral PNM Schottky collector bipolar transistor (SCBT) on SOI for nonsaturating VLSI logic design (2002) (22)
- A new symmetrical double gate nanoscale MOSFET with asymmetrical side gates for electrically induced source/drain (2006) (22)
- Impact of gate leakage considerations in tunnel field effect transistor design (2014) (22)
- Linearity and speed optimization in SOI LDMOS using gate engineering (2009) (21)
- Polysilicon Spacer Gate Technique to Reduce Gate Charge of a Trench Power MOSFET (2012) (20)
- Trench Gate Power MOSFET: Recent Advances and Innovations (2012) (19)
- Recessed source concept in nanoscale vertical surrounding gate (VSG) MOSFETs for controlling short-channel effects (2009) (18)
- 3D Simulation of Nanowire FETs using Quantum Models (2010) (17)
- Study of the extended p/sup +/ dual source structure for eliminating bipolar induced breakdown in submicron SOI MOSFET's (2000) (15)
- Estimation and Compensation of Process Induced Variations in Nanoscale Tunnel Field Effect Transistors (TFETs) for Improved Reliability (2010) (14)
- Investigation of laterally single-diffused metal oxide semiconductor (LSMOS) field effect transistor (2015) (13)
- Comprehensive approach to modeling threshold voltage of nanoscale strained silicon SOI MOSFETs (2007) (12)
- Drain current model for SOI TFET considering source and drain side tunneling (2014) (11)
- The effects of emitter region recombination and bandgap narrowing on the current gain and the collector lifetime of high-voltage bipolar transistors (1989) (11)
- A novel Doping-less Bipolar Transistor with Schottky Collector (2011) (10)
- Collector recombination lifetime from the quasi-saturation analysis of high-voltage bipolar transistors (1990) (10)
- Realising wide bandgap P-SiC-emitter lateral heterojunction bipolar transistors with low collector-emitter offset voltage and high current gain: a novel proposal using numerical simulation (2004) (9)
- Proposal and design of a new SiC-emitter lateral NPM Schottky collector bipolar transistor on SOI for VLSI applications (2004) (9)
- A new low-loss lateral trench sidewall Schottky (LTSS) rectifier on SOI with high and sharp breakdown voltage (2002) (9)
- Novel lateral merged double Schottky (LMDS) rectifier: proposal and design (2001) (9)
- Realizing high‐voltage thin film lateral bipolar transistors on SOI with a collector‐tub (2005) (9)
- Special Issue on Nanowire Transistors: Modeling, Device Design, and Technology (2008) (9)
- A new, high-voltage 4H-SiC lateral dual sidewall Schottky (LDSS) rectifier: theoretical investigation and analysis (2003) (8)
- Design tradeoffs for improved V/sub CE(sat/) versus I/sub C/ of bipolar transistors under forced gain conditions (1994) (8)
- Compact Modeling of Partially Depleted Silicon-on-Insulator Drain-Extended MOSFET (DEMOSFET) Including High-Voltage and Floating-Body Effects (2011) (8)
- Lateral thin-film Schottky (LTFS) rectifier on SOI: a device with higher than plane parallel breakdown voltage (2002) (8)
- A Novel Cascade-Free 5-V ESD Clamp Using I-MOS: Proposal and Analysis (2016) (7)
- Enhanced current gain in SiC power BJTs using a novel surface accumulation layer transistor concept (2005) (6)
- Miller's approximation in advanced bipolar transistors under nonlocal impact ionization conditions (1994) (6)
- Realising high-current gain p-n-p transistors using a novel surface accumulation layer transistor (SALTran) concept (2005) (4)
- Controlling the ON-resistance in SOI LDMOS using parasitic bipolar junction transistor (2014) (4)
- Guest Editorial Special Issue on Nanowire Transistors: Modeling, Device Design, and Technology (2008) (4)
- A Drain-side Gate-underlap I-MOS (DGI-MOS) transistor as a label-free biosensor for detection of charged biomolecules (2014) (3)
- Schottky bipolar I-MOS: An I-MOS with Schottky electrodes and an open-base BJT configuration for reduced operating voltage (2017) (3)
- A new SiGe Stepped Gate (SSG) Thin Film SOI LDMOS for enhanced breakdown voltage and reduced delay (2009) (3)
- Optimum collector EPI-thickness of advanced bipolar transistors for high speed and high current operation (1994) (3)
- Charge Plasma High Voltage PIN Diode Investigation (2018) (2)
- Design of New Low Power – Area Efficient Static Flip-Flops (2014) (2)
- Realizing Wide Bandgap P-SiC-emitter Lateral Heterojunction Bipolar Transistors with low collectoremitter offset voltage and high current gain - A novel proposal using numerical simulation (2010) (2)
- Base etched selfaligned transistor technology for advanced polyemitter bipolar transistors (1994) (2)
- Inverse modeling of delta doped pseudomorphic high electron mobility transistors (2004) (2)
- Application of selectively delta-doped channel to control the floating body effect in submicron SOI MOSFETs (2000) (1)
- A Compact Analytical Model for the drain current of a TFET with non-abrupt doping profile incorporating the effect of band-gap narrowing (2015) (1)
- Doping-less Bipolar Transistor with fT Surpassing that of Conventional BJT (2013) (1)
- Cjc and the output conductance of advanced bipolar junction transistors under nonlocal impact ionization conditions (1996) (1)
- Enhanced breakdown voltage and reduced self-heating effects in thin-film lateral bipolar transistors: Design and analysis using 2-D simulation (2006) (1)
- 0.25pA/Bit Ultra-Low-Leakage 6T Single-Port SRAM on 22nm Bulk Process for IoT Applications (2020) (1)
- Numerical study of the threshold voltage of TFETs with localized charges (2014) (1)
- Two dimensional analytical model for the threshold voltage of a Gate All Around Nanowire tunneling FET with localized charges (2015) (1)
- Tunnel Field Effect Transistor (TFET) with Strained Silicon Thinfilm Body for Enhanced Drain Current and Pragmatic Threshold Voltage (2008) (1)
- K. Nadda and M. J. Kumar, “Schottky Collector Bipolar Transistor without Impurity Doped Emitter and Base: Design (2013) (0)
- Controlling the ON-resistance in SOI LDMOS using parasitic bipolar junction transistor (2014) (0)
- A New Grounded Lamination Gate (GLG) SOI MOSFET for Diminished Fringe Capacitance Effects (2006) (0)
- High Voltage Junctionless FET with Improved DC Performance Compared to LDMOS (2016) (0)
- Low-loss high-performance lateral Schottky rectifiers on SOI (2002) (0)
- A simple hole scattering length model for the solution of charge transport in bipolar transistors (1999) (0)
- Silicon-on-insulator lateral dual sidewall Schottky (SOI-LDSS) concept for improved rectifier performance : a two-dimensional simulation study (2010) (0)
- A full-range dual material gate tunnel field effect transistor drain current model considering both source and drain depletion region band-to-band tunneling (2014) (0)
- High Performance Lateral Schottky Collector Bipolar Transistors on SOI for VLSI Applications (2003) (0)
- A New Lateral Trench Sidewall Schottky (LTSS) Rectifier on SOI (2002) (0)
- Compact Modeling of Threshold Voltage in Nanoscale Strained-Si/SiGe MOSFETs (2006) (0)
- Design of High Performance Lateral Schottky Structures using Technology CAD (2003) (0)
- Lateral Schottky rectifiers for power integrated circuits (2002) (0)
- Molecular Switches of a Self-Assembling Helical Biladienone (2006) (0)
- A dc model for partially depleted SOI laterally diffused MOSFETs utilizing the HiSIM-HV compact model (2013) (0)
- K. Nadda and M. J. Kumar, “Schottky Collector Bipolar Transistor without Impurity Doped Emitter and Base: Design (2013) (0)
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M. Jagadesh Kumar is affiliated with the following schools:
