Mauro Olivieri
#174,146
Most Influential Person Now
Italian electronic engineer
Mauro Olivieri's AcademicInfluence.com Rankings
Mauro Olivieriengineering Degrees
Engineering
#8612
World Rank
#10189
Historical Rank
Electronic Engineering
#14
World Rank
#16
Historical Rank
Electrical Engineering
#2837
World Rank
#2983
Historical Rank
Applied Physics
#3429
World Rank
#3527
Historical Rank
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Engineering
Why Is Mauro Olivieri Influential?
(Suggest an Edit or Addition)According to Wikipedia, Mauro Olivieri is a professor of electronics at Sapienza University of Rome, Italy. Grown up in Genoa, Italy, Olivieri received his Master degree in electronics engineering and his Doctorate degree in electronics and computer engineering from the University of Genoa, where he was also assistant professor from 1995 to 1998. In 1998 he joined Sapienza University, where he is responsible for the Digital System Lab and holds the chairs of Digital Electronics and Digital Integrated System Architectures. Since 2018 he has been a visiting researcher at the Barcelona Supercomputing Center, Spain, within the European Processor Initiative project. Olivieri served as a project evaluator for the European Commission in the ECSEL Joint Undertaking, and as a technical expert for the Italian Economic Development Ministry on the topic “Smart Cities/Communities”. He is a senior member of the IEEE.
Mauro Olivieri's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- MPARM: Exploring the Multi-Processor SoC Design Space with SystemC (2005) (272)
- A post-compiler approach to scratchpad mapping of code (2004) (105)
- Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells (2014) (55)
- Design of synchronous and asynchronous variable-latency pipelined multipliers (2001) (53)
- Statistical Carry Lookahead Adders (1996) (43)
- A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control (2005) (41)
- Current controlled current conveyor (CCCII) and application using 65nm CMOS technology (2011) (35)
- Fuzzy logic microcontroller (1997) (35)
- A bootstrap technique for wideband amplifiers (2002) (32)
- A class of code compression schemes for reducing power consumption in embedded microprocessor systems (2004) (31)
- Side channel analysis resistant design flow (2006) (30)
- A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs (2014) (30)
- High-Level Side-Channel Attack Modeling and Simulation for Security-Critical Systems on Chips (2008) (28)
- An analysis of dynamic scheduling techniques for symbolic applications (1993) (27)
- Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops (2015) (26)
- A novel CMOS logic style with data independent power consumption (2005) (22)
- Optimal transistor sizing for maximum yield in variation‐aware standard cell design (2016) (21)
- Adaptive idleness distribution for non-uniform aging tolerance in MultiProcessor Systems-on-Chip (2009) (21)
- Block placement with a Boltzmann Machine (1994) (20)
- Optimal NBTI degradation and PVT variation resistant device sizing in a full adder cell (2015) (19)
- Static Minimization of Total Energy Consumption in Memory Subsystem for Scratchpad-Based Systems-on-Chips (2009) (18)
- Logic Drivers: A Propagation Delay Modeling Paradigm for Statistical Simulation of Standard Cell Designs (2014) (17)
- Completion-detecting carry select addition (2000) (17)
- Hardware design of asynchronous fuzzy controllers (1996) (16)
- The international race towards Exascale in Europe (2019) (16)
- A novel logic level calculation model for leakage currents in digital nano-CMOS circuits (2011) (15)
- Clustered Boltzmann Machines: Massively Parallel Architectures for Constrained Optimization Problems (1993) (14)
- A low-power microcontroller with on-chip self-tuning digital clock-generator for variable-load applications (1999) (14)
- A novel stability analysis of a PLL for timing recovery in hard disk drives (1999) (14)
- KLU sparse direct linear solver implementation into NGSPICE (2012) (14)
- Bus-switch coding for reducing power dissipation in off-chip buses (2004) (13)
- Analysis and Implementation of a Novel Leading Zero Anticipation Algorithm for Floating-Point Arithmetic Units (2007) (13)
- Testing power-analysis attack susceptibility in register-transfer level designs (2007) (12)
- The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes (2017) (12)
- A Reconfigurable, Low Power, Temperature Compensated IC for 8-segment Gamma Correction Curve in TFT, OLED and PDP Displays (2007) (12)
- Efficient implementation of the Boltzmann machine algorithm (1993) (11)
- SC-DDPL: A Novel Standard-Cell Based Approach for Counteracting Power Analysis Attacks in the Presence of Unbalanced Routing (2020) (11)
- Necessary and sufficient conditions for the stability of microwave amplifiers with variable termination impedances (2005) (11)
- Introducing approximate memory support in Linux Kernel (2017) (11)
- Statistical nonlinear model of MESFET and HEMT devices (2003) (11)
- Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations (2016) (10)
- Investigation on the Optimal Pipeline Organization in RISC-V Multi-threaded Soft Processor Cores (2017) (10)
- A Non-deterministic Scheduler For A Software Pipelining Compiler (1992) (10)
- A new dynamic differential logic style as a countermeasure to power analysis attacks (2008) (10)
- An evaluation system for distributed-time VHDL simulation (1994) (9)
- Design centering/yield optimization of power aware band pass filter based on CMOS current controlled current conveyor (CCCII+) (2013) (9)
- An application specific multi-port RAM cell circuit for register renaming units in high speed microprocessors (2001) (9)
- TikTak: A Scalable Simulator of Wireless Sensor Networks Including Hardware/Software Interaction (2010) (8)
- Sizing and optimization of low power process variation aware standard cells (2013) (8)
- Yield optimization for low power current controlled current conveyor (2012) (8)
- Impact of Approximate Memory Data Allocation on a H.264 Software Video Encoder (2018) (8)
- A novel high-quality YUV-based image coding technique for efficient image storage in portable electronic appliances (2008) (7)
- Novel approaches to quantify failure probability due to process variations in nano-scale CMOS logic (2014) (7)
- A delay model allowing nano-CMOS standard cells statistical simulation at the logic level (2011) (7)
- Delay-Tolerant, Low-Power Protocols for Large Security-Critical Wireless Sensor Networks (2012) (7)
- A simulation-based power-aware architecture exploration of a multiprocessor system-on-chip design (2004) (7)
- First integration of MOSFET band-to-band-tunneling current in BSIM4 (2013) (7)
- A genetic approach to the design space exploration of superscalar microprocessor architectures (2001) (7)
- An Emulator for Approximate Memory Platforms Based on QEmu (2016) (6)
- Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores (2020) (6)
- A low-voltage class-AB OTA exploiting adaptive biasing (2020) (5)
- Design issues for bus switch systems in deep sub-micro metric CMOS technologies (2005) (5)
- Sonographic evaluation of soft tissue chondroma (1996) (5)
- A self timed interrupt controller: a case study in asynchronous micro-architecture design (1994) (5)
- A flip-flop implementation for the DPA-resistant Delay-based Dual-rail Pre-charge Logic family (2013) (5)
- A delay insensitive approach to the VLSI design of a DRAM controller (1993) (5)
- HW-SW optimisation of JPEG2000 wavelet transform for dedicated multimedia processor architectures (2007) (5)
- Robust three-state PFD architecture with enhanced frequency acquisition capabilities (2004) (5)
- An all-digital clock generator firm-core based on differential fine-tuned delay for reusable microprocessor cores (2001) (5)
- A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer (2019) (5)
- A physical-level LCD driver model and simulator with application to pixel crosstalk suppression (2006) (5)
- A Regulation-Based Security Evaluation Method for Data Link in Wireless Sensor Network (2014) (5)
- Semicustom design of an IEEE 1394-compliant reusable IC core (2000) (4)
- Delay insensitive micro-pipelined combinational logic (1993) (4)
- Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment (2020) (4)
- Theoretical system-level limits of power dissipation reduction under a performance constraint in VLSI microprocessor design (2002) (4)
- Theoretical system level limits of power-performance trade-off in VLSI microprocessor design (2001) (4)
- Combined Impact of NBTI Aging and Process Variations on Noise Margins of Flip-Flops (2014) (3)
- A power-balanced sequential element for the delay-based dual-rail precharge logic style (2013) (3)
- Efficient semicustom micropipeline design (1995) (3)
- The Italian research on HPC key technologies across EuroHPC (2021) (3)
- Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor (2019) (3)
- A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations (2007) (3)
- Instruction level analytic prediction of parallel CPU architecture performance (1997) (3)
- Using safe operation regions to assess the error probability of logic circuits due to process variations (2013) (3)
- Safe operation region characterization for quantifying the reliability of CMOS logic affected by process variations (2014) (3)
- A new algorithm for convergence verification in circuit level simulations (2014) (2)
- Design of a massively parallel SIMD architecture for the Boltzmann machine (1993) (2)
- BiSon-e: a lightweight and high-performance accelerator for narrow integer linear algebra computing on the edge (2022) (2)
- Optimal pipeline stage balancing in the presence of large isolated interconnect delay (2017) (2)
- AppropinQuo: A Platform Emulator for Exploring the Approximate Memory Design Space (2018) (2)
- Narrowband Delay Tolerant Protocols for WSN Applications: Characterization and Selection Guide (2016) (2)
- Software optimization of the JPEG2000 algorithm on a VLIW CPU core for system-on-chip implementation (2005) (2)
- Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors (2022) (2)
- An asynchronous approach to the RISC design of a micro-controller (1993) (2)
- Geometry Scaling Impact on Leakage Currents in FinFET Standard Cells Based on a Logic-Level Leakage Estimation Technique (2018) (2)
- Wireless and Ad Hoc Sensor Networks: An Industrial Example Using Delay Tolerant, Low Power Protocols for Security-Critical Applications (2013) (2)
- Cycle-Accurate Performance Evaluation of Parallel Jpeg2000 on a Multiprocessor System-on-Chip Platform (2006) (2)
- Performance evaluation of Jpeg2000 implementation on VLIW cores, SIMD cores and multi-cores (2011) (2)
- Synthesis Time Reconfigurable Floating Point Unit for Transprecision Computing (2018) (2)
- Customizable Vector Acceleration in Extreme-Edge Computing: A RISC-V Software/Hardware Architecture Study on VGG-16 Implementation (2021) (2)
- Implementation Techniques for Fuzzy Theory Systems and Their Applications (1999) (1)
- Statistical Variation Aware ANN and SVM Model Generation for Digital Standard Cells (2014) (1)
- Achieving power efficiency through minimum cycle time in digital signal processor design (2001) (1)
- ASIC and board design of a high performance parallel architecture (1992) (1)
- An asynchronous distributed architecture model for the Boltzmann machine control mechanism (1996) (1)
- Performance analysis of a parallel VLSI architecture for Prolog (1995) (1)
- A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design (2021) (1)
- Performance-timing overhead trade-off analysis for a low-power data bus encoding based on input lines reordering (2005) (1)
- A parallel architecture for the Color Doppler flow technique in ultrasound imaging (1993) (1)
- Overview on a formal model of architecture/circuit trade-offs for the implementation of fast processors (2001) (1)
- A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures (2013) (1)
- Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications (2022) (1)
- Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration (2022) (1)
- Full System Emulation of Approximate Memory Platforms with AppropinQuo (2019) (1)
- Circuit-level power efficiency investigation of advanced DSP architectures based on a specialized power modeling technique (2005) (1)
- Response of Equipments to High Frequency Excitations (1983) (0)
- Design and Test Automation in Europe (DATE) (2012) (0)
- SBWR - Drywell Head Ultimate Pressure Capability (1993) (0)
- On the Computation of FRS (1983) (0)
- Encoding circuits for low power optical on-chip communications (2005) (0)
- Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations (2016) (0)
- Results on leakage power management in scratchpad-based embedded systems (2007) (0)
- Theoretical system-level model for power-performance trade-off in VLSI microprocessor design (2007) (0)
- Variability aware modeling of SEU induced failure probability of logic circuit paths in static conditions (2015) (0)
- Message from the general chairs (2015) (0)
- Correction to "design of synchronous and asynchronous variable-latency pipelined multipliers" (2001) (0)
- An analysis of dynamic scheduling techniques for symbolic applications (1993) (0)
- Yield Optimization by Means of Process Parameters Estimation: Comparison Between ABB and ASV Techniques (2004) (0)
- Characterizing noise pulse effects on the power consumption of idle digital cells (2018) (0)
- Bus-Switch Coding , for Dynamic Power Management in off-chip communication channels (2005) (0)
- Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core (2022) (0)
- A Model-Based Methodology to Generate Code for Timer Units (2014) (0)
- Statistical Analysis, for Reducing the Energy Dissipation in a Bus-switch Encoder (2005) (0)
- LEADER: Leakage Currents Estimation Technique for Aging Degradation Aware 16 nm CMOS Circuits (2018) (0)
- Quality Aware Selective ECC for Approximate DRAM (2019) (0)
- Delay-insensitive synthesis of the MCS 251 microcontroller core for low power applications (1999) (0)
- Design and Test of a Novel Programmable Clock Generator Semi-Custom Core for Energy-Efficient Systems-on-Chips (2005) (0)
- Contributions in evaluating the statistical impact of technology variations on delay and power dissipation of logic cells (2010) (0)
- Safe start-up sequence of integrated charge pumps using dedicated control circuit (2005) (0)
- LCD Design Techniques (2009) (0)
- A comprehensive analytical model for embedded parallel microprocessors performance prediction (2004) (0)
- FAUST: Design and implementation of a pipelined RISC-V vector floating-point unit (2023) (0)
- A novel topology for a HEMT negative current mirror (2000) (0)
- Quality Aware Approximate Memory in RISC-V Linux Kernel (2019) (0)
- Mix-GEMM: An efficient HW-SW Architecture for Mixed-Precision Quantized Deep Neural Networks Inference on Edge Devices (2023) (0)
- Power efficiency of application-dependent self-configuring pipeline depth in DSP microprocessors (2003) (0)
- 2 Completion Detecting Carry Select Addition (2000) (0)
- Approximate Memory Support for Linux Early Allocators in ARM Architectures (2018) (0)
- A Platform-Based Emulator for Mass-Storage Flash Cards Evaluation in Embedded Systems (2014) (0)
- The international race towards Exascale in Europe (2019) (0)
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What Schools Are Affiliated With Mauro Olivieri?
Mauro Olivieri is affiliated with the following schools:
