Magdy Abd El-aziz. Bayoumi

Magdy Abd El-aziz. Bayoumi's AcademicInfluence.com Rankings

Engineering

#4483

World Rank

#5680

Historical Rank

Applied Physics

#1097

World Rank

#1125

Historical Rank

Electrical Engineering

#1136

World Rank

#1222

Historical Rank

engineering Degrees

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Engineering

Magdy Abd El-aziz. Bayoumi's Degrees

PhD Electrical Engineering Cairo University
Masters Electrical Engineering Cairo University
Bachelors Electrical Engineering Cairo University

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Magdy Abd El-aziz. Bayoumi's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Performance analysis of low-power 1-bit CMOS full adder cells (2002) (550)
Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style (2006) (452)
High-performance and low-power conditional discharge flip-flop (2004) (271)
Efficient Epileptic Seizure Prediction Based on Deep Learning (2019) (189)
Low-Power Cache Design Using 7T SRAM Cell (2007) (170)
A novel high-performance CMOS 1-bit full-adder cell (2000) (151)
A VLSI implementation of residue adders (1987) (140)
The Hierarchical Hypercube: A New Interconnection Topology for Massively Parallel Systems (1994) (133)
A new cell for low power adders (1996) (129)
Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop (2007) (126)
Design methodologies for high-performance noise-tolerant XOR-XNOR circuits (2006) (116)
NEDA: a low-power high-performance DCT architecture (2006) (102)
Interconnect noise analysis and optimization in deep submicron technology (2003) (95)
A low power 10-transistor full adder cell for embedded architectures (2001) (94)
Fast and flexible architectures for RNS arithmetic decoding (1992) (82)
Novel 7T sram cell for low power cache design (2005) (79)
Learning on Silicon: Adaptive VLSI Neural Systems (1999) (75)
Fast Motion Estimation System Using Dynamic Models for H.264/AVC Video Coding (2012) (69)
Three-dimensional discrete wavelet transform architectures (2002) (69)
A structured approach for designing low power adders (1997) (68)
Discrete Wavelet Transform: Architectures, Design and Performance Issues (2003) (68)
A Lightweight Collaborative Fault Tolerant Target Localization System for Wireless Sensor Networks (2009) (66)
A 10-transistor low-power high-speed full adder cell (1999) (65)
Performance evaluation of 1-bit CMOS adder cells (1999) (63)
Leakage sources and possible solutions in nanometer CMOS technologies (2005) (60)
Low-Power Clocked-Pseudo-NMOS Flip-Flop for Level Conversion in Dual Supply Systems (2009) (56)
On the design of low-energy hybrid CMOS 1-bit full adder cells (2004) (56)
Arabic text recognition using neural networks (1994) (55)
A merged multiplier-accumulator for high speed signal processing applications (2002) (50)
A look-up table VLSI design methodology for RNS structures used in DSP applications (1987) (49)
A Review on Internet of Things (IoT): Security and Privacy Requirements and the Solution Approaches (2017) (47)
Resource-Aware Data Fusion Algorithms for Wireless Sensor Networks (2012) (47)
Lightweight Cryptography for Internet of Insecure Things: A Survey (2019) (47)
A PUF-based paradigm for IoT security (2016) (45)
Novel design methodology for high-performance XOR-XNOR circuit design (2003) (45)
High Speed and Area-Efficient Multiply Accumulate (MAC) Unit for Digital Signal Prossing Applications (2007) (44)
Cost-Efficient and Robust On-Demand Video Transcoding Using Heterogeneous Cloud Services (2017) (41)
Data Fusion in WSN (2012) (41)
A network of sensor-based framework for automated visual surveillance (2007) (41)
A low power high performance distributed DCT architecture (2002) (41)
Noise tolerant low voltage XOR-XNOR for fast arithmetic (2003) (39)
Adaptive search window size algorithm for fast motion estimation in H.264/AVC standard (2005) (39)
Single-Phase SP-Domino: A Limited-Switching Dynamic Circuit Technique for Low-Power Wide Fan-in Logic Gates (2008) (39)
Deep Gated Recurrent and Convolutional Network Hybrid Model for Univariate Time Series Classification (2018) (38)
VLSC: Video Live Streaming Using Cloud Services (2016) (38)
CVSS: A Cost-Efficient and QoS-Aware Video Streaming Using Cloud Services (2016) (38)
A new full adder cell for low-power applications (1998) (38)
A comparative analysis for low power motion estimation VLSI architectures (2000) (37)
Reducing Interconnect Delay Uncertainty via Hybrid Polarity Repeater Insertion (2008) (36)
Deep Convolutional Bidirectional LSTM Recurrent Neural Network for Epileptic Seizure Detection (2018) (36)
RFID Security Threats and Basic Solutions (2017) (36)
MAC-SCC: medium access control with a separate control channel for multihop wireless networks (2003) (34)
3D discrete wavelet transform architectures (1998) (34)
Defect clustering viewed through generalized Poisson distribution (1992) (34)
Optimal Probabilistic Encryption for Secure Detection in Wireless Sensor Networks (2014) (34)
Performance Analysis and Modeling of Video Transcoding Using Heterogeneous Cloud Services (2018) (33)
A Deep Learning Approach for Automatic Seizure Detection in Children With Epilepsy (2021) (33)
A novel high write speed, low power, read-SNM-free 6T SRAM cell (2008) (32)
Brain Computer Interface: EEG Signal Preprocessing Issues and Solutions (2017) (32)
Image segmentation on a 2D array by a directed split and merge procedure (1992) (32)
Energy-balancing task allocation on wireless sensor networks for extending the lifetime (2010) (31)
Economic LSTM Approach for Recurrent Neural Networks (2019) (31)
A Three-Level Parallel High-Speed Low-Power Architecture for EBCOT of JPEG 2000 (2006) (30)
On minimizing hierarchical mesh coding overhead: (HASM) hierarchical adaptive structured mesh approach (2000) (30)
A systolic architecture for modulo multiplication (1995) (28)
A Vlsi Architecture for Separable 2-D Discrete Wavelet Transform (1998) (28)
Algorithm-based low-power VLSI architecture for 2D mesh video-object motion tracking (2002) (28)
Automatic epileptic seizure detection based on empirical mode decomposition and deep neural network (2018) (28)
A novel 8T SRAM cell with improved read-SNM (2007) (28)
Deep Learning Approach for Epileptic Focus Localization (2019) (28)
Area-Efficient NEDA Architecture for The 1-D DCT/IDCT (2006) (28)
A multi-modal automatic image registration technique based on complex wavelets (2009) (28)
An effective staggered-phase damping technique for suppressing power-gating resonance noise during mode transition (2009) (28)
MRI data compression using a 3-D discrete wavelet transform. (2002) (26)
Multiple voltage-based scheduling methodology for low power in the high level synthesis (1999) (26)
Hardware Design of a Binary Integer Decimal-based IEEE P754 Rounding Unit (2007) (26)
Algorithms for Energy-Efficient Query-Reduction in Wireless Sensor Networks (2007) (26)
Lightweight highly secure PUF protocol for mutual authentication and secret message exchange (2017) (25)
A new thinning algorithm for Arabic characters using self-organizing neural network (1995) (25)
Design and implementaion of a 2D-DCT architecture using coefficient distributed arithmetic [implementaion read implementation] (2005) (25)
VLSI architecture for hierarchical mesh-based motion estimation (1999) (24)
Machine Learning-Based Approach for Hardware Faults Prediction (2020) (23)
Secure End-to-End key establishment protocol for resource-constrained healthcare sensors in the context of IoT (2016) (23)
Semi-Supervised EEG Signals Classification System for Epileptic Seizure Detection (2019) (23)
A thinning algorithm for Arabic characters using ART2 neural network (1998) (23)
A data merging technique for high-speed low-power multiply accumulate units (2004) (22)
Remote Measuring for Sand in Pipelines Using Wireless Sensor Network (2011) (22)
Noise tolerant low power dynamic TSPCL D flip-flops (2002) (22)
High Performance On-demand Video Transcoding Using Cloud Services (2016) (22)
An overview of IEEE standardization efforts for cognitive radio networks (2015) (21)
Multisensor Data Fusion Schemes for Wireless Sensor Networks (2007) (21)
Power efficient architecture for (3,6)-regular low-density parity-check code decoder (2004) (20)
A gradient-based hybrid image fusion scheme using object extraction (2008) (20)
Fast Variable Padding Motion Estimation Using Smart Zero Motion Prejudgment Technique for Pixel and Frequency Domains (2009) (20)
Systematic Algorithm Mapping for Multidimensional Systolic Arrays (1989) (20)
Efficient Mapping of ANNs on Hypercube Massively Parallel Machines (1995) (20)
MAC-SCC: a medium access control protocol with separate control channel for reconfigurable multi-hop wireless networks (2006) (19)
An Efficient Data Reuse Motion Estimation Engine (2006) (19)
Low-latency power-efficient adaptive router design for network-on-chip (2015) (19)
A VLSI array for computing the DFT based on RNS (1986) (19)
Cost Efficient Repository Management for Cloud-Based On-demand Video Streaming (2017) (19)
Smart-flooding: A novel scheme for fault-tolerant NoCs (2009) (19)
A low power CMOS UWB pulse generator (2005) (19)
A low power VLSI architecture for mesh-based video motion tracking (2002) (18)
Semi-Supervised Deep Learning System for Epileptic Seizures Onset Prediction (2018) (18)
Models for VLSI implementation of residue number system arithmetic modules (1983) (18)
Assessment of a Spatiotemporal Deep Learning Approach for Soil Moisture Prediction and Filling the Gaps in Between Soil Moisture Observations (2021) (18)
Epileptic Seizure Detection using Deep Convolutional Autoencoder (2018) (17)
Remote Measuring of Flow Meters for Petroleum Engineering and Other Industrial Applications (2007) (17)
Parallel high-speed architecture for EBCOT in JPEG2000 (2003) (17)
An Efficient Approach for Neural Network Architecture (2018) (17)
A Multiplication-Free Algorithm and A Parallel Architecture for Affine Transformation (2002) (17)
Low-Power Distributed Kalman Filter for Wireless Sensor Networks (2011) (17)
Multi-Path Search Algorithm for Block-Based Motion Estimation (2006) (17)
Deep Learning based Reliable Early Epileptic Seizure Predictor (2018) (17)
A Low Power Domino with Differential-Controlled-Keeper (2007) (16)
Cost-Efficient Cloud-Based Video Streaming Through Measuring Hotness (2018) (16)
An efficient low power basic cell for adders (1995) (16)
A clock gated flip-flop for low power applications in 90 nm CMOS (2011) (16)
Cost-Efficient and Robust On-Demand Video Stream Transcoding Using Heterogeneous Cloud Services (2017) (16)
A Novel 90nm 8T SRAM Cell With Enhanced Stability (2007) (16)
Variable-way set associative cache design for embedded system applications (2003) (15)
Empirical Activation Function Effects on Unsupervised Convolutional LSTM Learning (2018) (15)
A hybrid adaptive scheme based on selective Gaussian modeling for real-time object detection (2009) (15)
High-speed Motion Estimation Architecture for Real-time Video Transmission (2012) (15)
A low power prototype for a 3D discrete wavelet transform processor (1999) (15)
On on-chip intelligence paradigms (2017) (14)
MIRF: A Multimodal Image Registration and Fusion Module Based on DT-CWT (2013) (14)
A novel approach towards less area overhead self-healing hardware systems (2017) (14)
Enhanced efficient Diamond Search algorithm for fast block motion estimation (2009) (14)
Pixel-Level Image Fusion Scheme based on Linear Algebra (2007) (14)
Self-healing hardware systems: A review (2019) (14)
Real-time streaming challenges in Internet of Video Things (IoVT) (2017) (14)
A 1-GS/s 6-bit flash ADC in 90 nm CMOS (2009) (14)
Computer Architectures for Machine Perception (1993) (14)
Crosstalk noise analysis in ultra deep submicrometer technologies (2003) (14)
P2E-DWT: A parallel and pipelined efficient VLSI architecture of 2-D Discrete Wavelet Transform (2011) (14)
SEM image denoising with unsupervised machine learning for better defect inspection and metrology (2021) (13)
theta (logN) architectures for RNS arithmetic decoding (1989) (13)
On integrated CMOS-MEMS system-on-chip (2005) (13)
Neuro-NoC: Energy Optimization in Heterogeneous Many-Core NoC using Neural Networks in Dark Silicon Era (2018) (13)
IoT based Efficient Epileptic Seizure Prediction System Using Deep Learning (2020) (13)
Standardization of cognitive radio networking: a comprehensive survey (2015) (13)
Self-healing router architecture for reliable network-on-chips (2017) (13)
SEDLRF: A New Door Detection System for Topological Maps (2007) (13)
Dual sense amplified bit lines (DSABL) architecture for low-power SRAM design (2005) (13)
Intelligent Fault-Prediction Assisted Self-Healing for Embryonic Hardware (2020) (13)
Automated system partitioning for synthesis of multi-chip modules (1994) (13)
Resource discovery techniques in the internet of things: A review (2020) (12)
Effects of Different Activation Functions for Unsupervised Convolutional LSTM Spatiotemporal Learning (2019) (12)
Video Surveillance for Sensor Platforms - Algorithms and Architectures (2013) (12)
New bulk dynamic threshold NMOS schemes for low-energy subthreshold domino-like circuits (2004) (12)
Transition Skew Coding for Global On-Chip Interconnect (2008) (12)
A Novel Authentication and Key Agreement Protocol for Internet of Things Based Resource-Constrained Body Area Sensors (2016) (12)
An Adaptive Block Size Phase Correlation Motion Estimation Using Adaptive Early Search Termination Technique (2007) (12)
RFID Security: A Lightweight Paradigm (2016) (12)
An area-time efficient NMOS adder (1983) (12)
A framework for assessing residual energy in wireless sensor network (2007) (12)
Gated Recurrent Neural Networks Empirical Utilization for Time Series Classification (2019) (12)
Highly stable, dual-port, sub-threshold 7T SRAM cell for ultra-low power application (2012) (12)
Efficient shield insertion for inductive noise reduction in nanometer technologies (2005) (11)
Reduced-Gate Convolutional LSTM Architecture for Next-Frame Video Prediction Using Predictive Coding (2019) (11)
A multiplication-free parallel architecture for affine transformation (2000) (11)
Algorithms for High Speed Multi-Dimensional Arithmetic and DSP Systolic Arrays (1988) (11)
Low complexity decimation filter for multi-standard digital receivers (2005) (11)
Transition Skew Coding: A Power and Area Efficient Encoding Technique for Global On-Chip Interconnects (2007) (11)
Contention reduced/conditional discharge flip-flops for level conversion in CVS systems (2004) (11)
Three-level parallel high speed architecture for EBCOT in JPEG2000 (2005) (11)
The nature of defect patterns on integrated-circuit wafer maps (1994) (11)
Specification and Verification of Systolic Arrays (1999) (11)
EB-MAC: An event based medium access control for wireless sensor networks (2009) (11)
Designing Novel AAD Pooling in Hardware for a Convolutional Neural Network Accelerator (2022) (10)
Noise-tolerant high fan-in dynamic CMOS circuit design (2005) (10)
Notice of Violation of IEEE Publication PrinciplesLDPC decoder: A cognitive radio perspective for next generation (XG) communication (2007) (10)
FPGA Implementation of High Accuracy Automatic Epileptic Seizure Detection System (2018) (10)
A theta (1) algorithm for modulo addition (1990) (10)
Demystifying Emerging Nonvolatile Memory Technologies: Understanding Advantages, Challenges, Trends, and Novel Applications (2019) (10)
A novel low-power building block CMOS cell for adders (1998) (10)
Adaptive Techniques for a Fast Frequency Domain Motion Estimation (2007) (10)
A methodology for low power scheduling with resources operating at multiple voltages (2004) (10)
On the hierarchical hypercube interconnection network (1993) (10)
A Comparative Analysis on Resource Discovery Protocols for The Internet of Things (2018) (10)
The design and implementation of multidimensional systolic arrays for DSP applications (1989) (10)
Editorial: Low-Power, Intelligent, and Secure Solutions for Realization of Internet of Things (2013) (10)
Towards real-time DPM object detector for driver assistance (2016) (10)
A Lightweight PUF-Based Authentication Protocol Using Secret Pattern Recognition for Constrained IoT Devices (2021) (10)
A Fully-Pipelined Parallel Architecture for Kalman Tracking Filter (2007) (9)
A novel technique for noise-tolerance in dynamic circuits (2003) (9)
Green novel power control framework for dense femtocell grids (2015) (9)
Optimizing the heterogeneous network on-chip design in manycore architectures (2017) (9)
Parallel arithmetic: from algebra to architecture (1990) (9)
Power- Thermal Aware Balanced Task-Resource Co-Allocation in Heterogeneous Many CPU-GPU Cores NoC in Dark Silicon Era (2018) (9)
VLSI parallel architecture for Kalman filterAn algorithm specific approach (1992) (9)
On block architectures for discrete wavelet transform (1998) (9)
Cloud-Based Video Streaming for Energy-and Compute-Limited Thin Clients (2015) (9)
A Novel Reconfigurable Hardware Architecture of Neural Network (2019) (9)
Rate-adaptive probabilistic spectrum management for cognitive radio networks (2011) (9)
Security Taxonomy in IoT – A Survey (2019) (9)
Empirical model-based adaptive control of MANETs (2008) (9)
A Novel Authenticated Encryption Algorithm for RFID Systems (2013) (9)
RSSI range estimation for indoor anchor based localization for wireless sensor networks (2013) (9)
Efficient Mapping Algorithm of Multilayer Neural Network on Torus Architecture (2003) (9)
Video codec incorporating block-based multihypothesis motion-compensated prediction (2000) (9)
RBS: Redundant Bit Security Algorithm for RFID Systems (2012) (9)
Systolic temporal arithmetic: a new formalism for specification and verification of systolic arrays (1990) (9)
Cognitive Radio Networking Preliminaries (2013) (9)
Design, Implementation and Characterization of Practical Distributed Cognitive Radio Networks (2013) (9)
Introduction to RFID (2017) (8)
A Survey on the Progression and Performance of Generative Adversarial Networks (2020) (8)
Affine schemes in mesh-based video motion compensation (2003) (8)
A generalized fast motion estimation algorithm using external and internal stop search techniques for H.264 video coding standard (2008) (8)
PMCNOC: A Pipelining Multi-channel Central Caching Network-on-chip Communication Architecture Design (2007) (8)
Opportunistic Spectrum Access Challenges in Distributed Cognitive Radio Networks (2013) (8)
Novel clock gating techniques for low power flip-flops and its applications (2013) (8)
A mesh based motion tracking architecture (2001) (8)
An efficient VLSI adder for DSP architectures based on RNS (1985) (8)
Application of compressed sensing in wideband cognitive radios when sparsity is unknown (2014) (8)
Dark silicon-power-thermal aware runtime mapping and configuration in heterogeneous many-core NoC (2017) (8)
Properties and performance of the hierarchical hypercube (1992) (8)
Low Power Design of Double-Edge Triggered Flip-Flop by Reducing the Number of Clocked Transistors (2008) (8)
Reduced-Gate Convolutional LSTM Using Predictive Coding for Spatiotemporal Prediction (2018) (7)
Low power VLSI architecture for 2D-mesh video object motion tracking (2000) (7)
Implementable Spike Sorting techniques for VLSI wireless BCI/BMI implants: A survey (2015) (7)
Hybrid VLSI architecture of FIR filters using residue number systems (1985) (7)
Reducing Delay Uncertainty of On-Chip Interconnects by Combining Inverting and Non-Inverting Repeaters Insertion (2007) (7)
On low power high level synthesis using genetic algorithms (2002) (7)
Gaussian pulse approximation using standard CMOS and its application for sub‐GHz UWB impulse radio (2010) (7)
High speed single-ended pseudo differential current sense amplifier for SRAM cell (2008) (7)
Energy-Aware Distributed QR Decomposition on Wireless Sensor Nodes (2011) (7)
A 108 Gbps, 1.5 GHz 1D-DCT architecture (2000) (7)
Flexible Self-Healing Router for Reliable and High-Performance Network-an-Chips Architecture (2018) (7)
An efficient technique to improve NORA CMOS testing (1987) (7)
An efficient two's complement systolic multiplier for real-time digital signal processing (1989) (7)
Gaussian pulse approximation using standard CMOS and its application for sub-GHz UWB impulse radio (2010) (7)
Towards Autonomic Network Performance Management in mobile ad hoc networks (2010) (7)
A low power based system partitioning and binding technique for multi-chip module architectures (1997) (7)
Interconnect noise optimization in nanometer technologies (2005) (7)
Lower bounds for VLSI implementation of residue number system architectures (1986) (7)
B-DTNMOS: a novel bulk dynamic threshold NMOS scheme (2004) (7)
A low-power multiplication algorithm for signal processing in wireless sensor networks (2009) (7)
A highly reliable dual-arbiter PUF for lightweight authentication protocols (2017) (7)
Fully Decentralized Weighted Kalman Filter for Wireless Sensor Networks with FuzzyART Neural Networks (2007) (7)
A Security Approach for CoAP-based Internet of Things Resource Discovery (2020) (6)
Modeling and performance simulation of PULSE and MCMAC protocols in RFID-based IoT network using OMNeT++ (2018) (6)
FinFET based SRAM design: A survey on device, circuit, and technology issues (2014) (6)
Noise-constrained interconnect optimization for nanometer technologies (2003) (6)
A Security-Aware Pre-partitioning Technique for 3D Integrated Circuits (2017) (6)
The challenges towards energy-efficient cognitive radio networking (2014) (6)
A Parallelized Algorithm for the All-Row Preconditioned Interval Newton/Generalized Bisection Method (1991) (6)
Fast region-based DPM object detection for autonomous vehicles (2016) (6)
A 6-bit 130-MS/s low-power tracking ADC in 90 nm CMOS (2010) (6)
Opportunistic Spectrum Access: From Theory to Practice (2012) (6)
Multisensor data fusion methods for petroleum engineering applications (2009) (6)
A Low Power 4-bit Interleaved Burst Sampling ADC for Sub-GHz Impulse UWB Radio (2007) (6)
Sand monitoring in pipelines using Distributed Data Fusion algorithm (2011) (6)
Wireless Sensors Integration into Internet of Things and The Security Primitives (2016) (6)
Self-Sleep Buffer for Distributed MTCMOS Design (2008) (6)
An ultra-low power current reused CMOS low noise amplifier for x-band space application (2012) (6)
Architectures for the three-dimensional discrete wavelet transform (1998) (6)
A partial parallel algorithm and architecture for arithmetic encoder in JPEG2000 (2005) (6)
An efficient mapping of multilayer perceptron with backpropagation ANNs on hypercubes (1993) (6)
A survey on security in internet of things with a focus on the impact of emerging technologies (2022) (6)
Vlsi Design Methodologies For Digital Signal Processing Architectures (2005) (6)
Enhanced low power motion estimation VLSI architectures for video compression (2001) (6)
Adaptive neural matching online spike sorting VLSI chip design for wireless BCI implants (2015) (6)
A Cost-Effective Self-Healing Approach for Reliable Hardware Systems (2018) (6)
System Framework and Protocols for Ubiquitous Computing Based Monitoring of an Oil Platform (2010) (6)
The Extended Cube Connected Cycles: An Efficient Interconnection for Massively Parallel Systems (1996) (6)
VLSI Signal Processing Technology (1997) (6)
A 90 nm low-power successive approximation register for A/D conversions (2011) (5)
Visual Sensor Nodes (2014) (5)
Real-time VLSI architecture for detection of moving object using Wronskian determinant (2005) (5)
Testing of a NORA CMOS serial-parallel multiplier (1989) (5)
Low-power binding of function units in high-level synthesis (1999) (5)
5 – Trends in Low-Power VLSI Design (2005) (5)
Reducing wakeup latency and energy of MTCMOS circuits via keeper insertion (2008) (5)
An Analysis of Univariate and Multivariate Electrocardiography Signal Classification (2019) (5)
Deep Learning-Based Defect Classification and Detection in SEM Images (2022) (5)
A new low power building block cell for adders (1997) (5)
Digital IF decimation filters for 3G systems using pipeline/interleaving architecture (2003) (5)
Low power video object motion-tracking architecture for very low bit rate online video applications (2000) (5)
A Directed Genetic Algorithms for Treating Linear Programming Problems (2003) (5)
Unsupervised machine learning based CD-SEM image segregator for OPC and process window estimation (2020) (5)
A New Efficient Block-Matching Algorithm for Motion Estimation (2006) (5)
SIGMA-DELTA BITSTREAM FILTERING IN VLSI (1994) (5)
A computational kernel for fast and efficient compressed-domain calculations of wavelet subband energies (2003) (5)
A double-edge implicit-pulsed level convert flip-flop (2004) (5)
A hardware obfuscation technique for manufacturing a secure 3D IC (2018) (5)
A PIPELINING METHOD FOR HIGH SPEED VLSI WAVE DIGITAL FILTERS (1994) (5)
Generative Adversarial Networks in Security: A Survey (2020) (5)
VLSI architecture for an object change detector for visual sensors (2005) (5)
Multi-look-up-table module for RNS systems implementation (1984) (5)
A new gate-level body biasing technique for PMOS transistors in subthreshold CMOS circuits (2005) (5)
A Novel Authenticated Cipher for RFID Systems (2014) (5)
A Low Complexity Inter Mode Decision for MPEG-2 to H.264/AVC Video Transcoding in Mobile Environments (2009) (5)
Cost-Efficient Storage for On-Demand Video Streaming on Cloud (2020) (5)
A low-power clock frequency multiplier (2006) (4)
A Low Power Hardware Implementation of Multi-Object DPM Detector for Autonomous Driving (2018) (4)
Introducing a Novel Smart Design Framework for a Reconfigurable Multi-Processor Systems-on-Chip (MPSoC) Architecture (2016) (4)
An efficient compressive wideband spectrum sensing architecture for cognitive radios (2013) (4)
Lightweight Polymorphic Encryption for the Data Associated with Constrained Internet of Things Devices (2020) (4)
Hotspot-aware task-resource co-allocation for heterogeneous many-core networks-on-chip (2018) (4)
Precharged SRAM cell for ultra low-power on-chip cache (2005) (4)
A novel scheduling-based CAD methodology for exploring the design space of ASICs for low power (1998) (4)
A framework for high level synthesis of digital architectures from u-recursive algorithms (1990) (4)
Acoustic target localization in sensor networks with FUZZYART (2007) (4)
Efficient Mutliplierless Polyphase FIR Filter based on New Distributed Arithmetic Architecture (2007) (4)
Dynamic fraction control bus: new SOC on-chip communication architecture design (2005) (4)
Green energy solution for femtocell power control in massive deployments (2015) (4)
Architecture of A Novel Low-Cost Hardware Neural Network (2020) (4)
Tree-based special-purpose Array architectures for neural computing (1995) (4)
Wiring-Area Efficient Simultaneous Bidirectional Point-to-Point Link for Inter-Block On-Chip Signaling (2008) (4)
A Clock gated Successive Approximation Register for a/d Conversions (2014) (4)
A novel ultra-low-energy bulk dynamic threshold PMOS scheme (2003) (4)
Minimizing switchings of the function units through binding for low power (1999) (4)
Low Power Lookup Tables for Huffman Decoding (2007) (4)
A fast block-based motion estimation using early stop search techniques for H.264/AVC standard (2007) (4)
An architecture for automated scene understanding (2005) (4)
Decentralized clustering in VANET using adaptive resonance theory (2015) (4)
A Reversible-Logic Based Architecture for Long Short-Term Memory (LSTM) Network (2021) (4)
A Review of Quantum Computer Energy Efficiency (2019) (4)
A novel clustering paradigm for key pre-distribution: Toward a better security in homogenous WSNs (2013) (4)
An enhanced low-power computational kernel for a pipelined multiplier-accumulator unit (1998) (4)
Methodologies for binding function units for low power in high level synthesis (1999) (4)
A Survey on the power and robustness of FinFET SRAM (2016) (4)
An Efficient Deep Learning System for Epileptic Seizure Prediction (2021) (4)
Experimental evaluation of Opportunistic Spectrum Access in distributed cognitive radio networks (2012) (4)
A comprehensive operand-aware dynamic clock gating scheme for low-power Domino Logic (2013) (4)
Hierarchical Time-Extended Petri Nets (H-EPNs) for Integrated Control and Diagnostics of Multilevel Systems (2000) (4)
VLSI Architectures for JPEG 2000 EBCOT (2006) (4)
VAStream: A Visual Analytics System for Fast Data Streams (2019) (4)
A Novel Design Gate based Low-Cost Configurable RO PUF using Reversible Logic (2019) (4)
Parallel implementation of a cut and paste maze routing algorithm (1993) (4)
Proceedings of the 16th IEEE international conference on Image processing (2009) (4)
Noise Metrics in Flip-Flop Designs (2005) (4)
Robust object tracking using correspondence voting for smart surveillance visual sensing nodes (2009) (4)
A VLSI model for residue number system architectures (1984) (4)
Implementation of NEDA-based DCT architecture using even-odd decomposition of the 8 × 8 DCT matrix (2006) (4)
A VLSI architecture for 2D mesh-based video object motion estimation (2000) (4)
A fast discrete transform architecture for Frequency Domain Motion Estimation (2010) (4)
An Efficient Adaptive High Speed Manipulation Architecture for Fast Variable Padding Frequency Domain Motion Estimation (2011) (4)
Green arithmetic logic unit (2012) (4)
TALS: Trigonometry-based Ad-hoc Localization System for wireless sensor networks (2011) (4)
High speed intra mode and direction prediction for MPEG-2 to H.264/AVC realtime transcoder (2011) (4)
On gate leakage reduction in dynamic CMOS circuits (2005) (4)
An application-specific array architecture for feedforward with backpropagation ANNs (1993) (4)
A complete scheme for distributed LU decomposition on wireless sensor networks (2010) (4)
A high speed architecture for MAP decoder (2002) (4)
Energy Efficient and Noise-Tolerant XOR-XNOR Circuit Design (2003) (3)
Systolic array implementation of image segmentation by a directed split and merge procedure (1990) (3)
Motion estimation algorithm for real-time systems (2004) (3)
Fast deep pyramid DPM object detection with region proposal networks (2017) (3)
ETSSI: Energy-based Task Scheduling Simulator for wireless sensor networks (2011) (3)
Area Efficient High Speed and Low Power MAC Unit (2013) (3)
A Reversible-Logic based Architecture for Artificial Neural Network (2020) (3)
A high-performance 1D-DCT architecture (2000) (3)
Secure localization for wireless sensor networks using decentralized dynamic key generation (2012) (3)
“Voodoo” error prediction for bit-depth scalable video coding (2009) (3)
An Empirical Analysis of Generative Adversarial Network Training Times with Varying Batch Sizes (2020) (3)
A Low-Power Parallel Architecture for Finite Galois Field GF(2m) Arithmetic Operations for Elliptic Curve Cryptography (2012) (3)
Green IoT System Architecture for Applied Autonomous Network Cybersecurity Monitoring (2021) (3)
Design of a power-efficient interleaved CIC architecture for software defined radio receivers (2005) (3)
Investigating the feasibility of LEAP+ in ZigBee specification (2014) (3)
Early Prediction of Epilepsy Seizures System based on Artificial Immune BCI System (2017) (3)
A Bit-Interleaved 2-Port Subthreshold 6T SRAM Array with High Write-Ability and SNM-Free Read in 90 nm (2011) (3)
Fault tolerant techniques for TSV-based interconnects in 3-D ICs (2017) (3)
Comparative Analysis on the Scaling Properties of Arbiter-based PUFs (2020) (3)
Low power VLSI prototype for motion tracking architecture (2000) (3)
Emerging Technologies: IoT, Big Data, and CPS with Sensory Systems (2018) (3)
A VLSI implementation of finite impulse response digital filters using residue number systems (1985) (3)
Real-time Parallelized Hybrid Median Filter for speckle removal in ultrasound images (2014) (3)
A low power VLSI prototype for low bit rate video applications (2000) (3)
Yield enhancement in the routing phase of integrated circuit layout synthesis (1994) (3)
Probabilistic Analysis of Power-Gating in Network-on-Chip Routers (2019) (3)
An efficient low-bit rate motion compensation technique based on quadtree (2000) (3)
A formal high level synthesis approach for DSP architectures (1990) (3)
Hybrid wavelet - DCT intra prediction for H.264/AVC interactive encoder (2014) (3)
Memory-based Arbiter PUF: A Novel Highly Reliable and Scalable Strong PUF Design (2020) (3)
A theta (log n) algorithm for modulo multiplication (1989) (3)
Reducing misprediction penalty in the Branch Target Buffer (2007) (3)
Traffic-aware power-gating scheme for Network-on-Chip routers (2016) (3)
A systolic (VLSI) array using RNS for digital signal processing applications (1984) (3)
State-of-the-Art of Cognitive Radio Networks (2013) (3)
A high speed VLSI architecture for scaleable ATM switches (1996) (3)
Formal Synthesis of a Parallel Architectures from Recursive Equations (1990) (3)
Fault tolerant Hopfield associative memory on torus (2003) (3)
Router-level performance driven dynamic management in hierarchical networks-on-chip (2017) (3)
A VLSI architecture for hierarchical mesh based motion compensation using scalable affine transformation core (2000) (3)
A fault-tolerant bit-serial array structure for digital filters (1988) (3)
A scalable affine core for mesh-based video object motion compensation (2000) (3)
ULSI design-for-manufacturability: a yield enhancement approach (1994) (3)
Simultaneous partitioning, scheduling and allocation for synthesis of multi-chip module architectures (1994) (3)
Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family (2008) (3)
BCI/AIS low power adaptive architecture for early prediction of epilepsy seizures (2017) (3)
Semi-supervised Learning for Epileptic Focus Localization Using Deep Convolutional Autoencoder (2019) (3)
Reconfigurable Hardware Design Approach for Economic Neural Network (2022) (3)
Texture feature extraction in the wavelet compressed domain (2000) (3)
A scalable shared buffer ATM switch architecture (1995) (3)
An efficient low-bit rate adaptive mesh-based motion compensation technique (2001) (2)
Mixed-Mode Programmable and Scalable Architecture for On-Chip Learning (1999) (2)
A formal design methodology for parallel architectures (1990) (2)
Unsupervised Ranking of Numerical Observations based on Magnetic Properties and Correlation Coefficient (2019) (2)
Efficient Reconfigurable Global Network-on-Chip Designs towards Heterogeneous CPU-GPU Systems: An Application-Aware Approach (2017) (2)
Compressed domain texture classification from a modified EZW symbol stream (2000) (2)
A systolic array for image segmentation using split and merge procedure (1989) (2)
Low Power Full Search Block Matching Motion Estimation Vlsi Architectures (2004) (2)
Physical Layer Security for IoT Communications - A Survey (2021) (2)
Evaluation of Femtocell Technology Challenges and Its Power Control Methodologies for Green Heterogeneous Networks (2018) (2)
Memory-Efficient Architecture for Hysteresis Thresholding and Object Feature Extraction (2011) (2)
Toward fast low power adaptive spike sorting VLSI chip design for wireless BCI implants (2015) (2)
Coefficient Elimination Algorithm for Low Energy Distributed Arithmetic DCT Architectures (2005) (2)
An efficient minimum area spacing algorithm for noise reduction (2003) (2)
Unsupervised machine learning based SEM image denoising for robust contour detection (2021) (2)
Dynamically Reconfigurable Deep Learning for Efficient Video Processing in Smart IoT Systems (2020) (2)
Memory accesses reduction for MIME algorithm (2003) (2)
Self-Healing Router Approach for High-Performance Network-on-Chip (2021) (2)
Power analysis of the Huffman decoding tree (2008) (2)
Low power very large scale integration prototype for three-dimensional discrete wavelet transform processor with medical applications (2003) (2)
VLSI MAP decoder architectural analysis (2004) (2)
Probabilistic framework for opportunistic spectrum management in cognitive ad hoc networks (2011) (2)
Distributed Kalman Filter using fast polynomial filter (2011) (2)
Multi-dimensional systolic networks for DSP algorithms (1988) (2)
Improving Hierarchy Storage for Video Streaming in Cloud (2021) (2)
A Speed and Energy Focused Framework for Dynamic Hardware Reconfiguration (2019) (2)
A compact single-pass architecture for hysteresis thresholding and component labeling (2010) (2)
Minimum-area shield insertion for explicit inductive noise reduction (2003) (2)
Low Power Conditional-Discharge Pulsed Flip-Flops (2003) (2)
A VLSI architecture for hybrid object-based video motion estimation (2000) (2)
A quadratic residue processor for complex DSP applications (1987) (2)
A low power architecture for a new efficient block-matching motion estimation algorithm (2000) (2)
A scalable analog architecture for neural networks with on-chip learning and refreshing (1995) (2)
Efficient multistage decimation filter using pipeline/interleaving architectures for digital IF receiver (2003) (2)
VLSI architecture for separable 2-D discrete wavelet transform (1999) (2)
A non-zero clock skew scheduling algorithm for high speed clock distribution network (1999) (2)
External-internal dual switch leakage controlled flip-flop design (2005) (2)
Data fusion framework for sand detection in pipelines (2009) (2)
Tunable level-shifter/buffer for dual supply systems and low-power clock-tree design in deep-submicron application (2005) (2)
An efficient adaptive manipulation architecture for real time video coding in Frequency Domain (2009) (2)
Hopfield associative memory on mesh (2004) (2)
Hybrid mesh-based/block-based motion compensation architecture (2001) (2)
On sub-Nyquist spectrum sensing for wideband cognitve radios (2016) (2)
A co-design based high-performance real-time GIS (1999) (2)
A low power adaptive transmitter architecture for low band UWB applications (2006) (2)
Redundant Bit Security in RFIDs: Architecture Design and Security Performance Evaluation (2017) (2)
A general purpose VLSI chip for robot axis motion controller (1992) (2)
Wireless sensor networks: a new communication paradigm (2005) (2)
Cloud-Based Video Streaming Services: A Survey (2020) (2)
A Low Power Architecture for HASM Motion Tracking (2004) (2)
Chapter Four - A survey on cloud-based video streaming services (2021) (2)
A new ATM switch architecture: scalable shared buffer (1996) (2)
Cost Minimization of Cloud Services for On-Demand Video Streaming (2022) (2)
A low power and high performance core for planar object overlaying (1999) (2)
Learning on Silicon: Editorial (1999) (2)
A Novel Design Reversible Logic Based Configurable Fault-Tolerant Embryonic Hardware (2020) (2)
Systolic array architectures for full-search block matching motion estimation (2002) (2)
Novel formulations for low-power binding of function units in high-level synthesis (1999) (2)
VLSI implementation of a systolic database machine for relational algebra and hashing (1991) (2)
Post-Silicon Clock-nvert (PSCI) for reducing process-variation induced skew in buffered clock networks (2009) (1)
Low-power and high-speed architecture for EBCOT block in JPEG2000 system (2004) (1)
An efficient successive elimination algorithm for block-matching motion estimation (2000) (1)
Deep Learning based Defect classification and detection in SEM images: A Mask R-CNN approach (2022) (1)
Wireless sensors networks infrastructure for Oil Industry (2010) (1)
High-performance asic architecture for hysteresis thresholding and component feature extraction in limited-resource applications (2011) (1)
A high speed pipelined FFT processor (1991) (1)
A low power VLSI architecture for multistage interval-based motion estimation (MIME) algorithm (2002) (1)
Performance analysis for a new automatic error control system for overcoming atmospheric multipath fading with random bit errors for wireless ATM networks (1999) (1)
An efficient low-bit rate adaptive mesh-based motion compensation technique (2000) (1)
Low power SOVA architecture using bi-directional scheme (2002) (1)
On reconfigurable fabrics for intelligent hardware systems (2017) (1)
A band-matching approach for motion estimation (1997) (1)
Performance analysis for a new automatic error control system for overcoming turbulent fading errors for wireless ATM networks (1999) (1)
Performance Evaluation and Design Optimization for Flexible Multiple Instruction Multiple Data Elliptic Curve Cryptography Crypto Architecture (2015) (1)
Framework for generating and designing spectrum awareness modules for opportunistic networking (2017) (1)
Repair techniques for aged TSVs in 3D integrated circuits (2017) (1)
A new partitioning framework for uniform clock distribution during high-level synthesis (1998) (1)
A low power 3-D discrete wavelet transform processor for medical applications (1999) (1)
RBS RFID Security and the Internet of Things (2017) (1)
Bitonic Sort on the Connection Machine (1994) (1)
An efficient low-bit rate motion compensation technique based on quadtree (2000) (1)
Testbed implementation for Autonomic Network Performance Management of wireless mesh networks (2012) (1)
Automated object detection and tracking based on clustered sensor networks (2007) (1)
A low power architecture for a new efficient block-matching motion estimation algorithm (2000) (1)
Motion-estimation parallel algorithm based on band matching (1997) (1)
Enhanced Parallel Interference Cancellation using Decorrelator for the base-station receiver (2004) (1)
Spectrum-Awareness-Based Performance and Scalability of Cognitive Radio Networks (2018) (1)
A VLSI implementation of an FFT/NTT computational unit (1985) (1)
Noise-tolerant design and analysis for a low-voltage dynamic full adder cell (2002) (1)
A fast new method to mitigate amplifier-induced ICI in OFDM systems based on predistortion in DFT domain (2013) (1)
The area-time complexity of a VLSI digital filter using residue number systems (1986) (1)
System-on-chip communication architecture: dynamic parallel fraction control bus design and test methodologies (2007) (1)
A model-based framework for autonomic performance management of wireless mesh networks (2011) (1)
A Convolutional Gated Recurrent Neural Network for Seizure Onset Localization (2020) (1)
Hardware architecture for fast Intra mode and direction prediction in real-time MPEG-2 to H.264/AVC transcoder (2012) (1)
Security Aspects of Internet of Things – A Survey (2020) (1)
Sensor Sequential Data-Stream Classification Using Deep Gated Hybrid Architecture (2019) (1)
Self-Healing Approach for Hardware Neural Network Architecture (2019) (1)
Parallel algorithms prototyping: a case study (1990) (1)
Guaranteeing QoS with the pipelined multi-channel central caching NoC communication architecture (2008) (1)
Design of a 24 GHz ultra low power current reused CMOS LNA in subthreshold region (2012) (1)
Compressed-domain classification of texture images (2000) (1)
An efficient frequency domain intra prediction for H.264/AVC (2008) (1)
A low power VLSI design paradigm for iterative decoders (2005) (1)
An efficient mapping algorithm of multilayer perceptron on mesh-connected architectures (1996) (1)
A new block-matching motion estimation algorithm based on successive elimination (2000) (1)
SDS: a framework for the design of DSP ASICs (1992) (1)
Optimal mapping of feedforward neural networks onto multiple bus architectures (1994) (1)
New Wireless Sensors Networks: The Art of Integration (2007) (1)
An Efficient Embryonic Hardware Architecture based on Network-on-Chip (2021) (1)
Implementation of RNS Multiplication in VLSI (1985) (1)
7 – Noise Analysis and Design in Deep Submicron Technology (2005) (1)
Hybrid multiplierless FIR filter architecture based on NEDA (2007) (1)
A Flexible Architecture for Finite Field Galois Fields(2m) Arithmetic Processor (2011) (1)
A 3.1 GB/s, 8 Kb, ZERO PRECHARGE, PIPELINED, HIGHLY STABLE 2-PORT 8T SRAM DESIGN IN 65 nm (2013) (1)
An efficient low-bit rate adaptive mesh-based motion compensation technique (2000) (1)
Intelligent Resource Discovery Approach for The Internet of Things (2021) (1)
Early Prediction of Epilepsy Seizures VLSI BCI System (2019) (1)
Foreword for March 1996 issue (1996) (1)
An Adaptive Block Size Phase Correlation Motion Estimation using Smart Multireference Frames Selection in Frequency Domain (2007) (1)
A VLSI architecture for rate-distortion optimized motion compensation using variable size blocks (1993) (1)
An Energy-Detection-Based Cooperative Spectrum Sensing Scheme for Minimizing the Effects of NPEE and RSPF (2016) (1)
Novel Adaptive Body Biasing Techniques for Energy Efficient Subthreshold CMOS Circuits (2007) (1)
Dynamic profiling algorithms for low bit rate video applications (2004) (1)
Mc-PUF: Memory-based and Machine Learning Resilient Strong PUF for Device Authentication in Internet of Things (2021) (1)
Efficient high speed lattice-CORDIC IFFT architecture for DMT transmitter (2010) (1)
Convolution Processing Unit Featuring Adaptive Precision using Dynamic Reconfiguration (2021) (1)
A novel scheduling-based CAD methodology for exploring the design space for low power (1998) (1)
Design and analysis of energy reference metric in a cluster based wireless sensor network (2008) (1)
High-Speed and Low-Power IP for Embedded Block Coding with Optimized Truncation (EBCOT) Sub-Block in JPEG2000 System Implementation (2006) (1)
Autonomous Decentralized Systems Based Approach to Object Detection in Sensor Clusters (2005) (1)
Cyber - Physical Systems: Reality, dreams, and fantasy (2015) (1)
Reliable modulo systolic arrays for DSP algorithms (1988) (1)
ASPEN: An Asynchronous Signal Processor for Energy Efficient Sensor Nodes (2010) (1)
A slice of a brain: a hybrid neural chip set (1994) (1)
Real-Time Heterogeneous Video Transcoding for Low-Power Applications (2014) (1)
Parameterized modeling of open-circuit critical volume for three-dimensional defects in VLSI processing (1994) (1)
Correction to "Efficient Mapping of ANNs on Hypercube Massively Parallel Machines" (1996) (1)
From algorithms to parallel architectures: a formal approach (1991) (1)
Design and implementation of a surface peak thermal detector algorithm (2007) (1)
Proposed Centralized Data Fusion Algorithms (2012) (1)
Apology [Plagiarism] (2008) (1)
Forward Body Biasing Technique in Current Folded CMOS LNA in Subthreshold Region for Biomedical Applications (2014) (1)
Full-Search Free Intra Prediction Algorithm for Real-Time H.264/AVC Decoder (2012) (1)
Parallel multiplication-free algorithm and architecture for affine-based motion compensation (2003) (1)
An energy-efficient 32-bit RISC processor for sensor platform in 90nm technology (2012) (1)
Hardware Acceleration of the Gipps Model for Real-Time Traffic Simulation (2013) (0)
Call for Papers and Participation (0)
A cluster-based key management framework for resource constraint networks (2014) (0)
Proceedings Third International Workshop on Digital and Computational Video. (2002) (0)
Vlsi Implementaton of residue number System Architectures (1985) (0)
SYSTOLIC TEMPORAL ARITHMETIC: A FORMALISM (1999) (0)
Symbolic execution using approximate computing (SEAC) — A novel branch hazard distribution method (2018) (0)
A low-area, low-power programmable frequency multiplier for DLL based clock synthesizers (2008) (0)
Stochastic Selection of Responses for Physically Unclonable Functions (2022) (0)
A Reversible-Logic based Architecture for VGGNet (2021) (0)
Three-dimensional defect sensitivity modeling for open circuits in ULSI structures (1998) (0)
Building and Evaluating COTS Based Optical Interlinks for Nanosatellites (2015) (0)
An embedded global addressing technique for scalable neural architectures (1997) (0)
It was Really Lagniappe!: Highlights from ICASSP 2017 in New Orleans [Conference Highlights] (2017) (0)
Future Special Issues/Special Sections of the Proceedings (2018) (0)
A systematic framework for high throughput MAP decoder VLSI architectures (2005) (0)
Comparing performance metrics of a parallel ECC architecture vs. input data patterns and granularity (2012) (0)
A non-zero clock skew scheduling algorithm for high speed clock distribution network (1999) (0)
Rate-Adaptive Probabilistic Approach for Opportunistic Spectrum Access (2013) (0)
A Perceptron-Inspired Technique for Hardware Obfuscation (2018) (0)
VLSI Architectures for JPEG 2000 EBCOT: Design Techniques and Challenges (2006) (0)
MULTIDIMENSIONAL SYSTOLIC ARRAYS FOR DSP APPLICATIONS (1989) (0)
A fast isointensity maps based approach to optimal motion field computation for MPEG coding (2003) (0)
Efficient 45nm ASIC Architecture for Full-Search Free Intra Prediction in Real-Time H.264/AVC Decoder (2013) (0)
FFT based fast architecture & algorithm for discrete wavelet transforms (1995) (0)
On Through Silicon Vias as used in three dimensional integrated circuits (2013) (0)
VSTA: A SPECIAL PURPOSE FORMAL VERIFIER FOR SYSTOLIC DESIGNS (1999) (0)
HIGH PERFORMANCE CAMERA-BASED MODULES FOR AUTONOMOUS VEHICLES (2016) (0)
Standardization of cognitive radio networking: a comprehensive survey (2015) (0)
An Efficient Reconfigurable Neural Network on Chip (2021) (0)
OAPM: Fine-grained operand-aware power management with fast reaction time (2014) (0)
RAP-MAC Performance Optimization with Statistical PRN Guarantees (2013) (0)
RAP-MAC Empirical Performance Evaluation (2013) (0)
Artificial Intelligence in Deepfake Technologies Based on Supply Chain Strategy (2020) (0)
PROCEEDINGS OF THE 37TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (1994) (0)
The land of pixels hosts ICIP 2009 [Conference Spotlight] (2009) (0)
Correlation-based detection of TCM signals for cognitive radios (2017) (0)
Skeletonization of Arabic Characters Using a Neural Network Mapped on Maspar (2021) (0)
A graph based approach to the synthesis of multi-chip module architectures (1996) (0)
Power efficient and scalable video compression for mobile multimedia devices (2010) (0)
Low power and high performance vlsi circuits for clocking systems (2005) (0)
Jfi(ton New OrCeans CJQverside, New Or(eans, Louisiana, VS)I PRELIMINARY CALL FOR PAPERS (2007) (0)
Special Issue on Systems-on-Chip: Design and Integration (2006) (0)
VLSI Technology: Impact and Promise. Identifying Emerging Issues and Trends in Technology for Special Education. (1992) (0)
Energy-efficient XOR gate with embedded level conversion for serial-link encoding (2011) (0)
RBS Performance Evaluation (2017) (0)
An application specific architecture for rate-distortion optimized motion compensation (1993) (0)
2000 IEEE Workshop on Signal Processing Systems : SiPS 2000 : design and implementation, 11-13 October, 2000, Lafayette, Louisiana (2000) (0)
Proceedings : IEEE Computer Society Annual Symposium on VLSI : emerging trends in VLSI systems design : 19-20 February 2004, Lafayette, Louisiana (2004) (0)
An Efficient Capsule Network Reconfigurable Hardware Accelerator for Deciphering Ancient Scripts with Scarce Annotations (2021) (0)
ASIC implementation of a computationally efficient compressive sensing detection method using least squares optimization in 45 nm CMOS technology (2015) (0)
Efficient 45nm ASIC Architecture for Full-Search Free Intra Prediction in Real-Time H.264/AVC Decoder (2012) (0)
Energy-Pivotal Solutions for Green Femtocell Power Control in Hybrid-Dense Deployments (2016) (0)
Wireless Sensor Networks: A New Life Paradigm (2005) (0)
A power-efficient architecture for EBCOT tier-1 in JPEG 2000 (2006) (0)
Mapping algorithms onto multidimensional systolic arrays (1990) (0)
FOR DIGITAL FILTERS (1988) (0)
Multiple-voltage-based high-level synthesis methodologies for low-power design (1999) (0)
INTRODUCTION TO VLSI SYSTEMS (2005) (0)
Shadow PUFs: Generating Temporal PUFs with Properties Isomorphic to Delay-Based APUFs (2022) (0)
A fast heuristic for leakage-aware synthesis (2005) (0)
Keynotes and plenary: Keynote #1: “Be Careful: I can read your mind” (2016) (0)
Novel high-throughput EBCOT architecture for JPEG2000 (2005) (0)
RAP-MAC Performance Evaluation in Large-Scale Networks (2013) (0)
De-Cache: A novel caching scheme for large-scale NoC based multiprocessor systems-on-chips (2011) (0)
MAP decoder architecture: soft IP for SOC applications (2002) (0)
Novel systolic array architecture for the decorrelator using conjugate gradient for least squares algorithm (2005) (0)
Design and Realization of Analog Phi-Function for LDPC Decoder (2007) (0)
Distributed Opportunistic Spectrum Access Networks : From Theory to Practice (2011) (0)
A e(logn) ALGORITHM FOR MODULO MULTIPLICATION (2010) (0)
SPECIFICATION AND VERIFICATION OF SYSTOLIC ARRAYS: APPLICATION EXAMPLES (1999) (0)
PPT based fast architecture & algorithm for discrete wavelet transforms (1995) (0)
Reviewing the Existing Methodologies and Tools of Cloud Forensics: Challenges and Solutions (2020) (0)
Wireless Sensor Network based Data Fusion and Control Model for an Oil Production Platform (2010) (0)
VLSI architecture for hierarchical 2D mesh representation for very low bit rate applications (1999) (0)
Editorial (2013) (0)
Wireless sensor networks: the product of a marriage made in heaven (2005) (0)
An efficient area manipulation architecture for frequency domain encoding process (2010) (0)
Study of Power-Delay Characteristics of a Mixed-Logic-Style Novel Adder Circuit at 90nm Gate Length (2020) (0)
SoC: The Promise Land for Wireless Sensors Networks (2008) (0)
XFeed PUF: A Secure and Efficient Delay-based Strong PUF Using Cross-Feed Connections (2022) (0)
A Fast Scheduling Algorithm for Low Power Design (2005) (0)
Block Computation 2-D Discrete Wavelet Transforms Architectures for (1999) (0)
Proposed Multiplication Algorithm for DKF (2012) (0)
Panel discussion: Distributed intelligence in IoT (2016) (0)
T1: Multimedia (1997) (0)
Optimized Line-of-Sight Assessment Algorithm for 5G mmW Network Design using LiDAR Information (2021) (0)
EVA-MAC: An event-based adaptive medium access control for wireless sensor networks (2011) (0)
VLSI DSP Technology: Current Developments (1994) (0)
Energy-efficient task-resource co-allocation and heterogeneous multi-core NoC design in dark silicon era (2021) (0)
Analysis of microprocessor-based digital filters (1986) (0)
Energy aware vlsi architectures for mobile video applications (2003) (0)
Low-bit-rate generalized quad-tree motion compensation algorithm and its optimal encoding schemes (2000) (0)
Energy Efficient 1-Bit Full Adder Cells for Low Voltage (2004) (0)
Proceedings of the 8th Great Lakes Symposium on VLSI : Hotel Acadiana Lafayette, Louisiana February 19-21, 1998 (1998) (0)
Experimental Results for the Proposed DKF (2012) (0)
New automatic error control system with ATM cell header reduction for wireless ATM networks (1999) (0)
CKEF: A Cluster-based Key Establishment Framework for homogenous mobile and static wireless sensor networks (2014) (0)
Editorial Special Issue on Rapid Prototyping of DSP Systems (2003) (0)
Introduction (1995) (0)
Structure generation and design of tracking ADCs (2012) (0)
On Securing MAC Layer Broadcast Signals Against Covert Channel Exploitation in 5G, 6G & Beyond (2021) (0)
VERIFYING THE CORRECTNESS OF A SYSTOLIC ARRAY FOR LU DECOMPOSITION (1999) (0)
Storage allocation strategies for data path synthesis of ASICs (1994) (0)
Efficient smart algorithms and architectures for real-time video transmission in pixel and frequency domains (2010) (0)
Adaptive Hardware Architecture for Neural-Network-on-Chip (2022) (0)
Assumers for high-speed single and multi-cycle on-chip interconnect with low repeater count (2008) (0)
EVAM-MAC: An Event Based Medium Access Control for Wireless sensor Networks with Multihop Support (2013) (0)
An Architecture for Cooperative Agent Based Automated Scene Understanding (0)
New error control enhancing technique for wireless ATM networks (1999) (0)
A Resource-Saving Energy-Efficient Reconfigurable Hardware Accelerator for BERT-based Deep Neural Network Language Models using FFT Multiplication (2022) (0)
A Method for Nonasymptotic Performance Analyses of Array Signal Processing Algorithms (1994) (0)
A Reconfiguration Technique for Reliable VLSI DSP Array Processors (1992) (0)
A flexible operand size architecture for gf(2m) arithmetic processors (2011) (0)
High Speed Power Efficient Asynchronous Adders (2017) (0)
Communication protocol with interference awareness for sensor networks with security enhancemments (2004) (0)
Editorial (2005) (0)
MIRF: A Multimodal Image Registration and Fusion Module Based on DT-CWT (2012) (0)
An energy efficient protocol exploiting cache data for sensor networks (2005) (0)
A system framework for assessment and reduction of energy in wireless sensor networks (2008) (0)
An efficient polynomial-modulus based technique for multiplication of large integers (2005) (0)
Low power full search block matching motion estimation architecture (2002) (0)
SPECIFICATION AND VERIFICATION OF SYSTOLIC ARRAYS: DEFINITIONS AND RELATED WORK (1999) (0)
Challenges and opportunities of silicon technology in communications (2005) (0)
A Parallel Algorithm for Neural Computing (2021) (0)
Efficient MPEG-2 to H.264/AVC Transcoding (2014) (0)
Cost-effective and low-power memory address bus encodings (2008) (0)
Proposed Distributed Kalman Filter (2012) (0)
RBS Security Analysis (2017) (0)
Algorithm for Modulo Addition (2004) (0)
A smart motion estimation paradigm for real-time video coding (2007) (0)
Keynote speech 1: Wireless sensors networks: Challenges and opportunities (2010) (0)
A prototype chipset for a large scaleable ATM switching node (1997) (0)
Frequency domain: Efficient and high speed technology for video transmission (2011) (0)
sed System Partitioning a Multi-Chip Module Arch (1997) (0)
SPECIFICATION AND VERIFICATION FRAMEWORK (1999) (0)
A Reversible-Logic based Architecture for Convolutional Neural Network (CNN) (2021) (0)
A motion-estimation architecture based on band-matching (1997) (0)
8-Bit Sub Threshold Ripple Carry Adders in 32nm CMOS Technology for Wireless Sensor nodes (2017) (0)
A scalable affine core for video object motion compensation (2000) (0)
Power Efficiency and Scalability in Video Compression (2010) (0)
A Data Fusion Scheme for Tenet Architecture (2007) (0)
Energy scavenging and storage using through silicon vias to reduce power consumption in 3D ICs (2014) (0)
LSI Design-For A Yield Enhanc (1996) (0)
A New Low Power ing Block Cell For A (1997) (0)
Real-time MPEG-2 to H.264/AVC Transcoding (2014) (0)
Cryptography in RFID Systems (2017) (0)
Industry forum: IoT for real life part I (2016) (0)
A new ATM congestion control scheme for shared buffer switch architectures (1995) (0)
Full-Search Free Intra Predication for H.264 Decoder (2014) (0)
Three-Dimensional Discrete Wavelet (2002) (0)
Reconfigurable testable bit-serial multiplier for DSP applications (1989) (0)
Fraction Control Bus: A New SoC On-chip Communication Architecture Design (2005) (0)
Intelligent Mechanisms for Energy Reduction in Design of Wireless Sensor Networks using Learning Methods (2006) (0)
CEMS-PG: A parametrized algorithm for balanced partitioning and wakeup of power gated circuits (2012) (0)
N2 OC: Neural-Network-on-Chip Architecture (2019) (0)
Hardware Architecture Assist for Critical Components (2014) (0)
A Cost-Efficient Reversible-Based Configurable Ring Oscillator Physical Unclonable Function (2021) (0)
Reduced-Gate Convolutional LSTM Design Using Predictive Coding for Next-Frame Video Prediction (2018) (0)
Distributed computing for signal processing on wireless sensor networks (2010) (0)
Editorial (2013) (0)
The blackjack tutor chip (1999) (0)
Editorial (2006) (0)
A LOW POWER ARCHITECTURE FOR A NEW EFFICIENT ALGOFUTHM BLOCK-MATCHING MOTION ESTIMATION (2000) (0)
Keynote Speech S3-1 - Silicon technologies and communication: challenges and opportunities (2004) (0)
A high-throughput ECC architecture (2012) (0)
Editorial (2003) (0)
An efficient decentralized target localization system for wireless sensor networks (2010) (0)

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Magdy Abd El-aziz. Bayoumi is affiliated with the following schools:

University of Louisiana at Lafayette

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