Malgorzata Marek-Sadowska

Malgorzata Marek-Sadowska's AcademicInfluence.com Rankings

Engineering

#7522

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#8899

Historical Rank

Electrical Engineering

#2376

World Rank

#2487

Historical Rank

Applied Physics

#2648

World Rank

#2690

Historical Rank

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Engineering

Malgorzata Marek-Sadowska's Degrees

PhD Electrical Engineering Warsaw University of Technology
Masters Electrical Engineering Warsaw University of Technology
Bachelors Electrical Engineering Warsaw University of Technology

Why Is Malgorzata Marek-Sadowska Influential?

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According to Wikipedia, Malgorzata Marek-Sadowska is a Polish-American electronics engineer known for her research in VLSI circuit design. She is a professor emeritus of electrical and computer engineering at the University of California, Santa Barbara, a member of the university's Institute for Energy Efficiency, and the director of the VLSI CAD Lab at the university.

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Malgorzata Marek-Sadowska's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Crosstalk reduction for VLSI (1997) (293)
Crosstalk in VLSI interconnections (1999) (169)
Perturb And Simplify: Multi-level Boolean Network Optimizer (1994) (156)
Benefits and costs of power-gating technique (2005) (149)
Efficient circuit clustering for area and power reduction in FPGAs (2002) (138)
Timing driven placement (1989) (122)
Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams (1996) (115)
Logic Synthesis for Engineering Change (1999) (104)
On-chip power-supply network optimization using multigrid-based technique (2003) (102)
Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs (1999) (97)
An Unconstrained Topological Via Minimization Problem for Two-Layer Routing (1984) (83)
Circuit Optimization by Rewiring (1999) (78)
Efficient circuit clustering for area and power reduction in FPGAs (2002) (76)
Clock skew optimization for ground bounce control (1996) (72)
Buffer delay change in the presence of power and ground noise (2003) (69)
Generalized Reed-Muller Forms as a Tool to Detect Symmetries (1996) (69)
Boolean Functions Classification via Fixed Polarity Reed-Muller Forms (1997) (68)
Post-layout Logic Restructuring For Performance Optimization (1997) (67)
An efficient and effective methodology on the multiple fault diagnosis (2003) (66)
Automatic Sizing of Power/Ground (P/G) Networks in VLSI (1989) (62)
Performance Optimization Using Variable-Latency Design Style (2011) (61)
Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration (2011) (59)
Low-power buffered clock tree design (1997) (59)
Rapid layout pattern classification (2011) (57)
Delay and area optimization in standard-cell design (1990) (56)
Aggressor alignment for worst-case crosstalk noise (2001) (56)
Postlayout logic restructuring using alternative wires (1997) (55)
Verifying equivalence of functions with unknown input correspondence (1993) (54)
Designing via-configurable logic blocks for regular fabric (2006) (54)
Fast Boolean optimization by rewiring (1996) (53)
FAR: fixed-points addition & relaxation based placement (2002) (53)
Analysis and methodology for multiple-fault diagnosis (2006) (53)
Layout Driven Logic Synthesis for FPGAs (1994) (51)
Boolean Matching Using Generalized Reed-Muller Forms (1994) (48)
Decomposition of Multiple-Valued Relations (1997) (47)
Graph based analysis of 2-D FPGA routing (1996) (47)
Coping with buffer delay change due to power and ground noise (2002) (45)
Power gating scheduling for power/ground noise reduction (2008) (44)
Delay-fault diagnosis using timing information (2004) (44)
Wire length prediction based clustering and its application in placement (2003) (43)
Wave steering in YADDs: a novel non-iterative synthesis and layout technique (1999) (43)
Multiple fault diagnosis using n-detection tests (2003) (43)
Global Routing for Gate Array (1984) (43)
Multilevel logic synthesis for arithmetic functions (1996) (40)
An Efficient Single-Row Routing Algorithm (1984) (40)
Partitioning sequential circuits on dynamically reconfiguable FPGAs (1998) (40)
Technology Mapping via Transformations of Function Graphs (1992) (39)
Crosstalk Reduction by Transistor Sizing (1999) (39)
Fine granularity clustering for large scale placement problems (2003) (39)
Interconnect complexity-aware FPGA placement using Rent's rule (2001) (38)
Buffer sizing for clock power minimization subject to general skew constraints (2004) (38)
Multilevel fixed-point-addition-based VLSI placement (2005) (37)
Buffer minimization and time-multiplexed I/O on dynamically reconfigurable FPGAs (1997) (37)
Congestion minimization during placement without estimation (2002) (37)
The crossing distribution problem (1991) (37)
Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions (1994) (36)
Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing (1995) (36)
Star test: the theory and its applications (2000) (36)
General skew constrained clock network sizing based on sequential linear programming (2005) (36)
An efficient router for 2-D field programmable gate array (1994) (36)
Cost-free scan: a low-overhead scan path design methodology (1995) (35)
Two-Dimensional Router for Double Layer Layout (1985) (35)
Efficient approach to early detection of lithographic hotspots using machine learning systems and pattern matching (2011) (34)
OPC-Free and Minimally Irregular IC Design Style (2007) (34)
Single-pass redundancy addition and removal (2001) (34)
Minimal Delay Interconnect Design Using Alphabetic Trees (1994) (33)
Gate Sizing to Eliminate Crosstalk Induced Timing Violation (2001) (33)
FPGA interconnect planning (2002) (32)
Worst Delay Estimation in Crosstalk Aware Static Timing Analysis (2000) (32)
Universal logic gate for FPGA design (1994) (31)
Floorplanning with pin assignment (1990) (31)
A Method for Improving Power Grid Resilience to Electromigration-Caused via Failures (2015) (31)
Pre-layout wire length and congestion estimation (2004) (31)
Fast post-placement rewiring using easily detectable functional symmetries (2000) (31)
Stepwise equivalent conductance circuit simulation technique (1993) (30)
mFAR: fixed-points-addition-based VLSI placement algorithm (2005) (30)
Single-Layer Routing for VLSI: Analysis and Algorithms (1983) (30)
Graph based analysis of FPGA routing (1993) (30)
STARBIST: scan autocorrelated random pattern generation (1997) (29)
Interconnect pipelining in a throughput-intensive FPGA architecture (2001) (29)
Timing-Aware Multiple-Delay-Fault Diagnosis (2009) (28)
Engineering change using spare cells with constant insertion (2007) (28)
Synthesis and placement flow for gain-based programmable regular fabrics (2003) (27)
Via-configurable routing architectures and fast design mappability estimation for regular fabrics (2006) (27)
Fine granularity clustering-based placement (2004) (26)
Scan-Encoded Test Pattern Generation for BIST (1997) (26)
Modeling Crosstalk in Resistive VLSI Interconnections (1999) (26)
Detecting context sensitive hot spots in standard cell libraries (2009) (26)
Circuit partitioning with logic perturbation (1995) (26)
Interconnect resource-aware placement for hierarchical FPGAs (2001) (24)
Efficient Delay Calculation in Presence of Crosstalk (2000) (24)
Transistor-level layout of high-density regular circuits (2009) (24)
ECO-Map: Technology remapping for post-mask ECO using simulated annealing (2008) (23)
Is there always performance overhead for regular fabric? (2008) (23)
On designing via-configurable cell blocks for regular fabrics (2004) (23)
SWEC: a stepwise equivalent conductance timing simulator for CMOS VLSI circuits (1991) (23)
An Efficient Mechanism for Performance Optimization of Variable-Latency Designs (2007) (22)
Skew-programmable clock design for FPGA and skew-aware placement (2005) (22)
On-chip power supply network optimization using multigrid-based technique (2003) (22)
Spare Cells With Constant Insertion for Engineering Change (2009) (22)
Diagnosis of hold time defects (2004) (21)
Temporofunctional crosstalk noise analysis (2003) (21)
Efficient static timing analysis in presence of crosstalk (2000) (21)
Gain-based technology mapping for discrete-size cell libraries (2003) (21)
Clock and power gating with timing closure (2003) (20)
T-VEMA: A Temperature- and Variation-Aware Electromigration Power Grid Analysis Tool (2015) (20)
Analysis of process variation's effect on SRAM's read stability (2006) (20)
The crossing distribution problem [IC layout] (1995) (19)
Can pin access limit the footprint scaling? (2012) (19)
Fast postplacement optimization using functional symmetries (2004) (19)
Detecting Symmetric Variables in Boolean Functions using Generalized Reel-Muller Forms (1994) (19)
Minimisation of fixed-polarity AND/XOR canonical networks (1994) (19)
A fast and efficient algorithm for determining fanout trees in large networks (1991) (19)
Closed-Form Crosstalk Noise Metrics for Physical Design Applications (2002) (19)
Layout Generator for Transistor-Level High-Density Regular Circuits (2010) (19)
Functional correlation analysis in crosstalk induced critical paths identification (2001) (18)
A study of netlist structure and placement efficiency (2004) (18)
Test-point insertion: scan paths through functional logic (1998) (17)
Routing for array-type FPGA's (1997) (17)
On computational complexity of a detailed routing problem in two dimensional FPGAs (1994) (17)
Variation-aware electromigration analysis of power/ground networks (2011) (17)
Atomic flux divergence based current conversion scheme for signal line electromigration reliability assessment (2014) (17)
Power supply noise aware workload assignment for multi-core systems (2008) (17)
Power optimal buffered clock tree design (1995) (16)
Delay budgeting in sequential circuit with application on FPGA placement (2003) (16)
RAIN: A Tool for Reliability Assessment of Interconnect Networks—Physics to Software (2018) (16)
Making split-fabrication more secure (2016) (16)
Eliminating false positives in crosstalk noise analysis (2004) (15)
SRAM bit-line electromigration mechanism and its prevention scheme (2013) (15)
Timing-Aware Power-Noise Reduction in Placement (2007) (15)
A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures (2012) (15)
Designing a via-configurable regular fabric (2004) (15)
A new hybrid methodology for power estimation (1996) (15)
Efficient minimization algorithms for fixed polarity AND/XOR canonical networks (1993) (15)
Aggressor alignment for worst-case coupling noise (2000) (15)
A new reasoning scheme for efficient redundancy addition and removal (2003) (14)
Cube diagram bundles: a new representation of strongly unspecified multiple-valued functions and relations (1997) (14)
Wire length prediction in constraint driven placement (2003) (13)
Crosstalk noise in FPGAs (2003) (13)
STAR-ATPG: a high speed test pattern generator for large scan designs (1999) (13)
Issues in Timing Driven Layout (1993) (13)
Delay fault diagnosis for nonrobust test (2006) (12)
Power/ground mesh area optimization using multigrid-based technique [IC design] (2003) (12)
Wire length prediction-based technology mapping and fanout optimization (2005) (12)
Pin assignment for improved performance in standard cell design (1990) (12)
Fast and simple modeling of non-rectangular transistors (2008) (12)
Modeling Crosstalk Induced Delay (2003) (12)
General channel-routing algorithm (1983) (12)
Not necessarily more switches more routability [sic.] (1997) (12)
Sizing Power/Ground Meshes for Clocking and Computing Circuit Components (2002) (11)
Statistical analysis of process variation induced SRAM electromigration degradation (2014) (11)
On designing universal logic blocks and their application to FPGA design (1997) (11)
Theory of wire addition and removal in combinational Boolean networks (2007) (11)
Blech Effect in Interconnects: Applications and Design Guidelines (2015) (11)
A novel high throughput reconfigurable FPGA architecture (2000) (11)
The magic of a via-configurable regular fabric (2004) (11)
A study of decoupling capacitor effectiveness in power and ground grid networks (2009) (11)
Speeding up power estimation by topological analysis (1995) (11)
Who are the alternative wires in your neighborhood? (alternative wires identification without search) (2001) (10)
Vertical Slit Field Effect Transistor in ultra-low power applications (2012) (10)
Timing-aware power noise reduction in layout (2005) (10)
Pre-layout physical connectivity prediction with application in clustering-based placement (2005) (10)
On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits (2011) (10)
Layout effects in fine grain 3D integrated regular microprocessor blocks (2011) (10)
Estimating true worst currents for power grid electromigration analysis (2014) (10)
Power Delivery for Multicore Systems (2011) (9)
Test point insertion: scan paths through combinational logic (1996) (9)
Wave pipelining YADDs-a feasibility study (1999) (9)
An integrated design flow for a via-configurable gate array (2004) (9)
Reliability Analysis and Optimization of Power-Gated ICs (2011) (9)
On-chip em-sensitive interconnect structures (2010) (9)
Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology (2006) (9)
Layout-driven hot-carrier degradation minimization using logic restructuring techniques (2001) (9)
Layout Aware Electromigration Analysis of Power/Ground Networks (2015) (9)
Characterizing VeSFET-Based ICs With CMOS-Oriented EDA Infrastructure (2014) (8)
Logic Synthesis for Testability (1996) (8)
Machine Learning in Simulation-Based Analysis (2015) (8)
Pad Assignment for Power Nets in VLSI Circuits (1987) (8)
Analysis and optimization of power-gated ICs with multiple power gating configurations (2007) (8)
Potential slack budgeting with clock skew optimization (2004) (7)
3D Chips can be cool: Thermal study of VeSFET-based ICs (2013) (7)
Electromigration study of power-gated grids (2009) (7)
Timing-Aware Multiple-Delay-Fault Diagnosis (2008) (7)
Time-multiplexed routing resources for FPGA design (1996) (7)
Improving the Resolution of Single-Delay-Fault Diagnosis (2008) (7)
A study on cell-level routing for VeSFET circuits (2011) (7)
Routing Challenges for Designs With Super High Pin Density (2013) (7)
Switch box routing: a retrospective (1992) (7)
Incorporating Process Variations Into SRAM Electromigration Reliability Assessment Using Atomic Flux Divergence (2016) (6)
In-place delay constrained power optimization using functional symmetries (2001) (6)
An accurate and efficient delay model for CMOS gates in switch-level timing analysis (1990) (6)
Power-Gating Aware Floorplanning (2007) (6)
Clock skew bounds estimation under power supply and process variations (2005) (6)
Power distribution topology design (1995) (6)
Timing driven placement of pads and latches (1992) (6)
Algorithm for wire sizing of Power and Ground Networks in VLSI Designs (1992) (6)
Low power, high throughput network-on-chip fabric for 3D multicore processors (2011) (6)
Minimum-area sequential budgeting for FPGA (2003) (6)
Functional scan chain testing (1998) (6)
Crosstalk minimization for multiple clock tree routing (2002) (5)
Non-Uniform Temperature Distribution in Interconnects and Its Impact on Electromigration (2019) (5)
Clock network sizing via sequential linear programming with time-domain analysis (2004) (5)
mFAR: Multilevel Fixed-Points Addition-Based VLSI Placement (2007) (5)
Logic rectification and synthesis for engineering change (1995) (5)
Perturb and simplify: optimizing circuits with external don't cares (1996) (5)
Circuit clustering using graph coloring (1999) (5)
A study of reliability issues in clock distribution networks (2008) (5)
Efficient Closed-Form Crosstalk Delay Metrics (2002) (5)
Wave steering to integrate logic and physical syntheses (2003) (5)
Timing analysis considering IR drop waveforms in power gating designs (2008) (4)
Atomic flux divergence-based AC electromigration model for signal line reliability assessment (2015) (4)
Perturb and Simplify: Optimizing Combinational Circuits with External Don't Cares (1996) (4)
Wave steered FSMs (2000) (4)
Multilevel expansion-based VLSI placement with blockages (2004) (4)
Individual wire-length prediction with application to timing-driven placement (2004) (4)
Wave-steering one-hot encoded FSMs (2000) (4)
Semi-individual wire-length prediction with application to logic synthesis (2006) (4)
Efficient ordered binary decision diagrams minimization based on heuristics of cover pattern processing (1993) (4)
Bu er Minimization and Time-multiplexed I / O on Dynamically Recon gurable FPGAs (1997) (4)
An interconnect insensitive linear time-varying driver model for static timing analysis (2005) (3)
Pipelining sequential circuits with wave steering (2004) (3)
Performance study of VeSFET-based, high-density regular circuits (2010) (3)
OBDD Minimization Based on Two-Level Representation of Boolean Functions (2000) (3)
Electromigration and voltage drop aware power grid optimization for power gated ICs (2007) (3)
PITIA: an FPGA for throughput-intensive applications (2003) (3)
Statistical static timing analysis flow for transistor level macros in a microprocessor (2010) (3)
An efficient algorithm for local don't care sets calculation (1995) (3)
Capturing input switching dependency in crosstalk noise modeling (2000) (3)
Technology mapping and circuit depth optimization for field programmable gate arrays (1993) (3)
A hybrid methodology for switching activities estimation (1998) (3)
Automated Routing for VLSI: Kuh's Group Contributions (2016) (3)
Incremental delay change due to crosstalk noise (2002) (3)
Power/Ground Supply Network Optimization for Power-Gating (2006) (3)
A crosstalk aware two-pin net router (2003) (2)
Post-placement lithographic hotspot detection and removal in one-dimensional gridded designs (2012) (2)
Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics (2005) (2)
A New Accurate and Efficient Timing Simulator (1992) (2)
Designing VeSFET-based ICs with CMOS-oriented EDA infrastructure (2013) (2)
Using Temporal and Functional Information in Crosstalk Aware Static Timing Analysis (2002) (2)
A fast, fully verifiable, and hardware predictable ASIC design methodology (2016) (2)
Circuit Partitioning for Behavioral Full Chip Simulation Modeling of Analog and Mixed Signal Circuits (2014) (2)
Metrics for characterizing machine learning-based hotspot detection methods (2011) (2)
Sequential delay budgeting with interconnect prediction (2003) (2)
AFD-based method for signal line EM reliability evaluation (2016) (2)
Performance assessment of VeSFET-based SRAM (2015) (2)
Latency and latch count minimization in wave steered circuits (2001) (2)
Minimizing coupling jitter by buffer resizing for coupled clock networks (2003) (2)
ATPG-based logic synthesis: an overview (2002) (2)
Minimizing Inter-Clock Coupling Jitter (2003) (2)
High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators (2018) (2)
On Optimal Kernel Size for Integrated CPU-GPUs — A Case Study (2014) (2)
Assessing circuit-level properties of vesfet-based ics (2013) (1)
On two-dimensional fpga routing: theoretical analysis and novel effective solutions (1994) (1)
System-level floorplan-aware analysis of integrated CPU-GPUs (2014) (1)
A Test Synthesis Approach To Reducing Ballast Dft Overhead (1997) (1)
. " Sis: a System for Sequential Circuit Synthesis, " Report M92/41, A) Shallow Reconvergant Fanout A) Deep Reconvergant Fanout (1)
A congestion-driven placement framework with local congestion prediction (2005) (1)
On old and new routing problems (2011) (1)
Multilevel vlsi placement in very deep sub-micron technology (2004) (1)
Pre-layout Physical Connectivity Prediction with Applications in Clustering , Placement and Logic Synthesis (2005) (1)
CUBE DIAGRAM BUNDLES: A NEW REPRESENTATION AND RELATIONS OF STRONGLY UNSPECIFIED MULTIPLE-VALUED FUNCTIONS (1997) (1)
Power Distribution Synthesis for VLSI (1998) (1)
Sequential permissible functions and their application to circuit optimization (1996) (1)
AFD-based model of EM lifetime and reservoir effect (2016) (1)
Perturb and Simplify: Multilevel Boolean (1996) (1)
Analysis of Heuristic Reasoning for the Visualization of CAD Quadratic (1989) (1)
On Designing Via-Configurra le eeso Blocks for Fabrics (2004) (1)
A Global Routing Technique for Wave-Steering Design Methodology (2001) (1)
A Delay Metric for RC Circuits Based on the Weibull Distribution (2004) (1)
RAIN (2018) (1)
An efficient and accurate algorithm for computing RC current response with applications to EM reliability evaluation (2016) (0)
Interconnect design algorithms for high performance vlsi (1996) (0)
UNIVERSITY OF CALIFORNIA Santa Barbara Interconnect Fabric Reconfigurability for Network on Chip A Thesis submitted in partial satisfaction of the requirements for the degree Master of Science in Electrical and Computer Engineering by (2015) (0)
A new approach to routing of two-layer printed circuit board (1981) (0)
Starbist Scan Autocorrelated Random Pattern Generation (1997) (0)
ISPD 2023 Lifetime Achievement Award Bio (2023) (0)
Tance and Unit Wire Resistance. 3 (1993) (0)
On Improved FPGA Greedy Routing Architectures (Special Section on VLSI Design and CAD Algorithms) (1998) (0)
Three-Dimensional Chips Can Be Cool: Thermal Study of VeSFET-Based 3-D Chips (2015) (0)
Session details: New approaches to physical design problems (2005) (0)
Routing on regular segmented 2-D FPGAs (1995) (0)
Multilevel Fixed-Point-Addition-Based (2005) (0)
Session details: Floorplanning (2004) (0)
On Regular Segmented 2-D FPGA Routing (Special Section on VLSI Design and CAD Algorithms) (1997) (0)
Session details: Crosstalk Noise (2002) (0)
A via-configurable regular fabric for nanometer technology (2005) (0)
Session details: Session 2: Issues in Timing (2003) (0)
Session details: Advanced techniques and technologies (2005) (0)
On the Verification of Function Equivalence with unknown Input Correspondence (1994) (0)
RAIN: a tool for reliability assessment of interconnect networks - physics to software (2018) (0)
Closed-Form Crosstalk Noise Delay Metrics (2003) (0)
Clock Network Sizing in Presence of Power Supply Noise (2004) (0)
Technology Decomposition (2004) (0)
Reconfiguration for logic reuse (1998) (0)
Logic and physical synthesis techniques for engineering change orders (ecos) (2011) (0)
Special Section on VLSI Design and CAD Algorithms (1995) (0)
Layout optimization through robust pattern learning and prediction in SADP gridded designs (2012) (0)
Scan paths through functional logic (1996) (0)

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Published Works

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