Marios Papaefthymiou | Academic Influence

Marios Papaefthymiou's AcademicInfluence.com Rankings

Marios Papaefthymiou

Engineering

#7634

World Rank

#9024

Historical Rank

Electrical Engineering

#2774

World Rank

#2917

Historical Rank

Applied Physics

#3285

World Rank

#3369

Historical Rank

engineering Degrees

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Engineering

Marios Papaefthymiou's Degrees

PhD Electrical Engineering Stanford University
Masters Electrical Engineering Stanford University
Bachelors Electrical Engineering Stanford University

Why Is Marios Papaefthymiou Influential?

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According to Wikipedia, Marios Papaefthymiou is the Ted and Janice Smith Family Foundation dean of the Donald Bren School of Information and Computer Sciences at the University of California, Irvine, United States. He previously served as chair of computer science and engineering at the University of Michigan, Ann Arbor, MI. He was named Fellow of the Institute of Electrical and Electronics Engineers in 2014 for contributions to the design of adiabatic circuits for high-performance computing.

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Marios Papaefthymiou's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Precomputation-based Sequential Logic Optimization For Low Power (1994) (356)
Computational sprinting (2012) (176)
True single-phase adiabatic circuitry (2001) (88)
Energy-Efficient GHz-Class Charge-Recovery Logic (2007) (87)
A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs (2007) (84)
Charge-recovery computing on silicon (2005) (73)
Optimizing two-phase, level-clocked circuitry (1997) (70)
True single-phase energy-recovering logic for low-power, high-speed VLSI (1998) (63)
Low power parallel multiplier design for DSP applications through coefficient optimization (1999) (63)
Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor (2012) (61)
Computational sprinting on a hardware/software testbed (2013) (59)
Analytical macromodeling for high-level power estimation (1999) (58)
Single-phase source-coupled adiabatic logic (1999) (53)
DelaY: An Efficient Tool for Retiming with Realistic Delay Modeling (1995) (52)
Understanding retiming through maximum average-weight cycles (1991) (51)
Figure-of-merit for phase-change materials used in thermal management (2016) (51)
Block-based multiperiod dynamic memory design for low data-retention power (2003) (48)
A true single-phase energy-recovery multiplier (2003) (46)
Fixed-phase retiming for low power design (1996) (44)
Resonant-Clock Latch-Based Design (2008) (43)
Stochastic Analysis of Gang Scheduling in Parallel and Distributed Systems (1996) (40)
A Gang Scheduling Design for Multiprogrammed Parallel Computing Environments (1996) (40)
TIM: A Timing Package for Two-Phase, Level-Clocked Circuitry (1993) (38)
Performance Evaluation of Gang Scheduling for Parallel and Distributed Multiprogramming (1997) (36)
Implementing and evaluating adiabatic arithmetic units (1996) (36)
A Markov chain sequence generator for power macromodeling (2002) (36)
Reconfigurable low energy multiplier for multimedia system design (2000) (33)
Utilizing Dark Silicon to Save Energy with Computational Sprinting (2013) (33)
187 MHz Subthreshold-Supply Charge-Recovery FIR (2010) (32)
Reduced delay uncertainty in high performance clock distribution networks (2003) (32)
Retiming and clock scheduling for digital circuit optimization (2002) (31)
A resonant clock generator for single-phase adiabatic systems (2001) (31)
Dynamic Memory Design for Low Data-Retention Power (2000) (30)
Incorporation of input glitches into power macromodeling (2002) (29)
On-chip phase change heat sinks designed for computational sprinting (2014) (29)
A true single-phase 8-bit adiabatic multiplier (2001) (29)
A static power estimation methodology for IP-based design (2001) (29)
Energy recovering static memory (2002) (28)
Implementing parallel shortest-paths algorithms (1994) (27)
1.32GHz high-throughput charge-recovery AES core with resistance to DPA attacks (2015) (26)
HyPE: hybrid power estimation for IP-based systems-on-chip (2005) (25)
Design of a high-throughput low-power IS95 Viterbi decoder (2002) (24)
Understanding retiming through maximum average-delay cycles (2005) (23)
Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic (2012) (23)
Practical repeater insertion for low power: what repeater library do we need? (2004) (23)
A 225 MHz resonant clocked ASIC chip (2003) (22)
A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty (2001) (21)
Computing Strictly-Second Shortest Paths (1997) (21)
Asymptotically efficient retiming under setup and hold constraints (1998) (21)
Maximizing performance by retiming and clock skew scheduling (1999) (21)
Energy recovering ASIC design (2003) (19)
Block-based multi-period refresh for energy efficient dynamic memory (2001) (19)
Design and Evaluation of Adiabatic Arithmetic Units (1997) (19)
An analysis of gang scheduling for multiprogrammed parallel computing environments (1996) (16)
Power-complexity analysis of pipelined VLSI FFT architectures for low energy wireless communication applications (1999) (15)
A 187MHz subthreshold-supply robust FIR filter with charge-recovery logic (2009) (15)
Design, verification, and test of a true single-phase 8-bit adiabatic multiplier (2001) (15)
Optimizing computations for effective block-processing (2000) (15)
RF2: A 1GHz FIR Filter with Distributed Resonant Clock Generator (2007) (14)
Design of a 20-mb/s 256-state Viterbi decoder (2003) (14)
Retiming edge-triggered circuits under general delay models (1997) (13)
A Timing Analysis and Optimization System for Level-Clocked Circuitry (1993) (13)
Two-phase resonant clock distribution (2005) (13)
Designing for Responsiveness with Computational Sprinting (2013) (13)
Empirical evaluation of timing and power in resonant clock distribution (2004) (13)
Fine-grain real-time reconfigurable pipelining (2003) (13)
Edge-triggering vs. two-phase level-clocking (1993) (12)
ON RETIMING SYNCHRONOUS CIRCUITRY AND MIXED-INTEGER OPTIMIZATION (1990) (12)
Skew spreading for peak current reduction (2007) (11)
Experimental evaluation of resonant clock distribution (2004) (11)
Rethinking Numerical Representations for Deep Neural Networks (2017) (11)
Boost logic : a high speed energy recovery circuit family (2005) (11)
A resonant-clock 200MHz ARM926EJ-STM microcontroller (2009) (11)
900MHz to 1.2GHz Two-Phase Resonant Clock Network with Programmable Driver and Loading (2006) (11)
A Markov chain sequence generator for power macromodeling (2004) (10)
2.07 GHz floating-point unit with resonant-clock precharge logic (2010) (10)
A 5.5GS/s 28mW 5-bit flash ADC with resonant clock distribution (2011) (9)
HyPE: hybrid power estimation for IP-based programmable systems (2003) (9)
27.6 An 821MHz 7.9Gb/s 7.3pJ/b/iteration charge-recovery LDPC decoder (2014) (9)
Resonant clock generator for single-phase adiabatic systems (2001) (8)
A statistical model of input glitch propagation and its application in power macromodeling (2002) (7)
Pitfalls of Accurately Benchmarking Thermally Adaptive Chips (2014) (7)
Efficient Block Scheduling to Minimize Context Switching Time for Programmable Embedded Processors (1999) (7)
A charge-recovery 600MHz FIR filter with 1.5-cycle latency overhead (2009) (7)
A reconfigurable pipelined IDCT for low-energy video processing (2000) (7)
Constant-load energy recovery memory for efficient high-speed operation (2004) (7)
RIP: an efficient hybrid repeater insertion scheme for low power (2005) (6)
Eecient Pipelining of Level-clocked Circuits with Min-max Propagation Delays (1995) (6)
Efficient retiming under a general delay model (1995) (6)
20.7 A 13.8µW binaural dual-microphone digital ANSI S1.11 filter bank for hearing aids with zero-short-circuit-current logic in 65nm CMOS (2017) (6)
A 1.25pJ/bit 0.048mm2 AES core with DPA resistance for IoT devices (2017) (5)
Optimizing systems for effective block-processing: the k-delay problem (1996) (5)
Energy recovery design for low-power ASICs (2003) (5)
A 0.8-1.2GHz Single-Phase Resonant-Clocked FIR Filter with Level-Sensitive Latches (2007) (5)
Synthesis of resonant clock networks supporting dynamic voltage / frequency scaling (2015) (4)
Minimizing sensitivity to delay variations in high-performance synchronous circuits (1999) (4)
Clock tree layout design for reduced delay uncertainty (2004) (4)
Memory Assignment for Multiprocessor Caches through Grey Coloring (1994) (3)
Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling (2016) (3)
A GHz-class charge recovery logic (2005) (3)
Pipelined DSP design with a true single-phase energy-recovering logic style (1999) (3)
Parallelizing post-placement timing optimization (2006) (3)
A 934MHz 9Gb/s 3.2pJ/b/iteration charge-recovery LDPC decoder with in-package inductors (2015) (3)
A 0.23mW Heterogeneous Deep-Learning Processor Supporting Dynamic Execution of Conditional Neural Networks (2018) (2)
Optimizing Systems for Effective Block-Processing: Optimizing Systems for Effective Block-Processing: (1996) (2)
A 5.5GHz 0.84TOPS/mm2 neural network engine with stream architecture and resonant clock mesh (2016) (1)
Resonant clock design for a power-efficient high-volume x86–64 microprocessor (2012) (1)
Symbolic debugging of globally optimized behavioral specifications (2000) (1)
An algorithm for geometric load balancing with two constraints (2004) (1)
A synchronous interface for SoCs with multiple clock domains (2004) (1)
Architectural-level design of high-performance, energy-efficient vlsi systems (1996) (1)
Pipelined DSP Design with a True Single-PhaseEnergy-Re overing Logi StyleSuhwan (1999) (0)
Session details: Latency tolerance and asynchronous design (2004) (0)
Technologies for Low-Power VLSI Design (1999) (0)
Symbolic debugging of embedded hardware and software (2001) (0)
Dynamic processor management for multiprogrammed parallel and distributed systems (1998) (0)
Session details: Micro-architectural techniques (2005) (0)
HYPE : A Hybrid Power Estimation Method for Programmable Systems (0)
Charge-Recovery LDPC Decoder (2014) (0)
Multi-Session Partitioning for Parallel Timing Optimization (2005) (0)
Towards An Efficient Low Frequency Energy Recovery Dynamic Logic (2005) (0)
Euclidean Tsp (part I) (1996) (0)
Fast, efficient, recovering, and irreversible (2005) (0)
Design Technologies for Energy-Efficient VLSI Systems (2007) (0)
On-chip synchronous communication between clock domains with quotient frequencies (2007) (0)
Low-Energy VLSI Circuit Architectures (2003) (0)
Drivers with low power consumption with energy recovery (2003) (0)
Resonant System Design with Coarse Grained Pipelines (0)

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