Mark D. Hill | Academic Influence

Mark D. Hill's AcademicInfluence.com Rankings

Mark D. Hill

Computer Science

#1635

World Rank

#1690

Historical Rank

Database

#2612

World Rank

#2734

Historical Rank

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Computer Science

Mark D. Hill's Degrees

PhD Computer Science University of California, Berkeley
Masters Computer Science University of California, Berkeley

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Why Is Mark D. Hill Influential?

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According to Wikipedia, Mark D. Hill is a computer scientist and professor at the University of Wisconsin–Madison. He has been cited over 27,000 times. He is the John P. Morgridge Professor and Gene M. Amdahl Professor of Computer Science. Hill specializes in computer architecture, parallel computing, memory systems, and performance evaluation.

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Mark D. Hill's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

The gem5 simulator (2011) (4266)
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset (2005) (1635)
Amdahl's Law in the Multicore Era (2008) (1285)
LogTM: log-based transactional memory (2006) (716)
Evaluating Associativity in CPU Caches (1989) (631)
Weak ordering—a new definition (1990) (590)
DBMSs on a Modern Processor: Where Does Time Go? (1999) (565)
A Primer on Memory Consistency and Cache Coherence (2012) (431)
A "flight data recorder" for enabling full-system multiprocessor deterministic replay (2003) (410)
Weaving Relations for Cache Performance (2001) (408)
The Wisconsin Wind Tunnel: virtual prototyping of parallel computers (1993) (408)
Cache-conscious structure layout (1999) (374)
SafetyNet: improving the availability of shared memory multiprocessors with global checkpoint/recovery (2002) (367)
LogTM-SE: Decoupling Hardware Transactional Memory from Caches (2007) (364)
Efficient virtual memory for big memory servers (2013) (304)
Token Coherence: decoupling performance and correctness (2003) (302)
Page placement algorithms for large real-indexed caches (1992) (299)
Why on-chip cache coherence is here to stay (2012) (278)
A case for direct-mapped caches (1988) (269)
Performance Pathologies in Hardware Transactional Memory (2007) (256)
Surpassing the TLB performance of superpages with less operating system support (1994) (253)
Aspects of cache memory and instruction buffer performance (1987) (251)
Efficiently enabling conventional block sizes for very large die-stacked DRAM caches (2011) (246)
A Unified Formalization of Four Shared-Memory Models (1993) (237)
gem5-gpu: A Heterogeneous CPU-GPU Simulator (2015) (221)
Virtual hierarchies to support server consolidation (2007) (204)
Cache performance of the SPEC92 benchmark suite (1993) (203)
Supporting nested transactional memory in logTM (2006) (199)
What is scalability? (1990) (196)
Wisconsin Wind Tunnel II: a fast, portable parallel architecture simulator (2000) (194)
An Analysis of Persistent Memory Use with WHISPER (2017) (188)
A serializability violation detector for shared-memory server programs (2005) (182)
Weak ordering-a new definition (1990) (176)
Design Decisions in SPUR (1986) (171)
Multiprocessors Should Support Simple Memory-Consistency Models (1998) (170)
Cooperative shared memory: software and hardware for scalable multiprocessors (1993) (169)
Rerun: Exploiting Episodes for Lightweight Memory Race Recording (2008) (165)
A Comparison of Trace-Sampling Techniques for Multi-Megabyte Caches (1994) (156)
Full-system timing-first simulation (2002) (153)
Tradeoffs in Supporting Two Page Sizes (1992) (151)
Application-specific protocols for user-level shared memory (1994) (151)
Simulating a $2M Commercial Server on a $2K PC (2003) (146)
Implementing Signatures for Transactional Memory (2007) (144)
Detecting data races on weak memory systems (1991) (144)
Supporting x86-64 address translation for 100s of GPU lanes (2014) (140)
Data page layouts for relational databases on deep memory hierarchies (2002) (139)
Redundant Memory Mappings for fast access to large memories (2015) (138)
A model for estimating trace-sample miss ratios (1991) (134)
Heterogeneous system coherence for integrated CPU-GPU systems (2013) (127)
Using destination-set prediction to improve the latency/bandwidth tradeoff in shared-memory multiprocessors (2003) (125)
TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory (2008) (124)
Slack: maximizing performance under technological constraints (2002) (124)
Challenges in Computer Architecture Evaluation (2003) (124)
Using prediction to accelerate coherence protocols (1998) (121)
Efficient support for irregular applications on distributed-memory machines (1995) (119)
Inexpensive Implementations Of Set-Associativity (1989) (115)
A regulated transitive reduction (RTR) for longer memory race recording (2006) (114)
Improving multiple-CMP systems using token coherence (2005) (113)
Making Pointer-Based Data Structures Cache Conscious (2000) (111)
Experimental evaluation of on-chip microprocessor cache memories (1984) (111)
Programming for Different Memory Consistency Models (1992) (110)
Coherent Network Interfaces for Fine-Grain Communication (1996) (105)
Multicast snooping: a new coherence method using a multicast address network (1999) (104)
An in-cache address translation mechanism (1986) (98)
Cost-Effective Parallel Computing (1995) (95)
Readings in computer architecture (2000) (93)
Heterogeneous-race-free memory models (2014) (92)
Comparison of hardware and software cache coherence schemes (1991) (90)
Efficient Memory Virtualization: Reducing Dimensionality of Nested Page Walks (2014) (88)
Lamport clocks: verifying a directory cache-coherence protocol (1998) (82)
Relaxed consistency and coherence granularity in DSM systems: a performance evaluation (1997) (82)
Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol (2002) (82)
Evaluating Non-deterministic Multi-threaded Commercial Workloads (2001) (80)
Implementing stack simulation for highly-associative memories (1991) (79)
Reducing memory reference energy with opportunistic virtual caching (2012) (74)
A new page table for 64-bit address spaces (1995) (74)
Calvin: Deterministic or not? Free will to choose (2011) (73)
Cooperative shared memory: software and hardware for scalable multiprocessor (1992) (73)
Cache performance for selected SPEC CPU2000 benchmarks (2001) (69)
Using interaction costs for microarchitectural bottleneck analysis (2003) (69)
Bandwidth adaptive snooping (2002) (66)
Supporting Very Large DRAM Caches with Compound-Access Scheduling and MissMap (2012) (66)
QuickRelease: A throughput-oriented approach to release consistency on GPUs (2014) (62)
Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing (2001) (61)
Notary: Hardware techniques to enhance signatures (2008) (60)
Coherence Ordering for Ring-based Chip Multiprocessors (2006) (60)
Wisconsin Architectural Research Tool Set (1993) (57)
Architecture of a VLSI instruction cache for a RISC (1983) (55)
Border control: Sandboxing accelerators (2015) (54)
Implementing Sequential Consistency in Cache-Based Systems (1990) (54)
Karma: scalable deterministic record-replay (2011) (53)
Agile Paging: Exceeding the Best of Nested and Shadow Paging (2016) (53)
Energy-efficient address translation (2016) (53)
Mechanisms For Cooperative Shared Memory (1993) (53)
Performance Implications of Tolerating Cache Faults (1993) (52)
Facile: a language and compiler for high-performance processor simulators (2001) (50)
Cache coherence techniques for multicore processors (2008) (50)
MOD: Minimally Ordered Durable Datastructures for Persistent Memory (2019) (47)
BadgerTrap: a tool to instrument x86-64 TLB misses (2014) (47)
Timestamp snooping: an approach for extending SMPs (2000) (46)
Devirtualizing Memory in Heterogeneous Systems (2018) (45)
Aspects of Cache Memory and Instruction (1987) (45)
Tempest: a substrate for portable parallel programs (1995) (42)
Implementing Fine-grain Distributed Shared Memory on Commodity SMP Workstations (1996) (40)
SPUR: A VLSI Multiprocessor Workstation (1985) (40)
Using Lamport clocks to reason about relaxed memory models (1999) (38)
Address translation mechanisms in network interfaces (1998) (38)
An evaluation of directory protocols for medium-scale shared-memory multiprocessors (1994) (37)
Token Coherence: A New Framework for Shared-Memory Multiprocessors (2003) (36)
Synchronization Using Remote-Scope Promotion (2015) (35)
Gables: A Roofline Model for Mobile SoCs (2019) (35)
Making Network Interfaces Less Peripheral (1998) (35)
Timestamp snooping: an approach for extending SMPs (2000) (35)
Range Translations for Fast Virtual Memory (2016) (34)
Thread-Level Transactional Memory (2005) (34)
Interaction cost and shotgun profiling (2004) (34)
Sirocco: cost-effective fine-grain distributed shared memory (1998) (33)
Two hardware-based approaches for deterministic multiprocessor replay (2009) (31)
Fast Checkpoint/Recovery to Support Kilo-Instruction Speculation and Hardware Fault Tolerance (2000) (31)
Cache performance of the integer SPEC benchmarks on a RISC (1990) (29)
Cache considerations for multiprocessor programmers (1990) (29)
Arch2030: A Vision of Computer Architecture Research over the Next 15 Years (2016) (28)
The impact of data transfer and buffering alternatives on network interface design (1998) (28)
Eecient Support for Irregular Applications on Distributed-memory Machines (1995) (27)
Dynamic verification of end-to-end multiprocessor invariants (2003) (27)
Use of superpages and subblocking in the address translation hierarchy (1995) (26)
Toward GPUs being mainstream in analytic processing: An initial argument using simple scan-aggregate queries (2015) (24)
A Survey of User-Level Network Interfaces for System Area Networks (1997) (23)
Improving Pointer-Based Codes Through Cache-Conscious Data Placement (1998) (23)
Specifying system requirements for memory consistency models (1993) (22)
OS Support for Virtualizing Hardware Transactional Memory (2008) (22)
DBMSs on modern processors : Where does time go ? (1999) (21)
Accelerator-level parallelism (2019) (21)
Sufficient Conditions for Implementing theData-Race-Free-1 Memory Model, * (1992) (21)
A Case for Deconstructing Hardware Transactional Memory Systems (2007) (21)
Optimistic Simulation of Parallel Architectures Using Program Executables (1996) (20)
On the Spectre and Meltdown Processor Security Vulnerabilities (2019) (20)
Single-Threaded vs. Multithreaded: Where Should We Focus? (2007) (18)
Design Challenges for High-Performance Network Interfaces - Guest Editors' Introduction (1998) (18)
Cooperative Shared Memory: Software and Hardware Support for Scalable Multiprocesors (1992) (17)
Fast and Portable Parallel Architecture Simulators: Wisconsin Wind Tunnel II (1995) (17)
First-generation Memory Disaggregation for Cloud Platforms (2022) (17)
Signatures in transactional memory systems (2009) (16)
Weak ordering- a new definition and some implications (1989) (15)
Implications of Emerging 3D GPU Architecture on the Scan Primitive (2015) (14)
21st century computer architecture (2014) (14)
Crossing Guard: Mediating Host-Accelerator Coherence Interactions (2017) (14)
Lamport Clocks : Reasoning About Shared Memory Correctness (1998) (14)
Retrospective on Amdahl's Law in the Multicore Era (2017) (13)
Accelerating Science: A Computing Research Agenda (2016) (13)
Where Is Software Headed? A Virtual Roundtable (1995) (12)
Virtual Hierarchies (2008) (12)
BSPlib : The BSP Programming (2010) (12)
Pond: CXL-Based Memory Pooling Systems for Cloud Platforms (2022) (12)
A case for making network interfaces less peripheral (1997) (11)
A Unified Formalization of (1993) (11)
A Wiki for discussing and promoting best practices in research (2006) (11)
Lamport Clocks: Reasoning About Shared Memory Correctness1 (1999) (11)
Using Prediction to Accelerate Coherence (1998) (11)
A system-level specification framework for I/O architectures (1999) (11)
Security Implications of Third-Party Accelerators (2016) (10)
StealthTest: Low Overhead Online Software Testing Using Transactional Memory (2009) (10)
Walking Four Machines By The Shore (2001) (10)
Don't Persist All : Efficient Persistent Data Structures (2019) (10)
Applying programming language implementation techniques to processor simulation (2000) (9)
When to use 3D Die-Stacked Memory for Bandwidth-Constrained Big Data Workloads (2016) (9)
Revisiting virtual memory (2013) (9)
Scalability and Its Application to Multicube (1989) (8)
FreshCache: Statically and dynamically exploiting dataless ways (2013) (8)
Thermodynamic Computing (2019) (8)
A Hardware Memory Race Recorder for Deterministic Replay (2007) (7)
Revisiting Stack Caches for Energy Efficiency (2014) (7)
A VLSI chip set for a multiprocessor workstation. I. An RISC microprocessor with coprocessor interface and support for symbolic processing (1989) (7)
Memory Hierarchy Aspects of a Multiprocessor RISC: Cache and Bus Analyses (1985) (6)
Solving microstructure electrostatics on a proposed parallel computer (1995) (6)
Sufficient System Requirements for Supporting the PLpc Memory Model (1993) (6)
Race recording for multithreaded deterministic replay using multiprocessor hardware (2006) (6)
Retrospective: weak ordering—a new definition (1998) (5)
Architecture-conscious database systems (2000) (5)
Is transactional memory an oxymoron? (2008) (5)
Safe and efficient supervised memory systems (2011) (5)
The Wisconsin Wind Tunnel project: an annotated bibliography (1994) (5)
CMP Directory Coherence: One Granularity Does Not Fit All (2013) (4)
Parallel Computer Research in the Wisconsin Wind Tunnel Project (1996) (4)
Design and evaluation of network interfaces for system area networks (1998) (4)
Multiprocessors Should Support Simple Memory- Consistency Models Uniprocessor Memory (1998) (4)
A vision to compute like nature: thermodynamically (2021) (3)
Cryogenic magnetic properties of iron garnets diluted with Al-In and Ca-V-In combinations (2001) (3)
Token Coherence: Low-Latency Coherence on Unordered Interconnects (2003) (3)
Sequential Consistency for Heterogeneous-Race-Free: Programmer-centric Memory Models for Heterogeneous Platforms (2013) (3)
A vision to compute like nature (2021) (3)
Democratizing Design for Future Computing Platforms (2017) (3)
Fine-grain distributed shared memory on clusters of workstations (1998) (3)
Three Other Models of Computer System Performance (2019) (3)
Opportunities beyond single-core microprocessors (2009) (3)
A 200 MHz RISC microprocessor with 128 kB on-chip caches (1997) (3)
HW/SW approaches for RISC-V code size reduction (2020) (3)
Agile Paging for Efficient Memory Virtualization (2017) (3)
Interaction cost: for when event counts just don't add up (2004) (3)
Acoherent shared memory (2012) (2)
Nanotechnology-inspired Information Processing Systems of the Future (2020) (2)
Proprietary versus Open Instruction Sets (2016) (2)
Probabilistic Directed Writebacks for Exclusive Caches (2016) (2)
Advancing Computing's Foundation of US Industry & Society (2021) (2)
Correction to Evaluating Associativity in CPU Caches (1991) (2)
Determination of Disconnecting Switch Ratings for the Pennsylvania-New Jersey-Maryland Interconnection (1972) (2)
Using speculation to simplify multiprocessor design (2004) (2)
Advanced Cyberinfrastructure for Science, Engineering, and Public Policy (2017) (2)
Computer Sciences Department Amdahl's Law in the Multicore Era (2007) (2)
Research directions for 21st century computer systems: asplos 2013 panel (2013) (2)
1 ACCELERATING SCIENCE : A COMPUTING RESEARCH AGENDA (2016) (1)
21st century computer architecture keynote at 2014 international conference on supercomputing (ICS) (2014) (1)
MultiView and Millipage - Fine-Grain Sharing in Page-Based DSMs (1999) (1)
Design Tradeoffs in CXL-Based Memory Pools for Public Cloud Platforms (2023) (1)
Challenges to Keeping the Computer Industry Centered in the US (2017) (1)
Technical perspective: Why 'correct' computers can leak your information (2020) (1)
A National Discovery Cloud: Preparing the US for Global Competitiveness in the New Era of 21st Century Digital Transformation (2021) (1)
Evaluating a $2M Commercial Server on a $2K PC and Related Challenges (2003) (1)
An Improved "Flight Data Recorder" of Shared Memory Races (2007) (1)
Portably Supporting Parallel Programming Languages (1995) (1)
Single-threaded vs. multi-threaded (2007) (1)
Hardware support for efficient transactional and supervised memory systems (2010) (1)
Guest Editor's Introduction: Hot Chips II Symposium (1991) (1)
Opportunities and Challenges for Next Generation Computing (2020) (1)
Advanced symmetric multiprocessor architecture (1997) (0)
Preliminary Draft of SPAA ’ 99 Submission A System-Level Specification Framework for I / O Ar chitectures 1 (1999) (0)
Hybrid memory access protocol in a data processing system with a distributed, shared memory (1997) (0)
Method and apparatus for a directory-less protocol memory access in a computer system having a distributed shared memory (1997) (0)
Programming Research GroupSTABILITY OF COMMUNICATION PERFORMANCE INPRACTICE : FROM THE CRAY T 3 E TO NETWORKS OFWORKSTATIONSJonathan (1995) (0)
Simple Memory- Consistency Models (1998) (0)
Devirtualizing virtual memory for heterogeneous systems (2017) (0)
Hierarchical data processing system with symmetrical multiprocessors (1997) (0)
DRAM CP $ Tag Control Logic & Bus Interface Block 2 Status SRAM PP $ from LANai BufferRegs (1996) (0)
Blizzard and Paradyn: Infrastructure and Scalable Tools for Multi-Paradigm Parallel Computers (1998) (0)
Programming Heterogeneous Computers and Improving Inter-Node Communication Across Xeon Phis (2016) (0)
Efficient Durability for Lock-based Code (2018) (0)
A Blockin Blockin Throughput-‐oriented Blockin Blockin Approach Blockin Blockin to Blockin Blockin Release Blockin Blockin Consistency Blockin Blockin on Blockin Blockin Gpus (2014) (0)
Programming Research Group PRACTICAL BARRIER (1996) (0)
Cybersecurity: Transcending Physics, Technology, and Society (2019) (0)
Reflections and Research Advice Upon Receiving the 2019 Eckert-Mauchly Award (2019) (0)
With the advent of distributed computing, developers are increasingly concerned with the efficient movement of data through the network and, in particular, the design of efficient network interfaces. Design Challenges for High-Performance Network Interfaces (1998) (0)
The Tempest approach to distributed shared memory (1996) (0)
Next Generation Computer Hardware (2020) (0)
How computer architecture trends may affect future distributed systems: from infiniBand clusters to inter-processor speculation (abstract) (2000) (0)
Hot Chips II Symposium (2001) (0)
Mechanisms for Cooperative Shared Memory of Wisconsin Graduate School Grant, Wisconsin Alumni Re- Search Foundation Fellowship and Donations from A.t.&t. Bell Laboratories and Digital Equipment Corporation. Our Thinking Machines Cm-5 Was Purchased through Nsf Institu- Tional Infrastructure Grant No. (1993) (0)
A future of parallel computer architectures (2004) (0)
Cache Coherence Protocols Workload Trends Favor Snooping Protocols Commercial Workload and Technology Trends Are Pushing Existing Shared-memory Multiprocessor Coherence Protocols in Divergent Directions. Token Coherence Provides a Framework for New Coherence Protocols That Can Reconcile These Opposi (2001) (0)
Multi-level cache (1997) (0)

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What Schools Are Affiliated With Mark D. Hill?

Mark D. Hill is affiliated with the following schools: