Mark Horowitz

Q: What Schools Are Affiliated With Mark Horowitz

Mark Horowitz is affiliated with the following schools: Stanford University, Massachusetts Institute of Technology

Mark Horowitz's AcademicInfluence.com Rankings

Mark Horowitz

Engineering

#568

World Rank

#937

Historical Rank

#250

USA Rank

Electrical Engineering

#112

World Rank

#128

Historical Rank

#53

USA Rank

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Engineering

Mark Horowitz's Degrees

PhD Electrical Engineering Stanford University
Masters Electrical Engineering Stanford University
Bachelors Electrical Engineering Stanford University

Why Is Mark Horowitz Influential?

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According to Wikipedia, Mark A. Horowitz is an American electrical engineer, computer scientist, inventor, and entrepreneur who is the Yahoo! Founders Professor in the School of Engineering and the Fortinet Founders Chair of the Department of Electrical Engineering at Stanford University. He holds a joint appointment in the Electrical Engineering and Computer Science departments and previously served as the Chair of the Electrical Engineering department from 2008 to 2012. He is a co-founder of Rambus Inc., now a technology licensing company. Horowitz has authored over 700 published conference and research papers and is among the most highly-cited computer architects of all time. He is a prolific inventor and holds 374 patents as of 2023.

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Mark Horowitz's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

EIE: Efficient Inference Engine on Compressed Deep Neural Network (2016) (2092)
Light Field Photography with a Hand-held Plenoptic Camera (2005) (1982)
The future of wires (2001) (1541)
The Stanford Dash multiprocessor (1992) (1099)
High performance imaging using large camera arrays (2005) (1084)
Forwarding metamorphosis: fast programmable match-action processing in hardware for SDN (2013) (918)
1.1 Computing's energy problem (and what we can do about it) (2014) (845)
Light field microscopy (2006) (756)
Energy dissipation in general purpose microprocessors (1996) (674)
Supply and threshold voltage scaling for low power CMOS (1997) (652)
The Stanford FLASH multiprocessor (1994) (633)
Architectural support for copy and tamper resistant software (2000) (631)
An evaluation of directory schemes for cache coherence (1988) (532)
Low-power digital design (1994) (507)
Smart Memories: a modular reconfigurable architecture (2000) (490)
Understanding sources of inefficiency in general-purpose chips (2010) (484)
Cortical representations of olfactory input by trans-synaptic tracing (2011) (478)
Clustered voltage scaling technique for low-power design (1995) (462)
Signal Delay in RC Tree Networks (1981) (429)
TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory (2017) (418)
Precise delay generation using coupled oscillators (1993) (366)
A semidigital dual delay-locked loop (1997) (341)
The Tiny Tera: A Packet Switch Core (1998) (340)
An analytical cache model (1989) (335)
Dual photography (2005) (306)
A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS (2007) (258)
Towards energy-proportional datacenter memory with mobile DRAM (2012) (248)
Cache performance of operating system and multiprogramming workloads (1988) (246)
Scaling internet routers using optics (2003) (245)
The Stanford FLASH multiprocessor (1994) (243)
Defining the Computational Structure of the Motion Detector in Drosophila (2011) (229)
ATUM: a new technique for capturing address traces using microcode (1986) (228)
Scaling, power, and the future of CMOS (2005) (228)
The implementation of a 2-core, multi-threaded itanium family processor (2006) (217)
A replica technique for wordline and sense control in low-power SRAM's (1998) (213)
Implementing an untrusted operating system on trusted hardware (2003) (212)
Synthetic aperture confocal imaging (2004) (210)
High-speed electrical signaling: overview and limitations (1998) (208)
A zero-overhead self-timed 160-ns 54-b CMOS divider (1991) (208)
Light field video camera (2000) (201)
A portable digital DLL for high-speed CMOS interface circuits (1999) (201)
Methods for true energy-performance optimization (2004) (198)
Speed and power scaling of SRAM's (2000) (190)
Limits on multiple instruction issue (1989) (190)
Digital Circuit Optimization via Geometric Programming (2005) (185)
Modeling and analysis of high-speed links (2003) (181)
Circuits and techniques for high-resolution measurement of on-chip power supply noise (2004) (179)
Convolution engine: balancing efficiency & flexibility in specialized computing (2013) (177)
Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell (2003) (177)
Embedded Every-where: A Research Agenda for Networked Systems of Embedded Computers (2001) (174)
Architecture validation for processors (1995) (171)
A fully digital, energy-efficient, adaptive power-supply regulator (1999) (170)
Adaptive supply serial links with sub-1 V operation and per-pin clock recovery (2002) (169)
Skew-tolerant domino circuits (1997) (167)
A 10-GHz global clock distribution using coupled standing-wave oscillators (2003) (165)
IRSIM: An Incremental MOS Switch-Level Simulator (1989) (162)
A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling (1998) (155)
Darkroom: compiling high-level image processing code into hardware pipelines (2014) (155)
Timing Models for MOS Circuits (1983) (154)
The Frankencamera: an experimental platform for computational photography (2010) (153)
High-speed videography using a dense camera array (2004) (151)
Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis (2010) (149)
Performance tradeoffs in cache design (1988) (147)
Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers (2000) (145)
Boosting beyond static scheduling in a superscalar processor (1990) (145)
Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery (2005) (144)
Markov random field based automatic image alignment for electron tomography. (2007) (143)
Scaling, Power and the Future of CMOS (2007) (140)
A 0.3-/spl mu/m CMOS 8-Gb/s 4-PAM serial link transceiver (2000) (139)
Enhancing the performance of the light field microscope using wavefront coding. (2014) (138)
The performance impact of flexibility in the Stanford FLASH multiprocessor (1994) (138)
How scaling will change processor architecture (2004) (138)
Replica compensated linear regulators for supply-regulated phase-locked loops (2006) (135)
A low power switching power supply for self-clocked systems (1996) (134)
Energy-Efficient Floating-Point Unit Design (2011) (134)
Efficient superscalar performance through boosting (1992) (131)
Low-power SRAM design using half-swing pulse-mode techniques (1998) (130)
Interleaving: a multithreading technique targeting multiprocessors and workstations (1994) (129)
Efficient on-chip global interconnects (2003) (129)
Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators (2018) (127)
CPU DB: Recording Microprocessor History (2012) (125)
SPIM: a pipelined 64*64-bit iterative multiplier (1989) (124)
Static control logic for microfluidic devices using pressure-gain valves (2010) (122)
Comparing memory systems for chip multiprocessors (2007) (120)
Methods for true power minimization (2002) (118)
Equalization and clock recovery for a 2.5-10Gb/s 2-PAM/4-PAM backplane transceiver cell (2003) (114)
A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects (2008) (112)
An efficient digital sliding controller for adaptive power supply regulation (2001) (111)
Specifying and verifying hardware for tamper-resistant software (2003) (109)
Design principles for packet parsers (2013) (108)
TANGRAM: Optimized Coarse-Grained Dataflow for Scalable NN Accelerators (2019) (103)
A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per-pin skew compensation (2000) (103)
Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors (1996) (101)
SRT division architectures and implementations (1997) (100)
Synthetic Aperture Focusing using a Shear-Warp Factorization of the Viewing Transform (2005) (99)
Programming Heterogeneous Systems from an Image Processing DSL (2016) (99)
Fast low-power decoders for RAMs (2001) (97)
Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era (2016) (96)
Self-timed logic using Current-Sensing Completion Detection (CSCD) (1991) (96)
A variable-frequency parallel I/O interface with adaptive power-supply regulation (2000) (95)
Microtubule Organization Determines Axonal Transport Dynamics (2016) (94)
FLASH vs. (Simulated) FLASH: closing the simulation loop (2000) (94)
A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter (1999) (93)
Compensation for multimode fiber dispersion by adaptive optics. (2005) (92)
A 0.4-4 Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs (2002) (92)
A 700 Mbps/pin CMOS signalling interface using current integrating receivers (1996) (91)
Characteristics Of Performance-Optimal Multi-level Cache Hierarchies (1989) (91)
Rounding algorithms for IEEE multipliers (1989) (90)
Rethinking Digital Design: Why Design Must Change (2010) (88)
Veiling glare in high dynamic range imaging (2007) (87)
Applications of on-chip samplers for test and measurement of integrated circuits (1998) (84)
Circuit techniques for 1.5-V power supply flash memory (1997) (81)
A serial-link transceiver based on 8 GSample/s A/D and D/A converters in 0.25 /spl mu/m CMOS (2001) (75)
The stream virtual machine (2004) (75)
High-frequency characterization of on-chip digital interconnects (2002) (74)
A 0.8-μm CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links (1996) (74)
Resistance Extraction from Mask Layout Data (1983) (73)
Architectural tradeoffs in the design of MIPS-X (1987) (70)
GABAergic Lateral Interactions Tune the Early Stages of Visual Processing in Drosophila (2013) (69)
Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver (2004) (67)
Energy dissipation in general purpose processors (1995) (67)
A new method for design of robust digital circuits (2005) (65)
Integrated Regulation for Energy-Efficient Digital Circuits (2007) (64)
Rethinking DRAM Power Modes for Energy Proportionality (2012) (64)
Volumetric Image Registration From Invariant Keypoints (2017) (63)
Rigel: flexible multi-rate image processing hardware (2016) (63)
Clocking and circuit design for a parallel I/O on a first-generation CELL processor (2005) (62)
Validation coverage analysis for complex digital designs (1996) (60)
Design of CMOS adaptive-bandwidth PLL/DLLs: a general approach (2003) (60)
Energy–delay tradeoffs in combinational logic using gate sizing and supply voltage optimization (2002) (60)
Analog signal multiplexing for PSAPD-based PET detectors: simulation and experimental validation (2010) (59)
A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications (2007) (59)
Architecture and inherent robustness of a bacterial cell-cycle control system (2008) (57)
Robust Energy-Efficient Adder Topologies (2007) (57)
GAD: A 12-GS/s CMOS 4-bit A/D converter for an equalized multi-level link (1999) (57)
CPU DB (2012) (56)
Microfluidic-based mini-metagenomics enables discovery of novel microbial lineages from complex environmental samples (2017) (55)
Approximate reachability with BDDs using overlapping projections (1998) (55)
The design of a high-performance cache controller: a case study in asynchronous synthesis (1993) (55)
A 0.3-/spl mu/m CMOS 8-Gb/s 4-PAM serial link transceiver (1999) (53)
Alignment of cryo-electron tomography datasets. (2010) (51)
Charge-Sharing Models for Switch-Level Simulation (1987) (51)
Managing wire scaling: a circuit perspective (2003) (49)
A Zero-overhead Self-timed 160ns 54b CMOS Divider (1991) (49)
Soft Error Resilience of Probabilistic Inference Applications (2006) (49)
MIPS-X: a 20-MIPS peak, 32-bit microprocessor with on-chip cache (1987) (47)
A Systematic Approach to Blocking Convolutional Neural Networks (2016) (46)
CMOS Image Sensors With Multi-Bucket Pixels for Computational Photography (2012) (45)
Hardware Fault Containment In Scalable Shared-memory Multiprocessors (1997) (44)
DNN Dataflow Choice Is Overrated (2018) (44)
Convolution engine (2015) (44)
A 90nm CMOS 16Gb/s Transceiver for Optical Interconnects (2007) (44)
A 500-megabyte/s data-rate 4.5 M DRAM (1993) (43)
Deep compression and EIE: Efficient inference engine on compressed deep neural network (2016) (43)
Avoiding game over: Bringing design to the next level (2012) (42)
Dynamic Pointer Allocation for Scalable Cache Coherence Directories (1991) (42)
TETRIS (2017) (42)
10GHz clock distribution using coupled standing-wave oscillators (2003) (41)
Fast, Non-Monte-Carlo Estimation of Transient Performance Variation Due to Device Mismatch (2007) (39)
Channel-limited high-speed links: modeling, analysis and design (2005) (39)
Circuit-level requirements for MOSFET-replacement devices (2008) (38)
A heuristic for optimizing stochastic activity networks with applications to statistical digital circuit sizing (2007) (38)
A variable-frequency parallel I/O interface with adaptive power supply regulation (2000) (38)
A 24 Gb/s Software Programmable Analog Multi-Tone Transmitter (2008) (38)
High performance inter-chip signalling (1998) (37)
FPU Generator for Design Space Exploration (2013) (37)
Long-term microfluidic tracking of coccoid cyanobacterial cells reveals robust control of division timing (2017) (37)
High-Speed Transmitters in 90nm CMOS for High-Density Optical Interconnects (2006) (36)
A semi-digital DLL with unlimited phase shift capability and 0.08-400 MHz operating range (1997) (36)
Techniques for calculating currents and voltages in VLSI power supply networks (1990) (36)
Equalization of modal dispersion in multimode fiber using spatial light modulators (2004) (36)
Design of scalable shared-memory multiprocessors: the DASH approach (1990) (36)
A Pipelined 64x64b Iterative Array Multiplier (1988) (35)
Design of a 10GHz clock distribution network using coupled standing-wave oscillators (2003) (35)
A 1.6 Gb/s, 3 mW CMOS receiver for optical communication (2002) (34)
Regenerative feedback repeaters for programmable interconnections (1995) (33)
CMOS transceiver with baud rate clock recovery for optical interconnects (2004) (33)
Power Optimization for SRAM and Its Scaling (2007) (32)
Informing memory operations: memory performance feedback mechanisms and their applications (1998) (32)
Subtomogram alignment by adaptive Fourier coefficient thresholding. (2010) (32)
Analysis of the Intact Surface Layer of Caulobacter crescentus by Cryo-Electron Tomography (2010) (32)
Optimal linear precoding with theoretical and practical data rates in high-speed serial-link backplane communication (2004) (32)
Dynamic structure of locomotor behavior in walking fruit flies (2017) (32)
Understanding sources of ineffciency in general-purpose chips (2011) (31)
Verification of chip multiprocessor memory systems using a relaxed scoreboard (2008) (31)
Opportunities for optics in integrated circuits applications (2005) (31)
High performance imaging using arrays of inexpensive cameras (2004) (30)
An eight channel 35 GSample/s CMOS timing analyzer (2000) (30)
Fortifying analog models with equivalence checking and coverage analysis (2010) (30)
Improving coverage analysis and test generation for large designs (1999) (29)
Scalable Device for Automated Microbial Electroporation in a Digital Microfluidic Platform. (2017) (29)
Evaluating programmable architectures for imaging and vision applications (2016) (28)
Design Automation Framework for Application-Specific Logic-in-Memory Blocks (2012) (28)
3D segmentation of cell boundaries from whole cell cryogenic electron tomography volumes. (2010) (28)
The Fanout-of-4 Inverter Delay Metric (1998) (28)
On-Chip Instruction Caches for High Performance Processors, (1987) (27)
Common-mode backchannel signaling system for differential high-speed links (2004) (27)
Timing analysis including clock skew (1999) (26)
Removing high contrast artifacts via digital inpainting in cryo-electron tomography: an application of compressed sensing. (2012) (26)
A 50% noise reduction interface using low-weight coding (1996) (26)
A 20-Gb/s 0.13-/spl mu/m CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer (2005) (25)
Timing Robustness in the Budding and Fission Yeast Cell Cycles (2010) (25)
A 4-ns 4K*1-bit two-port BiCMOS SRAM (1988) (25)
Improving CDR Performance via Estimation (2006) (24)
Interconnect scaling implications for CAD (1999) (24)
Digital Circuit Design Trends (2008) (24)
A 24Gb/s Software Programmable Multi-Channel Transmitter (2007) (24)
A memory system design framework: creating smart memories (2009) (23)
Local inhibition of microtubule dynamics by dynein is required for neuronal cargo distribution (2017) (23)
Mapping Histological Slice Sequences to the Allen Mouse Brain Atlas Without 3D Reconstruction (2018) (22)
Modeling the performance of limited pointers directories for cache coherence (1991) (22)
A Verilog piecewise-linear analog behavior model for mixed-signal validation (2013) (22)
Timing analysis for piecewise linear Rsim (1994) (21)
Transmit pre-emphasis for high-speed time-division-multiplexed serial-link transceiver (2002) (21)
Integrated pin electronics for VLSI functional testers (1988) (21)
Microfluidic serial digital to analog pressure converter for arbitrary pressure generation and contamination-free flow control. (2013) (21)
An Optical Interconnect Transceiver at 1550 nm Using Low-Voltage Electroabsorption Modulators Directly Integrated to CMOS (2007) (21)
A 0.6m CMOS 4Gb/s Transceiver With Data Recovery Using Oversampling (1997) (20)
500 Mbyte/sec data-rate 512 Kbits*9 DRAM using a novel I/O interface (1992) (20)
A New Technique for Characterization of Digital-to-Analog Converters in High-Speed Systems (2007) (19)
Multi-tone signaling for high-speed backplane electrical links (2004) (19)
Bisim: a simulator for custom ECL circuits (1988) (19)
A single-chip, functional tester for VLSI circuits (1990) (18)
Architecture and circuit techniques for a reconfigurable memory block (2004) (18)
Clocking strategies in high performance processors (1992) (18)
Low-power dividerless frequency synthesis using aperture phase detection (1998) (18)
False coupling exploration in timing analysis (2005) (18)
Leveraging designer's intent: A path toward simpler analog CAD tools (2009) (17)
Scaling Internet Routers Using Optics (Extended Version) (2003) (17)
SPC03-5: Analog Multi-Tone Signaling for High-Speed Backplane Electrical Links (2006) (17)
Clean-slate Design for the Internet (2006) (17)
A high-speed, low-power 3D-SRAM architecture (2008) (17)
A 160 ns 54 bit CMOS division implementation using self-timing and symmetrically overlapped SRT stages (1991) (17)
Variable domain transformation for linear PAC analysis of mixed-signal systems (2007) (17)
An integrated framework for joint design space exploration of microarchitecture and circuits (2010) (17)
Building Conflict-Free FFT Schedules (2015) (16)
Optimizing the mapping of low-density parity check codes on parallel decoding architectures (2001) (16)
Comparative evaluation of memory models for chip multiprocessors (2008) (16)
Using partitioning to help convergence in the standard-cell design automation methodology (1999) (16)
Creating an Agile Hardware Design Flow (2020) (16)
Piecewise linear models for Rsim (1993) (16)
Scalable circuits for supply noise measurement (2005) (15)
Cmos Image Sensors Dynamic Range and Snr Enhancement via Statistical Signal Processing (15)
Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-/spl mu/m CMOS (2005) (15)
On-Die Power Supply Noise Measurement Techniques (2009) (15)
Architectural and Implementation Tradeoffs in the Design of Multiple-Context Processors (1992) (15)
Digital Analog Design: Enabling Mixed-Signal System Validation (2015) (15)
Optimizing iterative decoding of low-density parity check codes on programmable pipelined parallel architectures (2001) (14)
Using a configurable processor generator for computer architecture prototyping (2009) (14)
1 mm3 resolution breast-dedicated PET system (2008) (13)
A 50 Gb/s 32/spl times/32 CMOS crossbar chip using asymmetric serial links (1999) (13)
The MIPS-X Microprocessor, (1985) (13)
Error Control and Limit Cycle Elimination in Event-Driven Piecewise Linear Analog Functional Models (2016) (13)
Automated pressure regulator (1984) (13)
Current integrating receivers for high speed system interconnects (1995) (12)
Global convergence analysis of mixed-signal systems (2011) (12)
SRT division diagrams and their usage in designing intergrated circuits for division (1986) (12)
Stochastic steady-state and AC analyses of mixed-signal systems (2009) (12)
Informing Loads: Enabling Software to Observe and React to Memory Behavior (1995) (12)
A low cost laser interferometer system for machine tool applications (1983) (11)
Automated electrotransformation of Escherichia coli on a digital microfluidic platform using bioactivated magnetic beads. (2017) (11)
Darkroom (2014) (11)
Latency Sensitive FMA Design (2011) (11)
A framework for designing reusable analog circuits (2003) (11)
Fast, Non-Monte-Carlo Estimation of Transient Performance Variation Due to Device Mismatch (2010) (11)
TETRIS (2017) (11)
Vex—A CAD toolbox (1999) (10)
A 4 ns BiCMOS translation-lookaside buffer (1990) (10)
FPMax: a 106GFLOPS/W at 217GFLOPS/mm2 Single-Precision FPU, and a 43.7GFLOPS/W at 74.6GFLOPS/mm2 Double-Precision FPU, in 28nm UTBB FDSOI (2016) (10)
An efficient test vector generation for checking analog/mixed-signal functional models (2010) (10)
Scale- and orientation-invariant keypoints in higher-dimensional data (2015) (10)
Improving energy efficiency of DRAM by exploiting half page row access (2016) (10)
Measurement of series collector resistance in bipolar transistors (1982) (10)
Practical Limits of Multi-Tone Signaling Over High-Speed Backplane Electrical Links (2007) (10)
A heuristic method for statistical digital circuit sizing (2006) (9)
A 220pJ/pixel/frame CMOS image sensor with partial settling readout architecture (2016) (9)
Measurement of Via Currents in Printed Circuit Boards Using Inductive Loops (2006) (9)
Hardware/software co-design of the Stanford FLASH multiprocessor (1997) (9)
Sparse matrix-vector multiply on the HICAMP architecture (2012) (9)
REDS: Resistance Extraction for Digital Simulation (1987) (9)
Measurement of Supply Pin Current Distributions in Integrated Circuit Packages (2007) (9)
Anatomical, Physiological, and Functional Heterogeneity of the Dorsal Raphe Serotonin System (2018) (9)
SegAlign: A Scalable GPU-Based Whole Genome Aligner (2020) (9)
Burst mode packet receiver using a second order DLL (2004) (8)
SP 22.4: A 1V 0.9mW at 100MHz 2kx16b SRAM utilizing a Half-Swing Pulsed-Decoder and Write-Bus Architecture in 0.25pm Dual-Vt CMOS (1998) (8)
An Equalization Scheme for 10 Gb / s 4-PAM Signaling over Long Cables (1997) (8)
Mable: A Technique for Efficient Machine Simulation (1994) (8)
Generating Incremental VLSI Compaction Spacing Constraints (1987) (8)
Beyond the horizon: The next 10x reduction in power - Challenges and solutions (2011) (8)
Front-end electronics for a 1 mm3 resolution avalanche photodiode-based PET system with analog signal multiplexing (2008) (8)
Area-efficiency in CMP core design: co-optimization of microarchitecture and physical design (2009) (7)
A 1 V 0.9 mW at 100 MHz 2 k/spl times/16 b SRAM utilizing a half-swing pulsed-decoder and write-bus architecture in 0.25 /spl mu/m dual-Vt CMOS (1998) (7)
Rigel (2016) (7)
CESEL: Securing a Mote for 20 Years (2016) (7)
Noise analysis of LSO-PSAPD PET detector front-end multiplexing circuits (2007) (7)
Processor Performance Modeling using Symbolic Simulation (2008) (7)
Techniques for characterizing DRAMs with a 500 MHz interface (1994) (6)
Joint Supply , Threshold Voltage and Sizing Optimization for Design of Robust Digital Circuits (2007) (6)
Analyzing CMOS power supply networks using Ariel (1988) (6)
A 14 bit dual-ramp DAC for digital-audio systems (1982) (6)
A 2 Gb / s Asymmetric Serial Link for High-Bandwidth Packet Switches (1997) (6)
A 50 Gb / s CMOS Crossbar Chip using Asymmetric Serial Links * (6)
An overview of the MIPS-X-MP project (1986) (6)
Energy-Efficient Design of High-Speed Links (2002) (6)
Energy–Performance Tunable Logic (2009) (6)
Markov Random Field Based Automatic Image Alignment for ElectronTomography (2007) (6)
Circuit techniques for large CSEA SRAMs (1992) (6)
20Gb/s 0.13/spl mu/m CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer (2004) (6)
Stream Virtual Machine and Two-Level Compilation Model for Streaming Architectures and Languages (2004) (5)
A Static RAM as a Fault Model Evaluator (1987) (5)
Time-Variant Characterization and Compensation of Wideband Circuits (2007) (5)
Why design must change: rethinking digital design (2009) (5)
A 3.5 ns, 1 Watt, ECL register file (1990) (5)
Array-of-arrays architecture for parallel floating point multiplication (1995) (5)
Smart Memories Polymorphic Chip Multiprocessor (2009) (5)
Fast FPGA Emulation of Analog Dynamics in Digitally-Driven Systems (2018) (5)
Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra (2022) (5)
fault: A Python Embedded Domain-Specific Language for Metaprogramming Portable Hardware Verification Components (2020) (5)
1550nm Optical Interconnect Transceiver with Low Voltage Electroabsorption Modulators Flip-Chip Bonded to 90nm CMOS (2007) (5)
Tethys: Collecting Sensor Data without Infrastracture or Trust (2018) (5)
Internet of Everything ( IoE ) focus area (2015) (5)
Why design must change: Rethinking digital design (2010) (5)
1550 nm Optical Interconnect Transceiver with Low Voltage Electroabsorption Modulators Flip-Chip Bonded to 90 nm CMOS (2006) (5)
A 0.8 /spl mu/m CMOS 2.5 Gb/s oversampled receiver for serial links (1996) (5)
A 0.6pm CMOS 4Gb/s Transceiver with Data Recovery usi (1997) (5)
SPIM (Stanford Pipelined Iterative Multiplier): A Pipelined 64 X 64 Bit Iterative Multiplier (1988) (4)
An Analog Model Template Library: Simplifying Chip-Level, Mixed-Signal Design Verification (2019) (4)
Mapping Mouse Brain Slice Sequence to a Reference Brain Without 3D Reconstruction (2018) (4)
Intermediate representations for controllers in chip generators (2011) (4)
SRT Division: Architectures, Models, and Implementations (1998) (4)
Large-Scale Mapping of Transposable Element Insertion Sites Using Digital Encoding of Sample Identity (2013) (4)
Falcon — A Flexible Architecture For Accelerating Cryptography (2019) (4)
A single-chip LSI high-speed functional tester (1987) (4)
A 3-stage Pseudo Single-phase Flip-flop family (2012) (4)
Bringing up a chip on the cheap (2012) (3)
Optimization of hybrid JJ/CMOS memory operating temperatures (1997) (3)
Parallel Link with Per Pin Skew Compensation (2000) (3)
The Stanford Dash multiprocessor-Computer (2008) (3)
A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs (2020) (3)
Open-Source Synthesizable Analog Blocks for High-Speed Link Designs: 20-GS/s 5b ENOB Analog-to-Digital Converter and 5-GHz Phase Interpolator (2020) (3)
An area-efficient minimum-time FFT schedule using single-ported memory (2013) (3)
Eliminating redundant DC equations for asymptotic waveform evaluation (1994) (3)
TANGRAM (2019) (3)
Compiling Algorithms for Heterogeneous Systems (2018) (3)
Fast Validation of Mixed-Signal SoCs (2021) (3)
Scaling, Power, and the Future of CMOS Technology (2008) (3)
Area Efficient High Speed and Low Power MAC Unit (2013) (3)
An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs (2022) (3)
Automated Design Space Exploration of CGRA Processing Element Architectures using Frequent Subgraph Analysis (2021) (3)
Demo: Tethys -- An Energy Harvesting Networked Water Flow Sensor (2015) (3)
The Interaction Engine (2018) (3)
MTQuant: “Seeing” Beyond the Diffraction Limit in Fluorescence Images to Quantify Neuronal Microtubule Organization (2016) (2)
Charge Sharing Models for MOS Circuits. (1983) (2)
Life at the end of CMOS scaling (and beyond) (panel session) (abstract only) (2000) (2)
A 0 . 8m CMOS 2 . 5 Gb / s Oversampling Receiver and Transmitter for Serial Links Chih-Kong (1996) (2)
The case for simple, visible cache coherency (2008) (2)
Enabling Reusable Physical Design Flows with Modular Flow Generators (2021) (2)
A dual in-pixel memory CMOS image sensor for computation photography (2011) (2)
20-GS/s 8-bit Analog-to-Digital Converter and 5-GHz Phase Interpolator for Open-Source Synthesizable High-Speed Link Applications (2020) (2)
Separating Protection and Resource Management in Operating Systems (2002) (2)
MICROFLUIDIC SERIAL DAC FOR ANALOG PRESSURE GENERATION (2012) (2)
The Sparse Abstract Machine (2022) (2)
The design and testing of MIPS-X (1988) (2)
The Frankencamera: an experimental platform for computational photography (2010) (2)
Rethinking Non-major Circuits Pedagogy for Improved Motivation (2018) (2)
Energy-Efficient Processor Design (2009) (2)
A Semi-Digital Delay Locked Loop with Unlimited Phase Shift Capability and 0 . 08-400 MHz (1997) (2)
Using texture mapping with mipmapping to render a VLSI layout (2001) (2)
Compiling Halide Programs to Push-Memory Accelerators (2021) (2)
Preventing Global Convergence Failures in Mixed-Signal Systems by Eliminating Indeterminate States (2011) (2)
Timing Analysis with Clock Skew (1999) (2)
Author response: Dynamic structure of locomotor behavior in walking fruit flies (2017) (2)
Low power electronics and design symposium preview (2001) (2)
A Fast Large-Integer Extended GCD Algorithm and Hardware Design for Verifiable Delay Functions and Modular Inversion (2022) (2)
Efficient moment-based timing analysis for variable accuracy switch level simulation (1991) (2)
Bringing source-level debugging frameworks to hardware generators (2022) (2)
Spatiotemporal Sampling and Interpolation for Dense Camera Arrays (2017) (1)
What's next after CMOS (2007) (1)
Intent-leveraged optimization of analog circuits via homotopy (2010) (1)
Codesign of the Stanford FLASH Multiprocessor (1997) (1)
Partitioning-driven convergence in the design of random-logic blocks (2000) (1)
Reconfigurable Future (2003) (1)
A 14b PCM DAC (1982) (1)
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996, Monterey, California, USA, August 12-14, 1996 (1996) (1)
Nondestructive readout architecture for a kinetic inductance memory cell (1993) (1)
A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro (2000) (1)
FP 12.4: A 0.8~ CMOS 2.5Gb/s Oversampled Receiver for Serial Links (1996) (1)
Polymorphous Computing Architectures (2007) (1)
Automatic Color Calibration for Large Camera (2017) (1)
Energy-Performance Tunable Logic (2009) (1)
Automating System Configuration (2021) (1)
A 4 nsec 4 K*1 bit two-port BiCMOS SRAM (1988) (1)
Bipolar circuit elements providing self-completion-indication (1990) (1)
Record 1 mm 3 Resolution Breast-Dedicated PET System (2009) (1)
Hardware Abstractions and Hardware Mechanisms to Support Multi-Task Execution on Coarse-Grained Reconfigurable Arrays (2023) (1)
Compensation of multimode fiber dispersion using adaptive optics (2005) (1)
SP 25.7: Skew-Tolerant Domino Circuits (1997) (0)
A Tracking PLL with an FIR Loop Filter (2002) (0)
Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays (2022) (0)
Session 26: Evening Panel Discussion Nanoelectronics - Now or Never? (2004) (0)
A Directory-Based Scalable General-Purpose Shared-Memory Multiprocessor (1998) (0)
Session details: Design and synthesis of biological circuits (2011) (0)
A 4 nsec 4Kxlbit Two-Port BiCMOS SRAM (1988) (0)
Dynamic spatial organization of multi-protein complexes controlling microbial polar organization, chromosome replication, and cytokinesis (2012) (0)
System with a variety of DRAMS and a bus (1991) (0)
Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators (2022) (0)
A 11 Patent Number : 5 , 671 , 151 45 Date of Patent : Sep . 23 , 1997 (2017) (0)
Detector and front-end electronics for 1mm3 resolution breast-dedicated PET system (2009) (0)
An Overview of the MIPS-XMP Project (1998) (0)
2013 Ieee Custom Integrated Circuits Conference (cicc 2013) Educational Sessions Session 1 – Plenary Session Welcome and Opening Remarks Awards Presentations Keynote Speaker Introduction Session 2 --microsystems for Biomedical and Sensing Applications a Broadband Biosensor Interface Ic for Miniaturi (0)
Educating future chip designers (1987) (0)
Enabling and Accelerating Dynamic Vision Transformer Inference for Real-Time Applications (2022) (0)
Training Domain Specific Models for Energy-Efficient Object Detection (2018) (0)
Energy-efficient Management of Reconfigurable Computers 5.1 Overview (2016) (0)
Dataset Culling: Towards Efficient Training of Distillation-Based Domain Specific Models (2019) (0)
Automatic Projective Model Estimation and Reconstruction in Cryogenic Electron Tomography (2006) (0)
Systeme de signalisation a vitesse elevee a preaccentuation de transmission, effacement de reflexion et effacement de decalage adaptatifs (2004) (0)
A 20 MIPS Peak Microprocessor with On-Chip Cache, (1984) (0)
Tomographic Reconstruction and Alignment Using Matrix Norm Minimization (2016) (0)
Fast signaling system with adaptive predistortion cancellation of reflections and suppression of DC offsets (2004) (0)
mflowgen: a modular flow generator and ecosystem for community-driven physical design: invited (2022) (0)
APEX: A Framework for Automated Processing Element Design Space Exploration using Frequent Subgraph Analysis (2023) (0)
Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration (2022) (0)
Joint DAC/IWBDA special session design and synthesis of biological circuits (2011) (0)
Acknowledgements 8.2 Lower Bounds for Broadcasting and Related Problems 5 Realization on Feasible Networks Spawning Algorithms. a Spawning Algorithm Starts with a Collection of Unit Tasks, and at Each (1994) (0)
Smart Memory Systems: Polymorphous Computing Architectures (2004) (0)
Removing overhead from high-level interfaces (2012) (0)
Simplified timing and data recovery support noise-tolerant character award procedures (2004) (0)
WAM 2.3 A 32b Microprocessor with OnChip ZKbyte Instruction Cache (1984) (0)
In field, energy-performance tunable FPGA architectures (2009) (0)
Chip Generators Study (2008) (0)
Delay loop circuit for adjusting a clock delay (1998) (0)
A 1 . 6 Gb / s , 3 mW Integrating CMOS Optical Receiver with Hybrid GaAs PhotoDetectors (2002) (0)
Method for operating a synchronous memory having a variable length of the output data (1991) (0)
A 500Megabyte/s Data-Rate 4.5M DRAM (Special Section on the 1992 VLSI Circuits Symposium) (1993) (0)
Accurate Prediction = > Large Model = > More Memory Reference = > High Power (0)
Specialized versus general-purpose hardware (2011) (0)
FOR VARIABLE ACCURACY SWITCH LEVEL SIMULATION (1998) (0)
Agencements et techniques de microscopie (2006) (0)
AD-Al 8 i 716 AN ANALYTICAL CACHE MODEL DTlC (0)
Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays (2022) (0)
Numériseur temporel pour photodétecteur de tep (2012) (0)
Memoire dynamique a acces aleatoire permettant un transfert synchrone de donnees a partir d'une requete asynchrone (1997) (0)
Cortical representation of olfactory bulb input revealed by retrograde mono-transsynaptic labeling (2010) (0)
Integrated Inference for Hardware-Software Efficiency : A Case Study in SpMV and Smart Memories (2010) (0)
On task mapping optimization for parallel decoding of low-density parity-check codes on message-passing architectures (2005) (0)
POWER AND COST ISSUES NECESSITATE RETHINKING DIGITAL DESIGN. TO REDUCE DESIGN COSTS, WE NEED TO STOP BUILDING CHIP INSTANCES, AND START MAKING CHIP GENERATORS INSTEAD. DOMAIN-SPECIFIC CHIP GENERATORS ARE TEMPLATES THAT CODIFY DESIGNER KNOWLEDGE AND DESIGN (2010) (0)
System with a plurality of DRAMs, and a bus (1991) (0)
Superconducting/semiconducting hybrids and advance memory concepts for superconducting electronics. Technical performance report (1993) (0)
Lawrence Berkeley National Laboratory Recent Work Title Automatic Projective Model Estimation and Reconstruction in Cryogenic Electron Tomography Permalink (2006) (0)
Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains (2022) (0)
Microsupercomputers: Design and Implementation (1988) (0)
Reshaping EDA for power (2003) (0)
Circuit with a delay locked loop to adjust the clock delay (1998) (0)
Session details: Reshaping EDA for power (2003) (0)
Semi-Custom High-Speed Datapath Design Using Commericial ASIC Design Tools (2007) (0)
A new IC with level-crossing ADC readout architecture for PET detector signals (2012) (0)
Exploring Shared Memory Protocols in FLASH (2007) (0)
Integrated I / O circuit using a Hochleistungsbusschnittstelle (1991) (0)
7. Validation 6. User Interface 5. Timing and the Global Event Ordering Problem 4. Implementation Platforms Parallel Simulation Instruction-driven Simulation Execution-driven Simulation (1994) (0)
Digital Analog Design: A Highly-Efficient Method to Design Analog Circuits (2017) (0)
Input / output of an integrated circuit with a high performance bus interface (1991) (0)
HIGH THROUGHPUT MICROFLUIDIC SAMPLE PREPARATION FOR METAGENOMIC ANALYSIS (2014) (0)
Ren Ng1 Marc Levoy1 Mathieu Bredif1 Gene Duval2 Mark Horowitz1 Pat Hanrahan1 (2005) (0)
Long-term microfluidic tracking of coccoid cyanobacterial cells reveals robust control of division timing (2017) (0)
EXPLORING ABSTRACT INTERFACES IN SYSTEM-ON-CHIP INTEGRATION A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE ON GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY (2014) (0)
A DISSERTATION SUBMITTED TO THE DEPARTMENT OF MECHANICAL ENGINEERING AND THE COMMITTEE ON GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY (1995) (0)
Vex-a CAD toolbox (1999) (0)
Circuits de source de courant electrique pour un bus (1993) (0)
The Magazine for Chip and Silicon Systems Designers (2010) (0)
Markov random field based automatic alignment for low SNR imagesfor cryo electron tomography (2007) (0)
Semiconductor Device with Dynamic Random Access Memory (DRAM) (1991) (0)
New SSCS Chapters in Tainan and South Brazil, Seoul and Santa Clara Chapters Host Talks (2007) (0)

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