Masahiro Fujita

Masahiro Fujita's AcademicInfluence.com Rankings

Masahiro Fujita

Computer Science

#9772

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#10252

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#6729

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#6967

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Computer Science

Masahiro Fujita's Degrees

PhD Computer Science University of Tokyo

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Best Online PhD of Computer Science (Doctorates) 2026

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Masahiro Fujita's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Symbolic model checking using SAT procedures instead of BDDs (1999) (802)
Multi-Terminal Binary Decision Diagrams: An Efficient Data Structure for Matrix Representation (1997) (459)
Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping (1993) (348)
Power analysis and minimization techniques for embedded DSP software (1997) (289)
On variable ordering of binary decision diagrams for the application of multi-level logic synthesis (1991) (273)
Evaluation and improvement of Boolean comparison method based on binary decision diagrams (1988) (254)
Partitioned ROBDDs-a compact, canonical and efficiently manipulable representation for Boolean functions (1996) (119)
Hybrid decision diagrams. Overcoming the limitations of MTBDDs and BMDs (1995) (100)
Program Slicing of Hardware Description Languages (1999) (94)
Advanced Verification Techniques Based on Learning (1995) (87)
Variable ordering algorithms for ordered binary decision diagrams and their evaluation (1993) (85)
Automatic test pattern generation for functional register-transferlevel circuits using assignment decision diagrams (2001) (79)
Multi-level logic optimization using binary decision diagrams (1989) (71)
Multi-Terminal Binary Decision Diagrams and Hybrid Decision Diagrams (1996) (70)
Multiple error diagnosis based on Xlists (1999) (69)
Power analysis and low-power scheduling techniques for embedded DSP software (1995) (66)
Multiresolution interpolation meshes (2001) (65)
Tokio: Logic Programming Language Based on Temporal Logic and its Compilation to Prolog (1986) (61)
The standard SpecC language (2001) (56)
Testing, verification, and diagnosis in the presence of unknowns (2000) (53)
Hybrid decision diagrams (1995) (52)
SAT-Based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions (2012) (52)
Model Checking Based on Sequential ATPG (1999) (50)
Modeling the unknown! Towards model-independent fault and error diagnosis (1998) (49)
Bug identification of a real chip design by symbolic model checking (1994) (46)
Automatic test pattern generation for functional RTL circuits using assignment decision diagrams (2000) (43)
Application of Boolean unification to combinational logic synthesis (1991) (42)
Boolean resubstitution with permissible functions and binary decision diagrams (1990) (38)
Embedded Software Verification Using Symbolic Execution and Uninterpreted Functions (2006) (38)
A Formal Approach for Debugging Arithmetic Circuits (2009) (36)
Program slicing for VHDL (2002) (35)
Sampling schemes for computing OBDD variable orderings (1998) (34)
Rectification method for lookup-table type FPGA's (1992) (34)
Multi-level logic minimization based on minimal support and its application to the minimization of look-up table type FPGAs (1991) (32)
Modular Datapath Optimization and Verification Based on Modular-HED (2010) (31)
Verification of Arithmetic Circuits by Comparing Two Similar Circuits (1996) (30)
Lp Based Cell Selection With Constraints Of Timing, Area, And Power Consumption (1994) (30)
Formal verification of combinational circuits (1997) (30)
Partial synthesis through sampling with and without specification (2013) (29)
Equivalence checking of C programs by locally performing symbolic simulation on dependence graphs (2006) (29)
Fast spectrum computation for logic functions using binary decision diagrams (1994) (28)
Transaction-based debugging of system-on-chips with patterns (2009) (28)
Protocol Transducer Synthesis using Divide and Conquer approach (2007) (28)
Methods for automatic design error correction in sequential circuits (1993) (27)
Verification Techniques for System-Level Design (2007) (26)
Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths (2005) (26)
Foveated Real-Time Ray Tracing for Virtual Reality Headset (2014) (25)
Functional Equivalence Verification Tools in High-Level Synthesis Flows (2009) (25)
Using complementation and resequencing to minimize transitions (1998) (25)
Efficient SAT-based ATPG techniques for all multiple stuck-at faults (2014) (25)
Implementation of Temporal Logic Programming Language Tokio (1985) (25)
Decomposition Techniques for Efficient ROBDD Construction (1996) (24)
Temporal Logic Programming Language Tokio - Programming in Tokio (1985) (24)
Logic synthesis for a single large look-up table (1995) (23)
Embedded Memory and ARM Cortex-M0 Core Using 60-nm C-Axis Aligned Crystalline Indium–Gallium–Zinc Oxide FET Integrated With 65-nm Si CMOS (2017) (23)
On the integration of model-driven design and dynamic assertion-based verification for embedded software (2013) (23)
Applications of Multi-Terminal Binary Decision Diagrams (1995) (23)
Formal Verification Techniques for Digital Systems (1998) (22)
Approximate DCT Design for Video Encoding Based on Novel Truncation Scheme (2019) (22)
An efficient filter-based approach for combinational verification (1999) (22)
A survey of techniques for formal verification of combinational circuits (1997) (21)
30.9 Normally-off computing with crystalline InGaZnO-based FPGA (2014) (20)
Polynomial datapath optimization using partitioning and compensation heuristics (2009) (20)
Verification of Synchronization in SpecC Description with the Use of Difference Decision Diagrams (2003) (19)
BDD minimization by truth table permutations (1996) (19)
An equivalence checking methodology for hardware oriented C-based specifications (2002) (19)
Transaction-based post-silicon debug of many-core System-on-Chips (2012) (18)
Dynamic property mining for embedded software (2012) (18)
VERIFUL: VERIfication using FUnctional Learning (1995) (17)
Multi-level logic optimization (2001) (17)
Irredundant address bus encoding techniques based on adaptive codebooks for low power (2003) (16)
Temperature-aware software-based self-testing for delay faults (2015) (16)
Toward Unification of Synthesis and Verification in Topologically Constrained Logic Design (2015) (16)
Delay estimation and optimization of logic circuits: a survey (1997) (16)
A 140 MHz 1 Mbit 2T1C gain-cell memory with 60-nm indium-gallium-zinc oxide transistor embedded into 65-nm CMOS logic process technology (2017) (16)
An energy-efficient patchable accelerator for post-silicon engineering changes (2011) (16)
Data Sequencing for Minimum-transition Transmission (1997) (16)
LTED : A Canonical and Compact Hybrid Word-Boolean Representation as a Formal Model for Hardware / Software Co-designs (2007) (15)
SEU tolerant robust memory cell design (2012) (15)
Hardware-Assisted Relief Texture Mapping (2002) (15)
Formal verification of the HAL S1 System cache coherence protocol (1997) (15)
Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications (2005) (14)
234Compositor: A flexible parallel image compositing framework for massively parallel visualization environments (2017) (14)
An Equivalence Checking Method for C Descriptions Based on Symbolic Simulation with Textual Differences (2005) (14)
Synchronization verification in system-level design with ILP solvers (2005) (14)
A resynthesis approach for network optimization (1991) (14)
Hybrid spectral transform diagrams (1997) (13)
Crystalline In–Ga–Zn–O FET-based configuration memory for multi-context field-programmable gate array realizing fine-grained power gating (2013) (13)
SEU tolerant SRAM cell (2011) (13)
Specifying Hardware in temporal Logic & Efficient Synthesis of State-Diagrams Using Prolog (1984) (13)
Guided gate-level ATPG for sequential circuits using a high-level test generation approach (2010) (13)
Arithmetic Circuits Verification without Looking for Internal Equivalences (2008) (12)
Efficient sum-to-one subsets algorithm for logic optimization (1992) (12)
A Methodology for Trace Signal Selection to Improve Error Detection in Post-Silicon Validation (2017) (12)
Efficient variable ordering using aBDD based sampling (2000) (12)
A fast test pattern generation for large scale circuits (1993) (12)
Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions (2007) (12)
A 32-bit CPU with zero standby power and 1.5-clock sleep/2.5-clock wake-up achieved by utilizing a 180-nm C-axis aligned crystalline In-Ga-Zn oxide transistor (2014) (12)
Pipelined Microprocessors Optimization and Debugging (2010) (11)
A Redesign Technique For Combinational Circuits Based On Gate Recomections (1994) (11)
Automatic and semi-automatic verification of switch-level circuits with temporal logic and binary decision diagrams (1990) (11)
On-chip dynamic signal sequence slicing for efficient post-silicon debugging (2011) (11)
On Securing Scan Design Through Test Vector Encryption (2018) (11)
Direct Ray Tracing of Full-Featured Subdivision Surfaces with B´ ezier Clipping (2015) (11)
Application of temporal logic to the assistance of hardware logic design (1988) (11)
EFSM-based model-driven approach to concolic testing of system-level design (2011) (11)
Post-Silicon Gate-Level Error Localization With Effective and Combined Trace Signal Selection (2020) (11)
Custom Instruction Generation with High-Level Synthesis (2008) (10)
Embedded SRAM and Cortex-M0 Core Using a 60-nm Crystalline Oxide Semiconductor (2014) (10)
Applications of crystalline Indium-Gallium-Zinc-Oxide technology to LSI: Memory, processor, image sensor, and field programmable gate array (2013) (10)
Pipeline scheduling for array based reconfigurable architectures considering interconnect delays (2005) (10)
On reducing transitions through data modifications (1999) (10)
Domain-specific high-level modeling and synthesis for ATM switch design using VHDL (1996) (10)
An ATPG Method for Double Stuck-At Faults by Analyzing Propagation Paths of Single Faults (2018) (10)
Variable ordering of binary decision diagrams for multi-level logic minimization (1993) (10)
Program Slicing for Design Automation: An Automatic Technique for Speeding-up Hardware Design, Simul (1998) (9)
Improved heuristics for finite word-length polynomial datapath optimization (2009) (9)
Debug methodology for arithmetic circuits on FPGAs (2002) (9)
Subthreshold Operation of CAAC-IGZO FPGA by Overdriving of Programmable Routing Switch and Programmable Power Switch (2017) (9)
Hierarchical error diagnosis targeting RTL circuits (2000) (9)
On error tolerance and Engineering Change with Partially Programmable Circuits (2012) (9)
UPF-based formal verification of low power techniques in modern processors (2015) (9)
Combining Restorability and Error Detection Ability for Effective Trace Signal Selection (2017) (9)
A study of composition schemes for mixed apply/compose based construction of ROBDDs (1996) (9)
Embedded SRAM and Cortex-M0 core with backup circuits using a 60-nm crystalline oxide semiconductor for power gating (2014) (8)
Post-silicon observability enhancement with topology based trace signal selection (2017) (8)
Equivalence checking of high-level designs based on symbolic simulation (2009) (8)
High-Level Design and Validation of ATM Switch (1997) (8)
A New Approach for Debugging Logic Circuits without Explicitly Debugging Their Functionality (2016) (8)
Debugging processors with advanced features by reprogramming LUTs on FPGA (2013) (8)
Polynomial datapath optimization using constraint solving and formal modelling (2010) (8)
Post-silicon patching for verification/debugging with high-level models and programmable logic (2012) (8)
Model-driven design and validation of embedded software (2011) (8)
Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor (1999) (8)
Systematic approximate logic optimization using don't care conditions (2017) (8)
Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition (2015) (8)
RTL level trace signal selection and coverage estimation during post-silicon validation (2017) (8)
On Testing of Superscalar Processors in Functional Mode for Delay Faults (2017) (8)
Multi-level logic minimization across latch boundaries (1990) (8)
Formal verification guided automatic design error diagnosis and correction of complex processors (2011) (7)
Some recent advances in software and hardware logic simulation (1997) (7)
Formally analyzing fault tolerance in datapath designs using equivalence checking (2016) (7)
A Unified Framework for Equivalence Verification of Datapath Oriented Applications (2009) (7)
Exact Minimum Factoring of Incompletely Specified Logic Functions via Quantified Boolean Satisfiability (2011) (7)
A Calibration Technique for Simultaneous Estimation of Actual Sensing Matrix Coefficients on Modulated Wideband Converters (2020) (7)
A novel formal approach to generate high-level test vectors without ILP and SAT solvers (2007) (7)
Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design (2018) (7)
A Boosting Pass Gate With Improved Switching Characteristics and No Overdriving for Programmable Routing Switch Based on Crystalline In-Ga-Zn-O Technology (2015) (7)
HIVE : A Visualization and Analysis Framework for Large-Scale Simulations on the K Computer (2016) (7)
RTL design verification by making use of datapath information (1992) (7)
Hardware/Software Co-design and Verification Methodology from System Level Based on System Dependence Graph (2007) (7)
Boolean technology mapping for both ECI and CMOS circuits based on permissible functions and binary decision diagrams (1990) (7)
Efficient scheduling techniques for ROBDD construction (1999) (7)
Synthesis of controllers from interval temporal logic specification (1993) (6)
Object-oriented analysis and design of hardware/software co-designs with dependence analysis for design reuse (2005) (6)
16.9 A 128kb 4b/cell nonvolatile memory with crystalline In-Ga-Zn oxide FET using Vt, cancel write method (2015) (6)
Using the Temporal Logic Programming Language Tokio for Algorithm Description and Automatic CMOS Gate Array Synthesis (1985) (6)
A Hybrid Approach for Equivalence Checking Between System Level and RTL Descriptions (2007) (6)
SRAM with c-axis aligned crystalline oxide semiconductor: Power leakage reduction technique for microprocessor caches (2014) (6)
A debugging method for gate level circuit designs by introducing programmability (2013) (6)
Polynomial datapath synthesis and optimization based on vanishing polynomial over Z2m and algebraic techniques (2012) (6)
On equivalence checking between behavioral and RTL descriptions (2004) (6)
Improving polynomial datapath debugging with HEDs (2014) (6)
An efficient method to localize and correct bugs in high-level designs using counterexamples and potential dependence (2012) (6)
Global transaction ordering in Network-on-Chips for post-silicon validation (2011) (6)
State retention flip flop architectures with different tradeoffs using crystalline indium gallium zinc oxide transistors implemented in a 32-bit normally-off microprocessor (2014) (6)
A Study on Open Source Software for Large-Scale Data Visualization on SPARC64fx based HPC Systems (2018) (6)
Distributed Particle-Based Rendering Framework for Large Data Visualization on HPC Environments (2017) (5)
High-Precision Sub-Nyquist Sampling System Based on Modulated Wideband Converter for Communication Device Testing (2021) (5)
A 48 MHz 880-nW Standby Power Normally-Off MCU with 1 Clock Full Backup and 4.69-μs Wakeup Featuring 60-nm Crystalline In–Ga–Zn Oxide BEOL-FETs (2019) (5)
234 scheduling of 3-2 and 2-1 eliminations for parallel image compositing using non-power-of-two number of processes (2015) (5)
On the evaluation of arbitrary defect coverage of test sets (1999) (5)
Combining Top-down and Bottom-up approaches for ROBDD (1995) (5)
Automated System Testing of Dynamic Web Applications (2011) (5)
Speeding up technology-independent timing optimization by network partitioning (1997) (5)
Specification and formal verification of power gating in processors (2014) (5)
Theoretical Analysis of Noise Figure for Modulated Wideband Converter (2020) (5)
Error Model Free Automatic Design Error Correction of Complex Processors Using Formal Methods (2012) (5)
Automated data analysis techniques for a modern silicon debug environment (2012) (5)
Preventing Scan Attack through Test Response Encryption (2019) (5)
A debugging method for repairing post-silicon bugs of high performance processors in the fields (2010) (5)
Introduction to the Special Issue on Multi-Terminal Binary Decision Diagrams (1997) (5)
Symbolic verification of CMOS synchronous circuits using characteristic functions (1991) (5)
Custom Instruction Generation for Configurable Processors with Limited Numbers of Operands (2010) (5)
A Retargetable Compilation Methodology for Embedded Digital Signal Processors Using a Machine-Dependent Code Optimization Library (1999) (5)
2-3-4 Decomposition Method for Large-Scale Parallel Image Composition with Arbitrary Number of Nodes (2014) (5)
Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm (2018) (5)
Formal equivalence checking for loop optimization in C programs without unrolling (2007) (5)
Rule-Based Approaches for Equivalence Checking of SpecC Programs (2008) (4)
Post Silicon Debugging of Electrical Bugs Using Trace Buffers (2017) (4)
Normally-Off Computing for Crystalline Oxide Semiconductor-Based Multicontext FPGA Capable of Fine-Grained Power Gating on Programmable Logic Element With Nonvolatile Shadow Register (2015) (4)
A new approach for selecting inputs of logic functions during debug (2017) (4)
SEU tolerant SRAM for FPGA applications (2010) (4)
A 20ns-write 45ns-read and 1014-cycle endurance memory module composed of 60nm crystalline oxide semiconductor transistors (2018) (4)
Automatic Rectification of Processor Design Bugs Using a Scalable and General Correction Model (2014) (4)
Synthesis of Algorithm Considering Communication Structure of Distributed/Parallel Computing (2019) (4)
An efficient algorithm for the net matching problem (1993) (4)
An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults (2019) (4)
Formal verification of C language based VLSI designs (2004) (4)
Securing Scan through Plain-text Restriction (2019) (4)
Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS (2016) (4)
Formal verification - prove it or pitch it (2003) (4)
Detection of test Patterns with Unreachable States through Efficient Inductive-Invariant Identification (2015) (4)
Fast simulation of Digital Spiking Silicon Neuron model employing reconfigurable dataflow computing (2013) (4)
An Automatic Test Pattern Generation Method for Multiple Stuck-At Faults by Incrementally Extending the Test Patterns (2020) (4)
Simple tree-construction heuristics for the fanout problem (1995) (4)
Design of Single-Bit Fault-Tolerant Reversible Circuits (2021) (4)
Coverage Driven High-Level Test Generation Using a Polynomial Model of Sequential Circuits (2010) (4)
Automatic identification of assertions and invariants with small numbers of test vectors (2015) (4)
Equivalence checking in C-based system-level design by sequentializing concurrent behaviors (2007) (4)
Template based synthesis for high performance computing (2017) (4)
A Simple BDD Package without Variable Reordering and Its Application to Logic Optimization with Permissible Functions (2019) (4)
Multi-step image compositing for massively parallel rendering (2014) (4)
Modular equivalence verification of polynomial datapaths with multiple word-length operands (2011) (4)
MAESTRO: A time-driven embedded testbed Architecture with Event-driven Synchronization (2014) (3)
High level design validation: current practices and future directions (2004) (3)
A Post-Silicon Debug Support Using High-Level Design Description (2009) (3)
Simulation-Based Analysis of Cyberphysical Systems (2012) (3)
An optimization of bus interconnects pitch for low-power and reliable bus encoding scheme (2006) (3)
Concurrent resynthesis for network optimization (1991) (3)
Generation of I/O sequences for a high-level design from those in post-silicon for efficient post-silicon debugging (2010) (3)
Debugging a communications chip (1996) (3)
Hardware in loop testing of an insulin pump (2015) (3)
A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio (1990) (3)
An Energy-Efficient Normally Off Microcontroller With 880-nW Standby Power, 1 Clock System Backup, and 4.69- $\mu$ s Wakeup Featuring 60-nm CAAC-IGZO FETs (2019) (3)
High presence remote presentation in the shared immersive virtual world (2003) (3)
Improving the accuracy of rule-based equivalence checking of system-level design descriptions by identifying potential internal equivalences (2009) (3)
Patching Method for Lookup-Table Type FPLs (1992) (3)
Improving post-silicon error detection with topological selection of trace signals (2017) (3)
Debugging and optimizing high performance superscalar out-of-order processors using formal verification techniques (2011) (3)
Time-Constraint-Aware Optimization of Assertions in Embedded Software (2012) (3)
System level design language extensions for timed/untimed digital-analog combined system design (2005) (3)
Equivalence Checking with Rule-Based Equivalence Propagation and High-Level Synthesis (2006) (3)
Logic synthesis and verification on fixed topology (2014) (3)
Testing multiple stuck-at faults of ROBDD based combinational circuit design (2017) (3)
Verification of Event-Based Synchronization of SpecC Description Using Difference Decision Diagrams (2002) (3)
Demonstration of hardware-accelerated formal verification (2009) (3)
Basic and Advanced Researches in Logic Synthesis and their Industrial Contributions (2019) (3)
BDD-based logic partitioning for sequential circuits (1997) (3)
Model checking: its basics and reality (1998) (3)
Automatic Test Pattern Generation for Double Stuck-at Faults Based on Test Patterns of Single Faults (2019) (3)
ATM switch design by high-level modeling, formal verification and high-level synthesi (1998) (3)
Incremental ATPG methods for multiple faults under multiple fault models (2015) (3)
Interconnect-Aware Pipeline Synthesis for Array-Based Architectures (2009) (3)
Targeting Leakage Constraints during ATPG (2008) (3)
Efficient signature-based sub-circuit matching (2015) (3)
Synthesis and formal verification of on-chip protocol transducers through decomposed specification (2010) (3)
High-level optimization of integer multipliers over a finite bit-width with verification capabilities (2009) (3)
Memory-system requirements for convolutional neural networks (2018) (3)
Validating Multi-Processor Cache Coherence Mechanisms under Diminished Observability (2019) (3)
Enhanced Design Debugging With Assistance From Guidance-Based Model Checking (2021) (3)
Multi-Step Image Composition Approach for Sort-Last Massively Parallel Rendering (2015) (2)
Object-oriented analysis and specification for HW/SW co-design with UML diagrams (2006) (2)
Synthesis and Generalization of Parallel Algorithm for Matrix-vector Multiplication (2020) (2)
Enhanced Unique Sensitization for Efficient Test Generation (Special Issue on Synthesis and Verification of Hardware Design) (1993) (2)
Interconnect-topology independent mapping algorithm for a Coarse Grained Reconfigurable Architecture (2011) (2)
Variation-Aware Analysis and Test Pattern Generation Based on Functional Faults (2014) (2)
Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams (2023) (2)
Towards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE (2010) (2)
Event-driven observability enhanced coverage analysis of C programs for functional validation (2003) (2)
Equivalence Checking of Loops before and after Pipelining by Applying Symbolic Simulation and Induction (2009) (2)
RTL datapath optimization using system-level transformations (2014) (2)
Test pattern generation for multiple stuck-at faults not covered by test patterns for single faults (2017) (2)
Integration of high-level modeling, formal verification, and high-level synthesis in ATM switch design (1998) (2)
A functional test generation technique for RTL datapaths (2012) (2)
Debugging from high level down to gate level (2009) (2)
Formal verification of a pipelined processor with new memory hierarchy using a commercial model checker (2002) (2)
Zero Area Overhead State Retention Flip Flop Utilizing Crystalline In-Ga-Zn Oxide Thin Film Transistor with Simple Power Control Implemented in a 32-bit CPU (2013) (2)
ZEPHCAD and FLORA: logic synthesis for control and datapath (1994) (2)
Using Counterexample Analysis to Minimize the Number of Predicates for Predicate Abstraction (2007) (2)
A low-cost approximate 32-point transform architecture (2017) (2)
HIVE: A cross-platform, modular visualization framework for large-scale data sets (2020) (2)
Automatically adjusting system level designs after RTL/gate-level ECO (2016) (2)
Simulation-Based Verification Techniques for System-Level Designs (2008) (2)
Formal Verification and Debugging of VLSI Logic Design for Systems Dependability: Experiments and Evaluation (2018) (2)
Early case splitting and false path detection to improve high level ATPG techniques (2011) (2)
Test Coverage (2018) (2)
System level design methodologies from the viewpoint of formal verification (2003) (2)
ATM Switch Design: Parametric High-Level Modeling and Formal Verification (1997) (2)
Multi-Level Logic Minimization of Large Combinational Circuits by Partitioning (1993) (2)
Slicing-based Hardware/Software Co-design Methodology From Functional Specifications (2006) (2)
Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture (2011) (2)
Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture (2011) (2)
Signal Selection Methods for Efficient Multi-Target Correction (2019) (2)
On more efficient combinational ATPG using functional learning (1996) (2)
Logic Synthesis for Generalization and Learning Addition (2021) (2)
A New Reconfigurable Architecture with Applications to IoT and Mobile Computing (2018) (2)
LUT-based Circuit Approximation with Targeted Error Guarantees (2020) (2)
ELURA: A Methodology for Post-Silicon Gate-Level Error Localization Using Regression Analysis (2018) (2)
A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug (2020) (2)
Synthesis and Generalization of Parallel Algorithms Considering Communication Constraints (2020) (2)
Dependence Graph Based Verification and Synthesis of Hardware/Software Co-Designs with SAT Related Formulation (2008) (2)
On-chip transaction level debug support for system-on-chips (2009) (2)
FPGA Based Accelerator for Neural Networks Computation with Flexible Pipelining (2021) (2)
System LSI distributed collaborative design environment for both designers and CAD developers/engineers (2006) (2)
Accelerating Tsunami simulation with FPGA and GPU through automatic compilation (2011) (2)
Hardware implementation of BLTL property checkers for acceleration of statistical model checking (2013) (1)
Patents and Patent Applications (2017) (1)
Approximate Arithmetic Circuit Design Using a Fast and Scalable Method (2019) (1)
Temporal logic based hardware description and its verification with Prolog (1983) (1)
Post-silicon verification and debugging with control flow traces and patchable hardware (2012) (1)
Fast and Efficient Signature-Based Sub-Circuit Matching (2016) (1)
Modular arithmetic decision procedure with auto-correction mechanism (2009) (1)
Field Modifiable Architecture and its Design Methodology: System Design Without Logic Synthesis (2002) (1)
HIVE: A Cross-Platform, Modular Visualization Ecosystem for Heterogeneous Computational Environments (2018) (1)
Practical design assistance at register transfer level using a data path verifier (1990) (1)
Logic analysis and optimization with quick identification of invariants through one time frame analysis (2015) (1)
Two Real Formal Verification Experiences: ATM Switch Chip and Parallel Cache Protocol (1998) (1)
Field modifiable architecture with FPGAs and its design/verification/debugging methodologies (2003) (1)
Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures (2007) (1)
Transaction Ordering in Network-on-Chips for Post-Silicon Validation (2012) (1)
Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table (2002) (1)
Verifying Reliability (Dagstuhl Seminar 12341) (2012) (1)
An Automatic Method of Mapping I/O Sequences of Chip Execution onto High-level Design for Post-Silicon Debugging (2011) (1)
Optimization of Assertion Placement in Time-Constrained Embedded Systems (2011) (1)
An approach to approximate computing: Logic transformations for one-minterm changes in specification (2017) (1)
Synthesizing, Verifying, and Debugging SoC with FSM-Based Specification of On-Chip Communication Protocols (2011) (1)
Precomputed radiance transfer with spatially-varying lighting effects (2004) (1)
Sequential Equivalence Checking (2006) (1)
Distance aware ray tracing for curves (2012) (1)
FOF: Functionally Observable Fault and its ATPG techniques (2013) (1)
A high-level language for programming complex temporal behaviors and its translation into synchronous (1997) (1)
An Interactive Verification and Debugging Environment by Concrete/Symbolic Simulations for System-Level Designs (2008) (1)
A Note on Complexity of OBDD Composition and Efficiency of Partitioned-OBDDs over OBDDs (2001) (1)
Solving the net matching problem in high-performance chip design (1996) (1)
Trends in Formal Verification Techniques for C-based Hardware Designs (2009) (1)
Synchronization Mechanism for Timed/Untimed Mixed-Signal System Level Design Environment (2006) (1)
Performance-Constrained Different Cell Count Minimization for Continuously-Sized Circuits (2008) (1)
A Formal Perspective on Effective Post-silicon Debug and Trace Signal Selection (2017) (1)
A Methodology for SAT-Based Electrical Error Debugging During Post-Silicon Validation (2019) (1)
A Decomposition-Based Synthesis Algorithm for Sparse Matrix-Vector Multiplication in Parallel Communication Structure (2021) (1)
Network Resynthesis Algorithms for Delay Minimization (Special Issue on Synthesis and Verification of Hardware Design) (1993) (1)
Logic Synthesis for Reversible Circuits (2019) (1)
High-Level Engineering Change Through Programmable Datapath and SMT Solvers (2019) (1)
The AMS Extension to System Level Design Language - SpecC (2006) (1)
Network Optimization Using Don’t-Cares and Boolean Relations (1993) (1)
Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths (2005) (1)
PHYSICS AND TECHNOLOGY OF CRYSTALLINE OXIDE (2016) (1)
Logic Design Assistence Using Temporal Logic Based Language Tokio (1989) (1)
SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement (2019) (1)
Performance-Constrained Transistor Sizing for Different Cell Count Minimization (2010) (1)
Signal Selection Methods for Debugging Gate-Level Sequential Circuits (2019) (1)
Methods of equivalence checking and ECO support under C-based design through reproduction of C descriptions from implementation designs (2017) (1)
HIVE: A VISUAL ANALYTICS FRAMEWORK FOR LARGE-SCALE CFD ON THE K COMPUTER (2016) (1)
SAT-Based Data-Flow Mapping Onto Array Processor (2020) (1)
A new approach for diagnosing bridging faults in logic designs (2017) (1)
Instruction-based self-test for delay faults maximizing operating temperature (2017) (1)
180-mV Subthreshold Operation of Crystalline Oxide Semiconductor FPGA Realized by Overdriving Programmable Power Switch and Programmable Routing Switch (2015) (1)
Improving BDD Variable Ordering Using Abstract BDDs and Sampling (1999) (1)
SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays (2020) (1)
Word-Level Equivalence Checking in Bit-Level Accuracy by Synthesizing Designs onto Identical Datapath (2009) (1)
Comparative study on verilog-based and C-based hardware design education (2003) (1)
Automatic rectification of design errors in complex processors with programmable hardware (2012) (1)
Speeding Up Look-up-Table Driven Logic Simulation (1999) (1)
Engineering changes in field modifiable architectures (2003) (1)
Client-tier Validation of Dynamic Web Applications (2011) (1)
Hardware-Accelerated Formal Veri fi cation (2008) (1)
Specification by existing design plus use-cases (2016) (0)
Dynamically Reconfigurable Non-Volatile Multi-Context FPGA with CAAC-OS-based Programmable Routing Switches (2014) (0)
Approximating Arithmetic Circuits for IoT Devices Data Processing (2022) (0)
Reducing scheduling overheads in dynamically reconfigurable processors (VLSI設計技術) (2010) (0)
Session details: Advances in sequential optimization (2008) (0)
AnOptimization ofBusInterconnects Pitch for Low-power andReliable BusEncoding Scheme (2006) (0)
Spatio-temporal computation on a coarse grained reconfigurable architecture (2011) (0)
Template-Based Semi-Formal Approach to Robust Equivalence Checking (2022) (0)
Logic optimization for asynchronous speed independent controllers using transduction method (2003) (0)
Session details: Special session: Design closure for reliability (2010) (0)
Automatic Error Correction of Reversible Circuits (2019) (0)
Domain–Specific High–Level Modeling and Synthesis for ATM Switch Prototyping (1997) (0)
A Low Overhead Methodology for Validating Memory Consistency Models in Chip Multiprocessors (2020) (0)
Synthesis and Optimization of Multiple Portions of Circuits for ECO based on Set-Covering and QBF Formulations (2020) (0)
Chapter 9–Conclusion (2018) (0)
Special session 4B: Elevator talks (2013) (0)
Efficient Reachability Analysis Based on Inductive Invariant Using X-value Based Flipflop Selection (2021) (0)
Verification Algorithms for FSM Models (2008) (0)
RTL Design Verification by Making Use of Da t apa t h In for ma ti on (1992) (0)
Static Checking of Higher-Level Design Descriptions (2008) (0)
Sequential Equivalence Checking Using a Hybrid Boolean-Word Level Decision Diagram (2008) (0)
Field modifiable architecture with FPGAs and its design methodology (2002) (0)
Illumination Renderer http : / / lucille . sourceforge . net (2004) (0)
Efficient Graph Matching Method for LUT-Networks (リコンフィギャラブルシステム) (2016) (0)
Formal Analysis of Integer Multipliers by building Binary Decision Diagram of Adder Trees (2022) (0)
Time-Constraint-Aware Optimization of Assertions in Embedded Software (2012) (0)
An Energy-Efficient Patchable Accelerator and Its Design Methods (2014) (0)
Solving the Net Matching Pro erforrnance Chip Desi (1996) (0)
Formal Veriication of Combinational Circuits (1997) (0)
Computer Aided Design and Test - BDDs versus SAT (Dagstuhl Seminar 01051) (2021) (0)
A High-Level Language for ProgrammingComplex Temporal Behaviors and Its Translationinto Synchronous (1997) (0)
Applying Per - pixel shading for Relief Textre Mapping (2002) (0)
Tutorial T10: Post - Silicon Validation, Debug and Diagnosis (2013) (0)
Formal Verification of Synchronization Issue in System-Level Design with Automatic Abstraction (0)
New design paradigms: what needs to be standardized? (2001) (0)
Computer Aided Design and Test Decision Diagrams - Concepts and Applications (Dagstuhl Seminar 9705) (2021) (0)
Theoretical Analysis on Noise Performance of Modulated Wideband Converters for Analog Testing (2020) (0)
Formal verification of hardware/software co‐designs with translation into representation by state transitions (2007) (0)
26 The Reliability Challenge from Random Process Variability Induced Timing Errors (2012) (0)
Computer Aided Design and Test : BDDs vs . SAT (2001) (0)
Optimization of modular multiplication on FPGA using don't care conditions (2009) (0)
Specification Description and High-level Design Methodology of SoC Considering Design Reuse (2008) (0)
Design Verification and Fault Diagnosis in Manufacturing (1999) (0)
Computer Aided Design and Test : BDDs vs . SAT (2001) (0)
High-Level Synthesis for Highly-Efficient Accelerators Enabling Post-Silicon Engineering Change (2010) (0)
[Plenary talks - 11 abstracts] (2014) (0)
Low-Precision Quantization Techniques for Hardware-Implementation-Friendly BERT Models (2022) (0)
Dynamically reconfigurable protocol transducer (2006) (0)
Live Demonstration: Automatic Synthesis of Algorithms on Multi Chip/FPGA with Communication Constraints (2019) (0)
SEU Tolerant Robust Latch Design (2012) (0)
Formal Verification of Synchronization Issues in SpecC Description with Automatic Abstraction (0)
Model Checking: Its Basics and Reality (Embedded Tutorial). (1998) (0)
Collaborative Flow Field Visualization in the Networked Virtual Laboratory (2004) (0)
Basic Technology for Formal Verification (2008) (0)
Device Physics of CAAC-IGZO FET (2016) (0)
A new approach for constructing logic functions after ECO (2017) (0)
Utilizing high level design information to speed up post-silicon debugging (2011) (0)
C Description Reconstruction Method from a Revised Netlist for ECO Support (2018) (0)
Integration of Logic Synthesis and Layout Processes by Generating Multiple Choices of Circuit Transformation (2001) (0)
VLSI CAD Education and Exercise Course with Public Domain Tools (2007) (0)
A Framework on Synchronization Verification in System-Level Design (2005) (0)
Rule-based equivalence checking of system-level design descriptions (2009) (0)
CAAC-OS-based Nonvolatile Programmable Analog Device: Voltage Controlled Oscillator Realizing Instant Frequency Switching (2014) (0)
High Level Verification and Its Use at Pos-Silicon Debugging and Patching (2011) (0)
Logic Optimization for Asynchronous SI Controllers using Transduction Method (2002) (0)
Network Resynthesis Algorithms for Delay Minimization (1993) (0)
Multi-level Bounded Model Checking to detect bugs beyond the bound (2008) (0)
Formal Verification based on recurrence equations and equivalence checking (2000) (0)
Aries: A Semiformal Technique for Fine-Grained Bug Localization in Hardware Designs (2022) (0)
Efficient Graph Matching Method for LUT-Networks (VLSI設計技術) (2016) (0)
Timing Optimization of Multi-Level Networks Using Boolean Relations (Special Section on the 5th Karuizawa Workshop on Circuits and Systems) (1993) (0)
Non-volatile hybrid optical phase shifter driven by a ferroelectric transistor (2022) (0)
Reducing scheduling overheads in dynamically reconfigurable processors (リコンフィギャラブルシステム) (2010) (0)
Simultaneous circuit transformation and routing (2002) (0)
Irredundant Low Power Address Bus Encoding Techniques Based on Adaptive Codebooks (2003) (0)
Energy-Efficient FPGA Implementation of Power-of-2 Weights-Based Convolutional Neural Networks With Low Bit-Precision Input Images (2023) (0)
Real-time Learned Image Codec on FPGA (2022) (0)
OVERCOMING MEMORY CONSTRAINTS IN ROBDD CONSTRUCTION BY FUNCTIONAL DECOMPOSITION AND PARTITIONING by (2016) (0)
Development and Verification of a Collaborative Printing Environment (2007) (0)
Parallel Scheduling Attention Mechanism: Generalization and Optimization (2022) (0)
Equivalence Checking of Loop Optimizations in C Programs without Loop Unrolling (2007) (0)
On Implementation of LUT with Large Numbers of Inputs (Abstract Only) (2015) (0)
SAT-Based On-Track Bus Routing (2021) (0)
Model checking and equivalence checking (2009) (0)
Adder-Only Convolutional Neural Network with Binary Input Image (2019) (0)
Unknown Threats and Provisions (2018) (0)
Trace signal selection methods for post silicon debugging (2015) (0)
Data-path aware high-level ECO synthesis (2019) (0)
Higher-Level Design Methodology and Associated Verification Problems (2008) (0)
A High-Level Language for Programming Complex Temporal Behaviors and Its Translation into Synchronous Circuits (2013) (0)
Delay Testing Based on Multiple Faulty Behaviors (2015) (0)
Model Checking on Higher-Level Design Descriptions (2008) (0)
Equivalence Checking on Higher-Level Design Descriptions (2008) (0)
Post-silicon debugging targeting electrical errors with patchable controllers (abstract only) (2012) (0)
Automatic assertion extraction in gate-level simulation using GPGPUs (2012) (0)
Code Generation Using FSM and Symbolic State Traversal (2002) (0)
Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only) (2010) (0)
The Tokio system (1996) (0)
F-LIC: FPGA-based Learned Image Compression with a Fine-grained Pipeline (2022) (0)
Analysis and testing on delays with two time frames (2015) (0)
Future Applications/Developments (2016) (0)
Surv ey of T echniques for F ormal Veri cation of Combinational Circuits (1997) (0)
A Large Data Visualization Framework for SPARC64 fx HPC Systems - Case Study: K Computer Operational Environment - (2018) (0)
Equivalence checking: a rule-based approach (2006) (0)
Speed tunable finite state machine compiler: Zephcad (1990) (0)
Hardware / Software Co-Design / Execution Approach to Silicon Debug and Diagnosis (2010) (0)
VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms: 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8–10, 2018, Revised and Extended Selected Papers (2019) (0)
AMS Extensions for Timed/Untimed System-Level Design Language (2005) (0)
Parallelized Implementation of Reachability Analysis Using Partitioned-ROBDDs on PC-cluster (2005) (0)
Rectification of advanced microprocessors without changing routing on FPGAs (abstract only) (2013) (0)
Rectification Method for (1992) (0)
Automatic Test Pattern Generation Targeting Multiple Faults under Multiple Fault Models (2014) (0)
Model Checking for Dependable Software-Intensive Systems (2003) (0)
Session details: Session 4A: Circuit structure in formal verification (2001) (0)
Performance Estimation with Automatic False-Path Detection for System-Level Designs (2010) (0)
High-Level Debugging of Post-Silicon Failures (2018) (0)
A 32-kb Embedded SRAM Using 60-nm Crystalline Oxide Semiconductor Transistors and Power Gating with 45-ns 144-fJ/bit Data Backup (2015) (0)
Compositional Techniques for Mixed Bottom-Up/Top-Down (1999) (0)
Automatic correction of logic bugs in hardware design: Partial logic synthesis (2018) (0)
Extended abstract: a formal design approach from software oriented UML descriptions to hardware oriented RTL (2005) (0)
Debugging and testing hardware and software (Memento) (2013) (0)
“Post silicon debug of SOC designs” (2011) (0)
A HW/SW Co-Reuse Methodology Based on Design Refinement Templates in UML Diagrams (2008) (0)
DNetSpec: A Distributed Network Testing Toolset for Middleware Developers (2017) (0)
Tutorial: "Post silicon debug of SOC designs". (2011) (0)
A 32-bit CPU with Zero Standby Power and 1.5-clock Backup/2.5-clock Restore Achieved by Utilizing a 180-nm Crystalline Oxide Semiconductor Transistor (2014) (0)
Description Methods of CHDL for Redesign Methods (1991) (0)
Automatic partitioning for efficient combinational verification (2000) (0)
Multi-Level Bounded Model Checking with Symbolic Counterexamples (2011) (0)
1 Model checking and equivalence checking (2009) (0)
Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design (2018) (0)
Equivalence Checking for C Description by Local Symbolic Simulation Using Dependence Graphs (2005) (0)
BMC-Based Temperature-Aware SBST for Worst-Case Delay Fault Testing Under High Temperature (2022) (0)
Highly-Pipelined and Energy-Saved Computing with Arrays of Non-Volatile Memories (2014) (0)
Synthesizing and Completely Testing Hardware Based on Templates Through Small Numbers of Test Patterns (2016) (0)
09461 Abstracts Collection - Algorithms and Applications for Next Generation SAT Solvers (2009) (0)
Parallel Scheduling Self-attention Mechanism: Generalization and Optimization (2020) (0)
Deep Learning-assisted Scan Chain Diagnosis with Different Fault Models during Manufacturing Test (2022) (0)
A verification technique for communication hardware and its application to a real chip design (1995) (0)
A Logic Optimization Method by Eliminating Redundant Multiple Faults from Higher to Lower Cardinality (2020) (0)
Debugging Methods Through Identification of Appropriate Functions for Internal Gates (2013) (0)
Scalable Construction of Formal Error Guaranteed LUT-Based Approximate Multipliers with Analytical Worst-Case Error Bound (2022) (0)
Toward Unification of Synthesis andVerificationinTopologically Constrained Logic Design In this paper, the author presents a method by which logic synthesis and formal verification can be achieved with a small number of input patterns, if all possible circuit transformations are predetermined. (2015) (0)
Synthesis of LUT Based Approximating Adder Circuits with Formal Error Guarantees (2022) (0)
Organizers and Program Committee Members (2006) (0)

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University of Tokyo

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