Massimo Alioto
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Engineering
Massimo Alioto's Degrees
- PhD Electrical Engineering University of California, Berkeley
- Masters Electrical Engineering University of California, Berkeley
- Bachelors Electrical Engineering University of Catania
Why Is Massimo Alioto Influential?
(Suggest an Edit or Addition)According to Wikipedia, Massimo Alioto is an associate professor in the Department of Electrical and Computer Engineering at the National University of Singapore. He was named Fellow of the Institute of Electrical and Electronics Engineers in 2016, for contributions to energy-efficient VLSI circuits.
Massimo Alioto's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial (2012) (399)
- Understanding the Effect of Process Variations on the Delay of Static and Domino Logic (2010) (196)
- Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis (2010) (170)
- Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits (1991) (166)
- Enabling the Internet of Things: From Integrated Circuits to Integrated Systems (2017) (157)
- Analysis and comparison on full adder block in submicron technology (2002) (138)
- Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I—Methodology and Design Strategies (2011) (125)
- General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space (2010) (116)
- Leakage Power Analysis Attacks: A Novel Class of Attacks to Nanometer Cryptographic Circuits (2010) (114)
- Design strategies for source coupled logic gates (2003) (112)
- Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II—Results and Figures of Merit (2011) (106)
- A feedback strategy to improve the entropy of a chaos-based random bit generator (2006) (92)
- A Class of Maximum-Period Nonlinear Congruential Generators Derived From the Rényi Chaotic Map (2007) (88)
- Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison (2006) (80)
- 14.3 15fJ/b static physically unclonable functions for secure chip identification with <2% native bit instability and 140× Inter/Intra PUF hamming distance separation in 65nm (2015) (80)
- Leakage–Delay Tradeoff in FinFET Logic Circuits: A Comparative Analysis With Bulk Technology (2010) (78)
- Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design (2010) (78)
- Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS (2012) (78)
- Effectiveness of Leakage Power Analysis Attacks on DPA-Resistant Logic Styles Under Process Variations (2014) (76)
- Comparative Evaluation of Layout Density in 3T, 4T, and MT FinFET Standard Cells (2011) (74)
- Mixed Full Adder topologies for high-performance low-power arithmetic circuits (2007) (71)
- Variations in Nanometer CMOS Flip-Flops: Part I—Impact of Process Variations on Timing (2015) (68)
- Design of High-Speed Power-Efficient MOS Current-Mode Logic Frequency Dividers (2006) (68)
- Oscillation frequency in CML and ESCL ring oscillators (2001) (65)
- A Simple Circuit Approach to Reduce Delay Variations in Domino Logic Gates (2012) (58)
- Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I—Device–Circuit Interaction and Evaluation at Device Level (2014) (57)
- 8.8 iRazor: 3-transistor current-based error detection and correction in an ARM Cortex-R4 processor (2016) (56)
- Static Physically Unclonable Functions for Secure Chip Identification With 1.9–5.8% Native Bit Instability at 0.6–1 V and 15 fJ/bit in 65 nm (2016) (55)
- SRAM for Error-Tolerant Applications With Dynamic Energy-Quality Management in 28 nm CMOS (2015) (52)
- The Internet of Things on Its Edge: Trends Toward Its Tipping Point (2018) (52)
- Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02 fJ/b in 40 nm (2018) (50)
- A simple strategy for optimized design of one-level carry-skip adders (2003) (49)
- Energy-quality scalable adaptive VLSI circuits and systems beyond approximate computing (2017) (44)
- iRazor: Current-Based Error Detection and Correction Scheme for PVT Variation in 40-nm ARM Cortex-R4 Processor (2018) (41)
- Enabling the Internet of Things (2017) (41)
- Modeling and evaluation of positive-feedback source-coupled logic (2004) (39)
- Modeling and optimized design of current mode MUX/XOR and D flip-flop (2000) (39)
- Token-Based Security for the Internet of Things With Dynamic Energy-Quality Tradeoff (2019) (38)
- Approximate SRAMs With Dynamic Energy-Quality Management (2016) (38)
- Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic Circuits From Device Measurements (2012) (37)
- AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption (2015) (37)
- The Digital Tent Map: Performance Analysis and Optimized Design as a Low-Complexity Source of Pseudorandom Bits (2006) (35)
- A General Power Model of Differential Power Analysis Attacks to Static Logic Circuits (2008) (34)
- Low-power approximate MAC unit (2017) (34)
- CML and ECL: optimized design and comparison (1999) (34)
- Power estimation in adiabatic circuits: a simple and accurate model (2001) (34)
- Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study (2015) (33)
- A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits (2018) (32)
- 13.8 A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOS (2014) (31)
- A 595pW 14pJ/Cycle microcontroller with dual-mode standard cells and self-startup for battery-indifferent distributed sensing (2018) (29)
- Evaluation of energy consumption in RC ladder circuits driven by a ramp input (2004) (29)
- A pW-Power Hz-Range Oscillator Operating With a 0.3–1.8-V Unregulated Supply (2019) (29)
- Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II–Evaluation at Circuit Level and Design Perspectives (2014) (28)
- Trends in Hardware Security: From basics to ASICs (2019) (28)
- Novel Class of Energy-Efficient Very High-Speed Conditional Push–Pull Pulsed Latches (2014) (27)
- Power–Delay–Area–Noise Margin Tradeoffs in Positive-Feedback MOS Current-Mode Logic (2007) (27)
- “EChO” Reconfigurable Power Management Unit for Energy Reduction in Sleep-Active Transitions (2013) (27)
- High-mobility 0.85nm-EOT Si0.45Ge0.55-pFETs: Delivering high performance at scaled VDD (2010) (26)
- Energy-Quality Scalable Integrated Circuits and Systems: Continuing Energy Scaling in the Twilight of Moore’s Law (2018) (26)
- Analysis of layout density in FinFET standard cells and impact of fin technology (2010) (26)
- Fully Synthesizable Low-Area Analogue-to-Digital Converters With Minimal Design Effort Based on the Dyadic Digital Pulse Modulation (2020) (26)
- Low-hardware complexity PRBGs based on a piecewise-linear chaotic map (2006) (25)
- Differential Power Analysis Attacks to Precharged Buses: A General Analysis for Symmetric-Key Cryptographic Algorithms (2010) (25)
- Analysis and Comparison on Full Adder Block in (2002) (25)
- Fully Synthesizable Low-Area Digital-to-Analog Converter With Graceful Degradation and Dynamic Power-Resolution Scaling (2019) (25)
- Fully Synthesizable, Rail-to-Rail Dynamic Voltage Comparator for Operation down to 0.3 V (2018) (24)
- Highly accurate and simple models for CML and ECL gates (1999) (24)
- Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits (2009) (24)
- Dynamic Reference Voltage Sensing Scheme for Read Margin Improvement in STT-MRAMs (2018) (24)
- Understanding the Potential and the Limits of Germanium pMOSFETs for VLSI Circuits From Experimental Measurements (2011) (24)
- A 346 µm 2 VCO-Based, Reference-Free, Self-Timed Sensor Interface for Cubic-Millimeter Sensor Nodes in 28 nm CMOS (2014) (23)
- Standard Cell-Based Ultra-Compact DACs in 40-nm CMOS (2019) (21)
- Variations in Nanometer CMOS Flip-Flops: Part II—Energy Variability and Impact of Other Sources of Variations (2015) (21)
- Fully Digital Rail-to-Rail OTA With Sub-1000-μm² Area, 250-mV Minimum Supply, and nW Power at 150-pF Load in 180 nm (2020) (21)
- Modelling of source‐coupled logic gates (2002) (21)
- Mixed FBB/RBB: A Novel Low-Leakage Technique for FinFET Forced Stacks (2012) (20)
- A Novel Framework to Estimate the Path Delay Variability On the Back of an Envelope via the Fan-Out-of-4 Metric (2017) (20)
- Voltage Scaled STT-MRAMs Towards Minimum-Energy Write Access (2016) (20)
- From energy‐delay metrics to constraints on the design of digital circuits (2012) (20)
- Design of Digital OTAs With Operation Down to 0.3 V and nW Power for Direct Harvesting (2021) (19)
- Novel Boosted-Voltage Sensing Scheme for Variation-Resilient STT-MRAM Read (2016) (19)
- Performance evaluation of adiabatic gates (2000) (19)
- Energy consumption in RC tree circuits (2006) (18)
- Impact of NMOS/PMOS imbalance in Ultra-Low Voltage CMOS standard cells (2011) (17)
- Leakage Power Analysis attacks: Well-defined procedure and first experimental results (2009) (17)
- Comparative soft error evaluation of layout cells in FinFET technology (2014) (17)
- 17.3 A reconfigurable dual-port memory with error detection and correction in 28nm FDSOI (2016) (17)
- Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation (2019) (16)
- Guest Editorial for the Special Issue on Ultra-Low-Voltage VLSI Circuits and Systems for Green Computing (2012) (16)
- Enabling sizing for enhancing the static noise margins (2013) (16)
- Performance evaluation of the low-voltage CML D-latch topology (2003) (16)
- Power-Aware Design of Nanometer MCML Tapered Buffers (2008) (16)
- Dynamically Adaptable Pipeline for Energy-Efficient Microarchitectures Under Wide Voltage Scaling (2018) (16)
- Editorial on the Opening of the New Editorial Year - The State of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2018) (16)
- Uniform-Distributed Noise Generator Based on a Chaotic Circuit (2006) (15)
- Active RFID: Perpetual wireless communications platform for sensors (2012) (15)
- DET FF topologies: A detailed investigation in the energy-delay-area domain (2011) (15)
- Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW (2021) (15)
- A gate-level strategy to design Carry Select Adders (2004) (14)
- IoT: Bird’s Eye View, Megatrends and Perspectives (2017) (14)
- NAND/NOR adiabatic gates: power consumption evaluation and comparison versus the fan-in (2002) (14)
- Exploiting Hysteresys in MCML Circuits (2006) (14)
- Rail-to-Rail Dynamic Voltage Comparator Scalable Down to pW-Range Power and 0.15-V Supply (2021) (14)
- A Sub-Leakage PW-Power HZ-Range Relaxation Oscillator Operating with 0.3V-1.8V Unregulated Supply (2018) (13)
- Time-Based Sensing for Reference-Less and Robust Read in STT-MRAM Memories (2018) (13)
- A Variability-Tolerant Feedback Technique for Throughput Maximization of Trbgs with Predefined Entropy (2010) (13)
- An approach to the design of PFSCL gates (2005) (13)
- Power‐delay optimization of D‐latch/MUX source coupled logic gates (2005) (12)
- Ultra-low power design approaches for IoT (2014) (12)
- Enhancing the Static Noise Margins by Upsizing Length for Ultra-Low Voltage/Power/Energy Gates (2014) (12)
- Impact of High-Mobility Materials on the Performance of Near- and Sub-Threshold CMOS Logic Circuits (2013) (12)
- Flip-Flop Design in Nanometer CMOS: From High Speed to Low Energy (2014) (12)
- Leakage Power Analysis attacks: Effectiveness on DPA resistant logic styles under process variations (2011) (11)
- Integrated Power Management for Battery-Indifferent Systems With Ultra-Wide Adaptation Down to nW (2020) (11)
- Interconnect-Aware Design of Fast Large Fan-In CMOS Multiplexers (2007) (11)
- Power-Delay-Area-Noise Margin Trade-offs in Positive-Feedback Source-Coupled Logic Gates (2007) (11)
- A 0.6-to-1.8V CMOS Current Reference With Near-100% Power Utilization (2021) (11)
- Power analysis attacks to cryptographic circuits: a comparative analysis of DPA and CPA (2008) (11)
- Leakage Power Analysis attacks against a bit slice implementation of the Serpent block cipher (2014) (11)
- A Robust, High-Speed and Energy-Efficient Ultralow-Voltage Level Shifter (2021) (10)
- Positive-Feedback Source-Coupled Logic: a delay model (2004) (10)
- Analysis and comparison of variations in double edge triggered flip-flops (2014) (10)
- Efficient Post-Processing Module for a Chaos-based Random Bit Generator (2006) (10)
- Analysis and design of ultra-low power subthreshold MCML gates (2009) (10)
- Improving the power-delay product in SCL circuits using source follower output stage (2008) (10)
- Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS (2018) (9)
- Analysis and evaluation of layout density of FinFET logic gates (2009) (9)
- ±CIM SRAM for Signed In-Memory Broad-Purpose Computing From DSP to Neural Processing (2021) (9)
- 36.1 Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security (2021) (9)
- Delay Variability Due to Supply Variations in Transmission-Gate Full Adders (2007) (9)
- Very high-speed carry computation based on mixed dynamic/transmission-gate Full Adders (2007) (9)
- Design-Oriented Energy Models for Wide Voltage Scaling Down to the Minimum Energy Point (2017) (9)
- Power Modeling of Precharged Address Bus and Application to Multi-bit DPA Attacks to DES Algorithm (2006) (9)
- Approximate Multipliers With Dynamic Truncation for Energy Reduction via Graceful Quality Degradation (2020) (9)
- Power-delay trade-offs in SCL gates (2002) (9)
- Optimized design of parallel carry-select adders (2011) (9)
- A reconfigurable sense amplifier with 3X offset reduction in 28nm FDSOI CMOS (2015) (9)
- High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology (2007) (9)
- Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits (2015) (8)
- Wake-Up Oscillators with pW Power Consumption in Dynamic Leakage Suppression Logic (2019) (8)
- Low-Energy Voice Activity Detection via Energy-Quality Scaling From Data Conversion to Machine Learning (2020) (8)
- Better-than-voltage scaling energy reduction in approximate SRAMs via bit dropping and bit reuse (2015) (8)
- A 300mV-Supply, Sub-nW-Power Digital-Based Operational Transconductance Amplifier (2021) (8)
- Guest Editorial Energy-Quality Scalable Circuits and Systems for Sensing and Computing: From Approximate to Communication-Inspired and Learning-Based (2018) (8)
- Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction (2009) (8)
- The digital Tent map: performance analysis and optimized design as a source of pseudo-random bits (2004) (8)
- Analysis and Comparison in the Energy-Delay-Area Domain (2015) (8)
- Leakage Power Analysis attacks: Theoretical analysis and impact of variations (2009) (8)
- Capacitance-to-Digital Converter for Operation Under Uncertain Harvested Voltage down to 0.3V with No Trimming, Reference and Voltage Regulation (2021) (8)
- Analysis and comparison of low-voltage CML D-latch (2002) (8)
- Nanometer MCML gates: models and design considerations (2006) (7)
- Design of MUX, XOR and D-latch SCL gates (2003) (7)
- Delay estimation of SCL gates with output buffer (2001) (7)
- Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs (2016) (7)
- Guest Editorial Special Issue on Circuits and Systems for the Internet of Things - From Sensing to Sensemaking (2017) (7)
- Optimized design of high fan-in multiplexers using tri-state buffers (2002) (7)
- Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling (2012) (7)
- On upsizing length and noise margins (2013) (7)
- Multi-Sensor Platform with Five-Order-of-Magnitude System Power Adaptation down to 3.1nW and Sustained Operation under Moonlight Harvesting (2020) (7)
- On the Suitability of Digital Maps for Integrated Pseudo-RNGs. (2003) (7)
- Tapered-VTH CMOS buffer design for improved energy efficiency in deep nanometer technology (2011) (7)
- Analysis and performance evaluation of area-efficient true random bit generators on FPGAs (2008) (7)
- Boosted sensing for enhanced read stability in STT-MRAMs (2016) (7)
- Reconfigurable sleep transistor for GIDL reduction in ultra-low standby power systems (2012) (7)
- A novel back-biasing low-leakage technique for FinFET forced stacks (2011) (7)
- An efficient implementation of PRNGs based on the digital sawtooth map (2004) (7)
- A simple keeper topology to reduce delay variations in nanometer domino logic (2012) (6)
- Metrics and design considerations on the energy-delay tradeoff of digital circuits (2009) (6)
- 26.3 Reconfigurable clock networks for random skew mitigation from subthreshold to nominal voltage (2017) (6)
- Adaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling (2020) (6)
- Modeling of Delay Variability Due to Supply Variations in Pass-Transistor and Static Full Adders (2006) (6)
- Enabling Ubiquitous Hardware Security via Energy-Efficient Primitives and Systems : (Invited Paper) (2019) (6)
- EQSCALE: Energy-quality scalable feature extraction engine for Sub-mW real-time video processing with 0.55 mm2 area in 40nm CMOS (2017) (6)
- Tapered-Vth Approach for Energy-Efficient CMOS Buffers (2011) (6)
- Flip-Flop Design in Nanometer CMOS (2015) (6)
- Exploiting locality to improve leakage reduction in embedded drowsy I-caches at same area/speed (2010) (6)
- Power-delay optimization of D-latch/MUX source coupled logic gates: Research Articles (2005) (6)
- A general model of DPA attacks to precharged busses in symmetric-key cryptographic algorithms (2007) (6)
- Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping (2016) (6)
- Energy-performance design exploration of a low-power microprogrammed deep-learning accelerator (2018) (5)
- Modeling the impact of dynamic voltage scaling on 1T-1J STT-RAM write energy and performance (2015) (5)
- Analysis of the impact of process variations on static logic circuits versus fan-in (2008) (5)
- In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security (2022) (5)
- Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis (2006) (5)
- Transistor sizing strategy for simultaneous energy-delay optimization in CMOS buffers (2017) (5)
- From Less Batteries to Battery-Less Alert Systems with Wide Power Adaptation down to nWs—Toward a Smarter, Greener World (2021) (5)
- Analysis and Modeling of Energy Consumption in RLC Tree Circuits (2009) (5)
- Modeling strategies of the input admittance of RC interconnects for VLSI CAD tools (2011) (5)
- Closed-form analysis of DC noise immunity in subthreshold CMOS logic circuits (2010) (5)
- Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates (2000) (5)
- Battery-Less IoT Sensor Node with PLL-Less WiFi Backscattering Communications in a 2.5-μW Peak Power Envelope (2021) (5)
- Delay uncertainty due to supply variations in static and dynamic full adders (2006) (5)
- Optimized Design of Carry-Bypass Adders (2001) (5)
- Trading off static power and dynamic performance in CMOS digital circuits: bulk versus double gate SOI MOSFETs (2007) (5)
- Evaluation of power consumption in adiabatic circuits (2000) (5)
- Power-precision scalable latch memories (2017) (4)
- Ultra-low voltage standard cell libraries: Design strategies and a case study (2016) (4)
- Analysis and design of digital PRNGS based on the discretized sawtooth map (2003) (4)
- Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects (2007) (4)
- Long period pseudo random bit generators derived from a discretized chaotic map (2005) (4)
- Optimization of the wire grid size for differential routing: Analysis and impact on the power-delay-area tradeoff (2010) (4)
- Automated Design of Reconfigurable Microarchitectures for Accelerators Under Wide-Voltage Scaling (2020) (4)
- CML ring oscillators: oscillation frequency (2001) (4)
- Circuit Techniques to Reduce the Supply Voltage Limit of Subthreshold MCML Circuits (2008) (4)
- Drop-In Energy-Performance Range Extension in Microcontrollers Beyond VDD Scaling (2019) (4)
- Low-standby current 4T FinFET buffers: Analysis and evaluation below 45 nm (2010) (4)
- Reconfigurable Clock Networks for Wide Voltage Scaling (2019) (4)
- A Simple and Accurate Model of Input capacitance for Power Estimation in CMOS logic (2007) (4)
- A general model for differential power analysis attacks to static logic circuits (2008) (4)
- Fully-Synthesizable Current-Input ADCs for Ultra-Low Area and Minimal Design Effort (2019) (4)
- 45pW ESD clamp circuit for ultra-low power applications (2013) (4)
- A variation-aware simulation framework for hybrid CMOS/spintronic circuits (2017) (4)
- Side-Channel Attack Counteraction via Machine Learning-Targeted Power Compensation for Post-Silicon HW Security Patching (2022) (4)
- Broad-Purpose In-Memory Computing for Signal Monitoring and Machine Learning Workloads (2020) (4)
- PUF Architecture with Run-Time Adaptation for Resilient and Energy-Efficient Key Generation via Sensor Fusion (2021) (3)
- Design metrics for RTL level estimation of delay variability due to intradie (random) variations (2010) (3)
- Processor Energy–Performance Range Extension Beyond Voltage Scaling via Drop-In Methodologies (2020) (3)
- Low-Swing Links with Dynamic Energy-Quality Trade-off for Error-Resilient Applications (2019) (3)
- Clock distribution in clock domains with Dual-Edge-Triggered Flip-Flops to improve energy-efficiency (2010) (3)
- A closed-form energy model for VLSI circuits under wide voltage scaling (2016) (3)
- 8 A 32 kb SRAM for Error-Free and Error-Tolerant Applications with Dynamic Energy-Quality Management in 28 nm CMOS (2018) (3)
- Ultra-Low Power and Minimal Design Effort Interfaces for the Internet of Things: Invited paper (2019) (3)
- Integrated Power Management and Microcontroller for Ultra-Wide Power Adaptation down to nW (2019) (3)
- Ultra-Low Power Crypto-Engine Based on Simon 32/64 for Energy- and Area-Constrained Integrated Systems (2018) (3)
- II-245 ECCTD ’ 01-European Conference on Circuit Theory and Design , August 28-31 , 2001 , Espoo , Finland Optimized Design of Carry-Bypass Adders (2001) (3)
- Optimized design of high fan-in multiplexers using switches with driving capability (2001) (3)
- Security Down to the Hardware Level (2017) (3)
- Design guidelines for bipolar frequency dividers (2002) (3)
- Display Stream Compression Encoder Architectures for Real-time 4K and 8K Video Encoding (2018) (3)
- Modelling and design considerations on CML gates under high‐current effects (2005) (3)
- Very fast carry energy efficient computation based on mixed dynamic=transmission-gate full adders (2007) (3)
- Analysis and design of MCML gates with hysteresis (2006) (3)
- Sub-nW Microcontroller With Dual-Mode Logic and Self-Startup for Battery-Indifferent Sensor Nodes (2021) (3)
- Project-Based Learning in Digital Fundamentals Course Using FPGAs (2018) (2)
- A technique to design high entropy chaos-based true random bit generators (2006) (2)
- Design strategies of cascaded CML gates (2006) (2)
- Hardware-efficient PRBGs based on 1-D piecewise linear chaotic maps (2004) (2)
- Physical design aware selection of energy-efficient and low-energy nanometer flip-flops (2010) (2)
- Efficient and Accurate Models of Output Transition Time in CMOS Logic (2007) (2)
- Design techniques for low-power cascaded CML gates (2005) (2)
- Performance and impact of process variations in Tunnel-FET ultra-low voltage digital circuits (2014) (2)
- TempDiff: Feature Map-Level CNN Sparsity Enhancement at Near-Zero Memory Overhead via Temporal Difference (2021) (2)
- An Approach to Energy Consumption Modeling in RC Ladder Circuits (2002) (2)
- Imager with Dynamic LSB Adaptation and Ratiometric Readout for Low-Bit Depth 5-μW Peak Power in Purely-Harvested Systems (2022) (2)
- An efficient implementation of PRNGs based on the digital sawtooth map: Research Articles (2004) (2)
- Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates (2002) (2)
- STT-MRAM Architecture with Parallel Accumulator for In-Memory Binary Neural Networks (2021) (2)
- A fully-synthesizable C-element based PUF featuring temperature variation compensation with native 2.8% BER, 1.02fJ/b at 0.8–1.0V in 40nm (2017) (2)
- Analysis of the impact of random process variations in CMOS tapered buffers (2009) (2)
- Deep Sub-pJ/Bit Low-Area Energy-Security Scalable SIMON Crypto-Core in 40 nm (2020) (2)
- EChO power management unit with reconfigurable switched-capacitor converter in 65 nm CMOS (2012) (2)
- Maximum-Period PRNGs Derived From A Piecewise Linear One-Dimensional Map (2007) (2)
- SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm2 and 749-1,459 TOPS/W in 28nm (2021) (2)
- Design of low-power high-speed bipolar frequency dividers (2002) (2)
- STT-BNN: A Novel STT-MRAM In-Memory Computing Macro for Binary Neural Networks (2022) (2)
- Near-Threshold Digital Circuits for Nearly-Minimum Energy Processing (2017) (2)
- Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic (2009) (2)
- Comparative analysis of the robustness of master-slave flip-flops against variations (2015) (2)
- ECCTD ’ 01-European Conference on Circuit Theory and Design , August 28-31 , 2001 , Espoo , Finland Predicting Propagation Delay in SCL Gates (2001) (2)
- Design of nanometer MOS Current Mode Logic: From very high-speed down to ultra-low power (2009) (2)
- Mixed Techniques to Protect Precharged Busses against Differential Power Analysis Attacks (2007) (2)
- Simple and accurate modeling of the output transition time in nanometer CMOS gates (2010) (2)
- TempDiff: Temporal Difference-Based Feature Map-Level Sparsity Induction in CNNs with <4% Memory Overhead (2021) (2)
- Mixed Logic Styles for High-Speed Low-Power Arithmetic Circuits (2)
- Energy consumption in RLC tree circuits (2007) (2)
- Compact and simple output transition time model in nanometer CMOS gates (2008) (2)
- STT-MRAM memories for IoT applications: Challenges and opportunities at circuit level and above (2017) (2)
- Fully Synthesizable Unified True Random Number Generator and Cryptographic Core (2021) (2)
- Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling (2011) (1)
- DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nm (2022) (1)
- An Energy Aware Variation-Tolerant Writing Termination Control for STT-based Non Volatile Flip-Flops (2019) (1)
- Device-circuit co-design and comparison of ultra-low voltage Tunnel-FET and CMOS digital circuits (2014) (1)
- Editorial (2017) (1)
- Integrated Power Management and Microcontroller for Ultra-Wide Power Adaptation down to nW (2019) (1)
- New Techniques for low power caches (2005) (1)
- High-speed bipolar MUX modeling and design (2000) (1)
- Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits (2009) (1)
- 45 pW ESD Clamp Circuit for Ultra-Low Power Applications (2018) (1)
- A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2,200-μm2 Area in 180nm (2020) (1)
- Novel Time-Based Sensing Scheme for STT-MRAMs (2018) (1)
- A 346μm2 reference-free sensor interface for highly constrained microsystems in 28nm CMOS (2013) (1)
- A Design Methodology for High-Speed Low-Power MCML Frequency Dividers (2006) (1)
- Implementation-Efficient Maximum-Period Nonlinear Congruential Generators (2007) (1)
- Minimum-Effort Design of Ultra-Low Power Interfaces for the Internet of Things (2019) (1)
- On-Chip Laser Voltage Probing Attack Detection with 100% Area Coverage at Above/Below the Bandgap Wavelength and Fully-Automated Design (2022) (1)
- Experimental study of leakage-delay trade-off in Germanium pMOSFETs for logic circuits (2010) (1)
- Voltage Reference With Corner-Aware Replica Selection/Merging for 1.4-mV Accuracy in Harvested Systems Down to 3.9 pW, 0.2 V (2023) (1)
- Reconfigurable Clock Networks, Automated Design Flows, Run-Time Optimization, and Case Study (2020) (1)
- Power-delay optimization in MCML tapered buffers (2008) (1)
- Energy-Quality Scalable Memory-Frugal Feature Extraction for Always-On Deep Sub-mW Distributed Vision (2020) (1)
- Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory (2019) (1)
- A scalable low-entropy detector to counteract the parameter variability effects in TRBGs (2010) (1)
- Modelling and design considerations on CML gates under high-current effects: Research Articles (2005) (1)
- Sub-nm EOT high-mobility SiGe-55% channel pFETs: Delivering high performance at scaled VDD (2010) (1)
- PVT variations in differential flip-flops: A comparative analysis (2015) (1)
- Design of cascaded ECL gates with power constraint (2006) (1)
- Fully Synthesizable All-Digital Unified Dynamic Entropy Generation, Extraction, and Utilization Within the Same Cryptographic Core (2020) (1)
- Fully-Digital Broadband Calibration-Less Impedance Monitor for Probe Insertion Detection against Power Analysis Attacks (2022) (1)
- Automated Design of Reconfigurable Microarchitectures for Accelerators under Wide-Voltage Scaling (2020) (1)
- Capacitance-Based Voltage Regulation- and Reference-Free Temperature-to-Digital Converter down to 0.3 V and 2.5 nW for Direct Harvesting (2022) (1)
- A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy (2021) (1)
- From Less Batteries to Battery-Less: Enabling A Greener World through Ultra-Wide Power-Performance Adaptation down to pWs (2022) (0)
- CAD models of the input admittance of RC wires: Comparison and selection strategies (2008) (0)
- Aggressive Design Reuse for Ubiquitous Zero-Trust Edge Security—From Physical Design to Machine-Learning-Based Hardware Patching (2023) (0)
- Enabling Always-On Sensor Nodes Entirely Powered by Sustainable Energy Sources - Making Our World Smarter and Greener (2020) (0)
- Comparative evaluation of Tunnel-FET ultra-low voltage SRAM bitcell and impact of variations (2014) (0)
- Conversion Time-Power Tradeoff in Capacitance-to-Digital Converters with Dual-Mode Logic (2022) (0)
- Introduction (2020) (0)
- Understanding loading effects of RC uniform interconnects (2009) (0)
- Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits (2010) (0)
- Editorial First TVLSI Best AE and Reviewer Awards (2016) (0)
- On-Chip Links With Energy-Quality Tradeoff in Error-Resilient and Machine Learning Applications (2021) (0)
- Dependence of Differential flip-flops performance on clock slope and relaxation of clock network design (2009) (0)
- Second Quarter of the 2021 Editorial Year - A Year in Crescendo (2021) (0)
- Energy Efficiency Versus Clock Slope (2015) (0)
- Hold Time Issues and Impact of Variations on Flip-Flop Topologies (2015) (0)
- Design of CML gate with the best propagation delay (1998) (0)
- ATechnique toDesign HighEntropy Chaos-Based TrueRandomBitGenerators (2006) (0)
- Case Studies of Reconfigurable Microarchitectures: Accelerators, Microprocessors, and Memories (2020) (0)
- Clocked Storage Elements (2015) (0)
- Explicit energy evaluation in RLC tree circuits with ramp inputs (2008) (0)
- Energy-Quality Scalable Analog-to-Digital Conversion and Machine Learning Engine in a 51.9 nJ/frame Voice Activity Detector (2019) (0)
- Opening of the 2021 Editorial Year - Overture for a New Year of Change (2021) (0)
- Guest Editorial Special Issue on Selected Papers from PRIME 2017 and SMACD 2017 (2018) (0)
- Optimization and evaluation of tapered-VTH approach for energy-efficient CMOS buffers (2011) (0)
- Analysis andDesign of MCML Gates withHysteresis (2006) (0)
- Variability budgetin pulsed flip-flops (2015) (0)
- International Solid-State Circuits Conference ISSCC 2016 / SESSION 8 / LOW-POWER DIGITAL CIRCUITS / 8 . 8 8 . 8 iRazor : 3-Transistor Current-Based Error Detection and Correction in an ARM Cortex-R 4 Processor (2017) (0)
- Energy evaluation in RLC tree circuits with exponential input (2008) (0)
- Efficient output transition time modeling in CMOS gates with ramp/exponential inputs (2006) (0)
- Optimization of wire grid size for differential routing and impact on the power-delay-area tradeoff (2009) (0)
- Ultra-Fast and Energy-Efficient Pulsed Latch Topologies (2015) (0)
- PUF-based Key Generation with Design Margin Reduction via In-Situ and PVT Sensor Fusion (2019) (0)
- Impact of clock slope on energy/delay of pulsed flip-flops and optimum clock domain design (2009) (0)
- Last-Round and Joint First/Last-Round Power Analysis Attacks on PRESENT (2021) (0)
- Optimum clock slope for flip-flops within a clock domain: Analysis and a case study (2009) (0)
- IEEE Circuits and Systems Society (2018) (0)
- 2018 SOCC Organizing Committee (2018) (0)
- Conclusions (2020) (0)
- Design in the Energy-Delay Space (2015) (0)
- STT-MRAM write energy minimization via area optimization under dynamic voltage Scaling (2016) (0)
- Thursday Keynote: Survival of The Fittest: Circuits and Architectures for Computation with Wide Power- Performance Adaptation Beyond Voltage Scaling (2019) (0)
- Low-overhead countermeasures to protect Pre-charged busses against Power Analysis attacks (2009) (0)
- Voice Activity Detection with >83% Accuracy under SNR down to −3dB at $1.19\mu \mathrm{W}$ and 0.07mm2 in 40nm (2020) (0)
- STT-BNN: A Novel Energy-efficient and Scalable BNN Accelerator Based on STT-MRAM (2021) (0)
- The Logical Effort Method (2015) (0)
- Reconfigurable Microarchitecures Down to Pipestage and Memory Bank Level (2020) (0)
- Introduction to the special issue on IEEE-NEWCAS 2012 (2013) (0)
- Jitter analysis and measurement in subthreshold source-coupled differential ring oscillators (2015) (0)
- Design of CML gate propagation with the best delay (1998) (0)
- Novel simple models of CML propagation delay (1998) (0)
- Design-oriented models for quick estimation of path delay variability via the fan-out-of-4 metric (2017) (0)
- Energy-Quality Scalable Integrated Systems - Preserving Energy Downscaling in the Decade Ahead (2019) (0)
- Editorial on the Conclusion of the 2020 Editorial Year - The Climactic Finale of a Peculiar Year (2020) (0)
- Special issue on IEEE-NEWCAS 2012 (2013) (0)
- Correct procedures to evaluate the effect of intradie variations on the delay variability of digital circuits (2009) (0)
- A 1448-Mpixel/s, 84-pJ/Pixel Display Stream Compression Encoder in 28 nm for 4K Video Resolution (2021) (0)
- Maximum-Period Nonlinear Congruential Generators (2007) (0)
- Tapered-Vth Approach for Energy-Efficient (2011) (0)
- Fully-Digital Self-Calibrating Decoder with Sub-µW, 1.6fJ/convstep and 0.0075mm2 per Receptor for Scaling to Human-Like Tactile Sensing Density (2021) (0)
- Session 36 Overview: Hardware Security Digital Architectures and Systems Subcommittee (2021) (0)
- Flip-Flop Optimized Design (2015) (0)
- Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical Model (2005) (0)
- Welcome message from the technical program chairs (2016) (0)
- MODELING OF DELAY VARIABILITYDUE TO SUPPLYVARIATIONSIN PASS-TRANSISTORAND STATICFULLADDERS (2006) (0)
- New topic session 7B: Challenges and directions for ultra-low voltage VLSI circuits and systems: CMOS and beyond (2013) (0)
- Capacitance-to-Digital Converter for Harvested Systems Down to 0.3 V With No Trimming, Reference, and Voltage Regulation (2023) (0)
- F4: Electronics for a Quantum World (2021) (0)
- 1 DESIGN IN THE ENERGY – DELAY SPACE (2012) (0)
- Automated Design Flows and Run-Time Optimization for Reconfigurable Microarchitecures (2020) (0)
- Editorial Opening of the 2022 TVLSI Editorial Year - Connecting Trends From Society to VLSI Systems (2022) (0)
- Editorial: TVLSI Keynote Papers Enriching Our Transactions With Invited Contributions (2019) (0)
- Power-Delay Optimized Design of Cascaded ECL Gates (2006) (0)
- Early assessment of emerging technologies for VLSI logic circuits from experimental measurements (2012) (0)
- Voice Activity Detection with >83% Accuracy under SNR down to -3dB at 1.19µW and 0.07mm2 in 40nm (2020) (0)
- Editorial (2017) (0)
- A delay model of CML gates valid under high-current effects (2003) (0)
- Nanometer flip-flops design in the E-D space (2010) (0)
- 55pW/pixel Peak Power Imager with Near-Sensor Novelty/Edge Detection and DC-DC Converter-Less MPPT for Purely Harvested Sensor Nodes (2023) (0)
- Panel discussion: Distributed intelligence in IoT (2016) (0)
- SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm2 and 749-1,459 TOPS/W in 28nm (2021) (0)
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