Michael. Nicolaidis

Michael. Nicolaidis's AcademicInfluence.com Rankings

Michael. Nicolaidis

Engineering

#7188

World Rank

#8551

Historical Rank

Electrical Engineering

#2219

World Rank

#2325

Historical Rank

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Engineering

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Michael. Nicolaidis's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Upset hardened memory design for submicron CMOS technology (1996) (1079)
Time redundancy based soft-error tolerance to rescue nanometer technologies (1999) (510)
Design for soft error mitigation (2005) (399)
On-Line Testing for VLSI—A Compendium of Approaches (1998) (250)
Soft Errors in Modern Electronic Systems (2010) (234)
Cost reduction and evaluation of temporary faults detecting technique (2000) (173)
Strongly Code Disjoint Checkers (1988) (141)
Embedded robustness IPs for transient-error-free ICs (2002) (136)
Evaluation of a soft error tolerance technique based on time and/or space redundancy (2000) (129)
Carry checking/parity prediction adders and ALUs (2003) (127)
An SFS Berger check prediction ALU and its application to self-checking processor designs (1992) (116)
SEU-tolerant SRAM design based on current monitoring (1994) (111)
Efficient implementations of self-checking adders and ALUs (1993) (104)
Theory of Transparent BIST for RAMs (1996) (101)
TRANSPARENT BIST FOR RAMS (1992) (93)
Low-Cost Highly-Robust Hardened Cells Using Blocking Feedback Transistors (2008) (82)
Fault-Secure Parity Prediction Arithmetic Operators (1997) (82)
An efficient BICS design for SEUs detection and correction in semiconductor memories (2005) (80)
Deep submicron CMOS technologies for the LHC experiments (1999) (76)
New methods for evaluating the impact of single event transients in VDSM ICs (2002) (75)
Reliability challenges of real-time systems in forthcoming technology nodes (2013) (74)
Cost reduction and evaluation of a temporary faults detecting technique (2000) (68)
GRAAL: a new fault tolerant design paradigm for mitigating the flaws of deep nanometric technologies (2007) (66)
A diversified memory built-in self-repair approach for nanotechnologies (2004) (63)
Dynamic data-bit memory built-in self-repair (2003) (61)
Self-exercising checkers for unified built-in self-test (UBIST) (1989) (60)
A generalized theory of fail-safe systems (1989) (55)
SEU-hardened storage cell validation using a pulsed laser (1996) (51)
Single event effects in static and dynamic registers in a 0.25 /spl mu/m CMOS technology (1999) (49)
Programmable memory BIST (2005) (48)
Total dose and Single Event Effects (SEE) in a 0.25 µm CMOS technology (1998) (47)
Design for soft-error robustness to rescue deep submicron scaling (1998) (45)
Shorts in self-checking circuits (1991) (43)
Design of static CMOS self-checking circuits using built-in current sensing (1992) (42)
Fault secure property versus strongly code disjoint checkers (1994) (41)
Measuring the width of transient pulses induced by ionising radiation (2003) (41)
Fault-Tolerant Deadlock-Free Adaptive Routing for Any Set of Link and Node Failures in Multi-cores Systems (2010) (39)
A CAD framework for generating self-checking multipliers based on residue codes (1999) (37)
Fault-Secure Parity Prediction Booth Multipliers (1999) (36)
Defects Tolerant Logic Gates for Unreliable Future Nanotechnologies (2007) (36)
Testing complex couplings in multiport memories (1995) (36)
Optimal reconfiguration functions for column or data-bit built-in self-repair (2003) (36)
On-line testing for VLSI: state of the art and trends (1998) (36)
A fault-tolerant deadlock-free adaptive routing for on chip interconnects (2011) (33)
Upset-tolerant CMOS SRAM using current monitoring: prototype and test experiments (1995) (32)
An Unified Built in Self-Test Scheme : UBIST (1986) (31)
Simulating Single Event Transients in VDSM ICs for Ground Level Radiation (2002) (30)
Fail-Safe Interfaces for VLSI: Theoretical Foundations and Implementation (1998) (29)
A Practical Approach to Single Event Transient Analysis for Highly Complex Design (2013) (29)
A digital BIST for operational amplifiers embedded in mixed-signal circuits (1999) (27)
Single Event Effects in Static and Dynamic Registers in a 0 . 25 μ m CMOS Technology (1999) (27)
Achieving fault secureness in parity prediction arithmetic operators: general conditions and implementations (1996) (27)
A low-cost, highly reliable SEU-tolerant SRAM: prototype and test results (1995) (26)
A unified built-in-test scheme: UBIST (1988) (26)
Radiation induced single-word multiple-bit upsets correction in SRAM (2005) (24)
Design of built-in current sensors for concurrent checking in radiation environments (1993) (23)
Self-checking circuits versus realistic faults in very deep submicron (2000) (23)
Circuit-Level Soft-Error Mitigation (2011) (22)
Built-in self-test in multi-port RAMs (1991) (22)
Concurrent Checking for VLSI (1999) (22)
New Techniques for SET Sensitivity and Propagation Measurement in Flash-Based FPGAs (2014) (22)
A Practical Approach to Single Event Transient Analysis for Highly Complex Design (2011) (22)
A tool for automatic generation of BISTed and transparent BISTed RAMs (1992) (21)
A low-cost single-event latchup mitigation scheme (2006) (19)
Topology-related upset mechanisms in design hardened storage cells (1997) (19)
On-line testing for VLSI (1997) (19)
Finitely self-checking circuits and their application on current sensors (1993) (18)
Design of fault-secure parity-prediction Booth multipliers (1998) (18)
A Transparent based Programmable Memory BIST (2006) (18)
Memory built-in self-repair for nanotechnologies (2003) (17)
A tool for automatic generation of self-checking data paths (1995) (17)
Efficient implementations of self-checking multiply and divide arrays (1994) (16)
Embedded robustness IPs (2002) (16)
RIIF - Reliability information interchange format (2012) (16)
Through-silicon-via built-in self-repair for aggressive 3D integration (2012) (16)
Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor (2011) (16)
A strongly code disjoint built-in current sensor for strongly fault-secure static CMOS realizations (1995) (15)
Scaling deeper to submicron: on-line testing to the rescue (1998) (15)
Double-Sampling Design Paradigm—A Compendium of Architectures (2015) (14)
New implementations, tools, and experiments for decreasing self-checking PLAs area overhead (1991) (14)
On-line BIST for testing analog circuits (1999) (14)
An iterative diagnosis approach for ECC-based memory repair (2013) (14)
Reducing power dissipation in memory repair for high defect densities (2013) (13)
An effective approach to detect logic soft errors in digital circuits based on GRAAL (2009) (13)
Self-checking logic arrays (1989) (12)
Design for test and reliability in ultimate CMOS (2012) (12)
An approach to the on-line testing of operational amplifiers (1998) (12)
Evaluation of a self-checking version of the mc 68000 microprocessor (1987) (11)
Efficient UBIST implementation for microprocessor sequencing parts (1990) (11)
Clustering techniques and statistical fault injection for selective mitigation of SEUs in flip-flops (2013) (11)
A Test Methodology Applied to Cellular Logic Programmable Gate Arrays (1994) (11)
Addressing transient routing errors in fault-tolerant Networks-on-Chips (2016) (11)
Built-in current sensor for IDDQ testing in deep submicron CMOS (1999) (11)
Self-Recovering Parallel Applications in Multi-core Systems (2011) (11)
Design techniques for soft-error mitigation (2010) (11)
IC Reliability and Test: What Will Deep Submicron Bring? (1999) (11)
A D&T Roundtable: Online Test (1999) (11)
Scaling deeper to submicron: on-line testing to the rescue (1999) (11)
Variability-aware task mapping strategies for many-cores processor chips (2011) (11)
Online VLSI Testing (1998) (10)
Efficient Totally Self-Checking Shifter Design (1998) (10)
Evaluation of memory built-in self repair techniques for high defect density technologies (2004) (10)
Fault-secure shifter design: results and implementations (1997) (10)
Fault-tolerant adaptive routing under an unconstrained set of node and link failures for many-core systems-on-chip (2014) (10)
UBIST version of the SYCO's control section compiler (1988) (10)
Rout3D: A lightweight adaptive routing algorithm for tolerating faulty vertical links in 3D-NoCs (2017) (10)
Transparent BIST for ECC-based memory repair (2013) (10)
Test algorithms for ECC-based memory repair in nanotechnologies (2012) (10)
A CAD framework for efficient self-checking data path design (1997) (10)
Quiescent current monitoring to improve the reliability of electronic systems in space radiation environments (1993) (9)
Eliminating speed penalty in ECC protected memories (2011) (9)
Test Algorithms for ECC-Based Memory Repair in Ultimate CMOS and Post-CMOS (2016) (9)
Design trends and challenges of logic soft errors in future nanotechnologies circuits reliability (2008) (9)
Design for mitigation of single event effects (2005) (8)
Current-based testing for analog and mixed-signal circuits (1998) (8)
Memory Defect Tolerance Architectures for Nanotechnologies (2005) (8)
10th IEEE International On-Line Testing Symposium (2004) (8)
AC/DC BIST for testing analog circuits (1999) (8)
Biologically Inspired Robust Tera-Device Processors (2012) (8)
MINI-ESPADA: A low-cost fully adaptive routing mechanism for Networks-on-Chips (2017) (8)
CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems (2012) (8)
Double-sampling architectures (2014) (8)
Hardware Fault Injection (2011) (7)
Aliasing-free signature analysis for RAM BIST (1994) (7)
A new approach to deadlock-free fully adaptive routing for high-performance fault-tolerant NoCs (2016) (7)
A memory built-in self-repair for high defect densities based on error polarities (2003) (7)
A theory of perturbation tolerant asynchronous FSMs and its application on the design of perturbation tolerant memories (1997) (6)
Efficient UBIST for RAMs (1994) (6)
Exact aliasing computation for RAM BIST (1995) (6)
A Dynamic Sufficient Condition of Deadlock-Freedom for High-Performance Fault-Tolerant Routing in Networks-on-Chips (2017) (6)
Detailed and highly parallelizable cycle-accurate network-on-chip simulation on GPGPU (2017) (6)
MUGEN: A high-performance fault-tolerant routing algorithm for unreliable Networks-on-Chip (2015) (6)
Using Error Correcting Codes Without Speed Penalty in Embedded Memories: Algorithm, Implementation and Case Study (2013) (5)
I-BIRAS: Interconnect Built-In Self-Repair and Adaptive Serialization in 3D Integrated Systems (2011) (5)
Designing Single-Chip Massively Parallel Tera-Device Processors: Towards the Terminator Chip (2011) (5)
Improving the theory of truth table verification of iterative logic arrays (1992) (5)
Defect Tolerant Logic Gates for Unreliable Future Nanotechnologies (2007) (5)
Quiescent current estimation based on quality requirements (1993) (5)
GRAAL: A Fault-Tolerant Architecture for Enabling Nanometric Technologies (2007) (5)
Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip (2013) (5)
IP for embedded robustness (2002) (5)
ISIS: A Fail-Safe Interface Realized in Smart Power Technology (2000) (4)
Variability-aware and fault-tolerant self-adaptive applications for many-core chips (2013) (4)
Trade-offs in scan path and BIST implementations for RAMs (1993) (4)
Current-testable high-frequency CMOS operational amplifiers (1998) (4)
Designing Single Chip Massively Parallel Processors Affected by Extreme Failure Rates (2012) (4)
Robustness IPs for reliability and security of SoCs (2002) (4)
A GENERALIZED THEORY OF FAIL+SAFE SYSTEMS (1995) (4)
Low-power memory repair for high defect densities (2015) (4)
Enhanced self-configurability and yield in multicore grids (2009) (4)
Variability and reliability-aware application tasks scheduling and power control (Voltage and Frequency Scaling) in the future nanoscale multiprocessors system on chip (2009) (4)
A self-checking PLA automatic generator tool based on unordered codes encoding (1991) (4)
Fault detection for linear analog circuits using current injection (1998) (4)
Second workshop on dependable and secure nanocomputing (2008) (4)
Workshop on Dependable and Secure Nanocomputing (2007) (4)
Interconnect Built-In Self-Repair and Adaptive-Serialization (I-BIRAS) for 3D integrated systems (2010) (3)
Verification of self-checking properties by means of output code space computation (1992) (3)
Advanced double-sampling architectures (2016) (3)
Microarchitecture of the MC 68000 and Evaluation of a Self Checking Version (1985) (3)
A Framework for Scalable TSV Assignment and Selection in Three-Dimensional Networks-on-Chips (2017) (3)
Computational Opportunities and CAD for Nanotechnologies (2010) (3)
Checking signatures on boundary scan boards (1993) (3)
Towards a holistic CAD platform for nanotechnologies (2007) (3)
VLSI implementation for control of critical systems (1989) (2)
Adaptive Mapping of Parallelized Application (Fork-join DAG) on Multicore System in the Presence of Multiple Failures (2012) (2)
Memory BIST with address programmability (2011) (2)
Built-in Self-Test of RAMs (1985) (2)
Easily testable carry-save multipliers with respect to path delay faults (1999) (2)
A tool for computation of output code spaces in complex self-checking systems (1991) (2)
Low cost rollback to improve fault-tolerance in VLSI circuits (2017) (2)
Area versus detection latency trade-offs in self-checking memory design (1995) (2)
Design of a Self-Checking Microprocessor for Real-Time Applications (1985) (2)
A new placement algorithm dedicated to parallel computers: bases and application (1999) (2)
Special Session 2: Benchmarking and Standardization in Software-Based SER Characterization: Towards an IEEE Task Force? (2008) (2)
Study of the radiation tolerance of ICs for LHC : 3rd status report (2000) (2)
Enhancing realistic fault secureness in parity prediction array arithmetic operators by I/sub DDQ/ monitoring (1996) (2)
Computational Space, Time and Quantum Mechanics (2009) (2)
Towards a tool for implementing delay-free ECC in embedded memories (2011) (2)
Design of Self-Checking Integrated Circuits and Boards (1991) (2)
Fail-safe synchronization circuit for duplicated systems (2001) (2)
Foreword to the Special Section on the IEEE International On-Line Testing and Robust System Design Symposium (IOLTS) 2016 (2017) (2)
Zero aliasing ROM BIST (1994) (2)
Simulating Time (2009) (2)
A generic and high-level model of large unreliable NoCs for fault tolerance and performance analysis (2014) (1)
Self-Checking Circuits: From Theory to Practice (1986) (1)
Iterative Diagnosis Approach for ECC-Based Memory Repair (2020) (1)
Complex Electronic Systems Soft Error Rate (SER) Management (2009) (1)
Reducing Rollback Cost in VLSI Circuits to Improve Fault Tolerance (2018) (1)
Simulation and mitigation of single event effects (2005) (1)
Memory repair for high defect densities (2015) (1)
A Fail-Safe Microcontroller for Railway Signalling (1990) (1)
Design for testability of on-line multipliers (1994) (1)
Performance improvement of fault-tolerant systems through chip-level current monitoring (1997) (1)
CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems (2011) (1)
Special Session 13A: Panel : Mitigating Reliability, Yield and Power Issues in Nano-CMOS: Design Problem or EDA Problem? (2008) (1)
Design of self-checking N-MOS (H-MOS) integrated circuits (1984) (1)
Analytic approach for error masking elimination in on-line multipliers (1995) (1)
Current-based testing for high-frequency CMOS operational amplifiers (1998) (1)
Guest Editors' Introduction: Online VLSI Testing (1998) (1)
E-groups: a new technique for fast backward propagation in system-level test generation (1996) (1)
A one-bit-signature BIST for embedded operational amplifiers in mixed-signal circuits based on the slew-rate detection (1999) (1)
Testing embedded single and multi-port RAMs using BIST and boundary scan (1992) (1)
Foreword to the Special Section on “Design for Reliability and Yield for Ultimate CMOS Technologies” (2015) (1)
Congestion-Aware Adaptive Routing in 2D-Mesh Multicores (2014) (1)
Asynchronous Current Monitors for Transient Fault Detection in Deep Submicron CMOS (1998) (0)
Tutorial Statement (2000) (0)
Guest Editorial (2002) (0)
Fast Standard Cells Statistical Characterization for SSTA Based on Design of Experiment Approach in 45nm MOSFETs Technology (2011) (0)
Proceedings on 4th IEEE International On-Line Testing Workshop, July 6-8, Capri, Italy (1997) (0)
From Nuclear Reaction to System Failures: Can We Address All Levels of Soft Errors Accurately? (2006) (0)
Generalized Fail-Safe Systems (1970) (0)
Robust massively parallel single-chip architectures Power management from the OS down to silicon Fault tolerant and self-adaptative architectures 3D NOC Robust Architectures Design in Reliability face to aging, process variation and soft errors Evaluation of robustness and qualification: radiation t (2018) (0)
Proceedings of 11th IEEE International On-Line Testing Symposium (IOLT 2005)Saint Raphael, French Riviera, France, July 6-8, 2005 (2004) (0)
Soft Error Protection for Embedded Memories (2002) (0)
Soft Errors and Tolerance for Soft Errors (2001) (0)
Silicon compilation of hierarchical control sections with unified BIST testability (1991) (0)
Reliability threats in VDSM - shortcomings in conventional test and fault tolerance alternatives (2003) (0)
Can Defect-Tolerant Chips Better Meet the Quality Challenge? (1996) (0)
2015 JETTA Reviewers (2016) (0)
Efficient Self-checking Arithmetic Fault-secure Parity Prediction Arithmetic Operators Ieee Design & Test of Computers (0)
9th IEEE International On-Line Testing Symposium (IOLTS 2003), Kos Island, Greece, July 7-9, 2003 (2002) (0)
An approach for designing total-dose tolerant MCMs based on current monitoring (1995) (0)
The Quest of the Ideal Error Detecting Architecture: The GRAAL Architecture (2021) (0)
The Cells Framework : Overal Description (2017) (0)
A Biologically Inspired EDA Framework for Nanotechnologies (2010) (0)
Proceedings 10th IEEE International On-Line Testing Symposium (2004) (0)
Hardware Fault-Tolerance Requirements for Very Deep Submicron (1998) (0)
Proceedings of 6th IEEE InternationalOn-Line Testing Workshop (IOLT 2000), July 3-5, 2000 Palma De Mallorca, Spain (2000) (0)
Using Error Correcting Codes Without Speed Penalty in Embedded Memories: Algorithm, Implementation and Case Study (2013) (0)
Emergence of Euclidian Geometry in a Computational Universe (2014) (0)
VDSM Reliability Issues in the Field (2001) (0)
Hot topic session 4A: Reliability analysis of complex digital systems (2013) (0)
Basic properties of strongly code disjoint checkers (1990) (0)
FIT Rate Calculation and Mitigation Techniques for Advanced Technologies and Automotive Applications (2018) (0)
On path delay fault testing of multiplexer-based shifters (1999) (0)
An ECC-Based Repair Approach with an Offset-Repair CAM for Mitigating the MBUs Affecting Repair CAM (2020) (0)
Guest Editorial Robust System Design: IEEE International On-Line Testing and Robust System Design Symposium (IOLTS) 2018 (2019) (0)
Session Abstract (2006) (0)
Design practices for better reliability and yield (tutorial) (2000) (0)
Strongly fail-safe interfaces based on concurrent checking (1994) (0)
hardened storage cell (2005) (0)
Fourth workshop on dependable and secure nanocomputing (2010) (0)
Designing reliable processor cores in ultimate CMOS and beyond: A double sampling solution (2018) (0)
Architecture de circuits protegee contre des perturbations (2002) (0)
Fail safe interface for appts control - has inputs for receiving two binary control signals and concurrent checker which provides error detection signal if error exists in input signals (1995) (0)
A Self-checking PIA Automatic Generator Tool Based on (1991) (0)
A safety microcontroller Dedicated to Railway control (1990) (0)
Proceedings on 2nd International On-Line Testing Workshop (IOLT'96), July 8-10, 1996, Biarritz - Saint-Jean-de-Luz, France (1996) (0)
Study of the Radiation Tolerance of ICs for LHC Co-Spokespersons : (1999) (0)
Third workshop on dependable and secure nanocomputing (2009) (0)
Proceedings on 3th IEEE International On-Line Testing Workshop (IOLT'97), July 7-9, 1997, Crete, Greece (1996) (0)
A reconfiguration device for a faulty memory (2006) (0)
Transient fault evaluation; soft error susceptibility; on-line testing and fault tolerance for signal integrity; concurrent monitors and diagnosis; coding techniques; in-field testing and diagnosis; on-line testing; high availability systems; secure and safe circuits and systems design; dependabilit (2013) (0)
Guest Editorial (1999) (0)

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Michael. Nicolaidis's Academic­Influence.com Rankings

Why Is Michael. Nicolaidis Influential?

Michael. Nicolaidis's Published Works

Published Works

What Schools Are Affiliated With Michael. Nicolaidis?

Michael. Nicolaidis's AcademicInfluence.com Rankings