Michael Orshansky
#155,690
Most Influential Person Now
American scientist
Michael Orshansky's AcademicInfluence.com Rankings
Michael Orshanskyengineering Degrees
Engineering
#8475
World Rank
#10020
Historical Rank
#1510
USA Rank
Electrical Engineering
#2649
World Rank
#2786
Historical Rank
#355
USA Rank
Michael Orshanskycomputer-science Degrees
Computer Science
#10286
World Rank
#10790
Historical Rank
#1791
USA Rank
Computer Engineering
#174
World Rank
#176
Historical Rank
#19
USA Rank
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Engineering Computer Science
Michael Orshansky's Degrees
- PhD Electrical and Computer Engineering University of California, Berkeley
- Masters Electrical and Computer Engineering University of California, Berkeley
Why Is Michael Orshansky Influential?
(Suggest an Edit or Addition)According to Wikipedia, Michael Orshansky is an American researcher in integrated circuit design, currently with University of Texas at Austin since 2003. He received his undergraduate education and Ph.D. at the UC Berkeley.
Michael Orshansky's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- Approximate computing: An emerging paradigm for energy-efficient design (2013) (874)
- New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation (2000) (503)
- A general probabilistic framework for worst case timing analysis (2002) (223)
- Design for Manufacturability and Statistical Design - A Constructive Approach (2007) (213)
- BulletProof: a defect-tolerant CMP switch architecture (2006) (207)
- FASER: fast analysis of soft error susceptibility for cell-based designs (2006) (191)
- Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits (2002) (175)
- Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization [logic IC design] (2003) (170)
- An efficient algorithm for statistical minimization of total power under timing yield constraints (2005) (143)
- Fast statistical timing analysis handling arbitrary delay correlations (2004) (120)
- Modeling and synthesis of quality-energy optimal approximate adders (2012) (114)
- Characterization of spatial intrafield gate CD variability, its impact on circuit performance, and spatial mask-level correction (2004) (106)
- NBTI-aware DVFS: A new approach to saving energy and increasing processor lifetime (2010) (99)
- Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits (2000) (96)
- Analytical Modeling of SRAM Dynamic Stability (2006) (82)
- A new statistical optimization algorithm for gate sizing (2004) (77)
- Joint Design-Time and Post-Silicon Minimization of Parametric Yield Loss using Adjustable Robust Optimization (2006) (72)
- Approximate logic synthesis under general error magnitude and frequency constraints (2013) (68)
- Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring (2013) (49)
- Novel strong PUF based on nonlinearity of MOSFET subthreshold operation (2013) (49)
- Horizontal side-channel vulnerabilities of post-quantum key exchange protocols (2018) (48)
- An Accurate Sparse Matrix Based Framework for Statistical Static Timing Analysis (2006) (47)
- Design for Manufacturability and Statistical Design: A Comprehensive Approach (2006) (47)
- Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation (2008) (46)
- Strong subthreshold current array PUF with 265 challenge-response pairs resilient to machine learning attacks in 130nm CMOS (2017) (46)
- Multi-level approximate logic synthesis under general error constraints (2014) (44)
- Leakage power reduction by dual-Vth designs under probabilistic analysis of Vth variation (2004) (43)
- Enabling efficient analog synthesis by coupling sparse regression and polynomial optimization (2014) (42)
- The Search for Alternative Computational Paradigms (2008) (39)
- A sequence dependent challenge-response PUF using 28nm SRAM 6T bit cell (2017) (32)
- Controlled timing-error acceptance for low energy IDCT design (2011) (31)
- Direct sampling methodology for statistical analysis of scaled CMOS technologies (1999) (30)
- Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty (2006) (27)
- Circuit performance variability decomposition (1999) (25)
- From blind certainty to informed uncertainty (2002) (25)
- Circuit-Level Timing-Error Acceptance for Design of Energy-Efficient DCT/IDCT-Based Systems (2013) (24)
- Interval-based robust statistical techniques for non-negative convex functions, with application to timing analysis of computer chips (2006) (23)
- Efficient simulation of EM side-channel attack resilience (2017) (23)
- A Strong Subthreshold Current Array PUF Resilient to Machine Learning Attacks (2020) (23)
- Binary Ring-LWE hardware with power side-channel countermeasures (2018) (22)
- A new maskless debiasing method for lightweight physical unclonable functions (2017) (20)
- A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits (2007) (20)
- Electrically driven optical proximity correction based on linear programming (2008) (19)
- Intra-field gate CD variability and its impact on circuit performance (1999) (18)
- Predictable Equation-Based Analog Optimization Based on Explicit Capture of Modeling Error Statistics (2012) (17)
- Robust Estimation of Parametric Yield under Limited Descriptions of Uncertainty (2006) (17)
- Electrically driven optical proximity correction (2008) (17)
- Lattice PUF: A Strong Physical Unclonable Function Provably Secure against Machine Learning Attacks (2019) (16)
- Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis (2007) (16)
- Using Power-Anomalies to Counter Evasive Micro-Architectural Attacks in Embedded Systems (2019) (15)
- SMATO: Simultaneous mask and target optimization for improving lithographic process window (2010) (15)
- Symbolic Simulation of the Propagation and Filtering of Transient Faulty Pulses (2005) (14)
- Velocity overshoot of electrons and holes in Si inversion layers (1997) (13)
- Assessing SEU Vulnerability via Circuit-Level Timing Analysis (2005) (13)
- Statistical technology mapping for parametric yield (2005) (13)
- Towards formal probabilistic power-performance design space exploration (2006) (12)
- A statistical performance simulation methodology for VLSI circuits (1998) (12)
- Spice up your MOSFET modelling (2003) (12)
- Efficient generation of pre-silicon MOS model parameters for early circuit design (2001) (11)
- Probabilistic strain optimization under constraint uncertainty (2013) (10)
- Fresh re-keying with strong PUFs: A new approach to side-channel security (2018) (10)
- Methods for joint optimization of mask and design targets for improving lithographic process window (2013) (10)
- Architecting a reliable CMP switch architecture (2007) (10)
- A heterogeneous CMOS-CNT architecture utilizing novel coding of boolean functions (2007) (10)
- Increasing Circuit Performance through Statistical Design Techniques (2004) (9)
- Statistical circuit characterization for deep-submicron CMOS designs (1998) (9)
- Path-Based Statistical Timing Analysis Handling Arbitrary Delay Correlations: Theory and Implementation (2006) (9)
- Variation-Tolerant Write Completion Circuit for Variable-Energy Write STT-RAM Architecture (2016) (8)
- Securing AES against Localized EM Attacks through Spatial Randomization of Dataflow (2019) (8)
- Training with Multi-Layer Embeddings for Model Reduction (2020) (8)
- Mitigation of intra-array SRAM variability using adaptive voltage architecture (2009) (7)
- Analysis of systematic variation and impact on circuit performance (2008) (7)
- Report for the NSF Workshop on Cross ‐ layer Power Optimization and Management (2012) (7)
- Tutorial II: Variability and Its Impact on Design (2006) (7)
- International Symposium on VLSI Technology, Systems, and Applications, Proceedings (1997) (7)
- Horizontal Side-Channel Vulnerabilities of Post-Quantum Key Exchange and Encapsulation Protocols (2021) (6)
- A methodology for propagating design tolerances to shape tolerances for use in manufacturing (2010) (6)
- Statistical analysis of circuit timing using majorization (2009) (5)
- Gain-based technology mapping for minimum runtime leakage under input vector uncertainty (2006) (5)
- Estimation of Leakage Power Consumption and Parametric Yield Based on Realistic Probabilistic Descriptions of Parameters (2007) (5)
- Simultaneous OPC and decomposition for double exposure lithography (2011) (5)
- Characterization of spatial CD variability, spatial mask-level correction, and improvement of circuit performance (2000) (5)
- Embracing local variability to enable a robust high-gain positive-feedback amplifier: Design methodology and implementation (2012) (5)
- Low-energy signal processing using circuit-level timing-error acceptance (2012) (5)
- An algorithm for exploiting modeling error statistics to enable robust analog optimization (2010) (4)
- Analysis of Leakage Power Reduction in Dual-Vth Technologies in the Presence of Large Threshold Voltage Variation (2006) (4)
- Impact of velocity overshoot, polysilicon depletion, and inversion layer quantization on NMOSFET scaling (1998) (4)
- Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel Attacks (2021) (4)
- Estimating path delay distribution considering coupling noise (2007) (4)
- PolyGP: Improving GP-based analog optimization through accurate high-order monomials and semidefinite relaxation (2016) (4)
- Compensating non-optical effects using electrically driven optical proximity correction (2009) (4)
- Application of fast SOCP based statistical sizing in the microprocessor design flow (2006) (4)
- A Monte Carlo simulation flow for SEU analysis of sequential circuits (2016) (3)
- Ground rule slack aware tolerance-driven optical proximity correction for local metal interconnects (2010) (3)
- Modeling and Optimization Techniques for Yield-Aware SRAM Post-Silicon Tuning (2014) (3)
- Abnormal ESD failure mode with low-voltage turn-on phenomenon of LDMOS output driver (2012) (3)
- Novel power grid reduction method based on L1 regularization (2015) (2)
- Coupling timing objectives with optical proximity correction for improved timing yield (2011) (2)
- Power Minimization with Multiple Supply Voltages and Multiple Threshold Voltages (2003) (2)
- Efficient helper data reduction in SRAM PUFs via lossy compression (2018) (2)
- Highly Secure Strong PUF based on Nonlinearity of MOSFET Subthreshold Operation (2012) (2)
- Statistical Minimization of Total Power under Timing Yield Constraints (2006) (1)
- Galvanically Isolated, Power and Electromagnetic Side-Channel Attack Resilient Secure AES Core with Integrated Charge Pump based Power Management (2021) (1)
- Statistical models, methods, and algorithms for computer-aided design for manufacturing (2001) (1)
- Static Timing Analysis Based on Partial Probabilistic Description of Delay Uncertainty (2006) (1)
- Winning the power struggle in an uncertain era (2007) (1)
- Shape slack: a design-manufacturing co-optimization methodology using tolerance information (2013) (1)
- A Provably Secure Strong PUF Based on LWE: Construction and Implementation (2023) (1)
- Generation of Efficient Codes for Realizing Boolean Functions in Nanotechnologies (2007) (1)
- Design of power-optimal buffers tunable to process variability (2010) (0)
- Power-based Malware Detection in Linux Boot (2022) (0)
- Exploiting randomness in sketching for efficient hardware implementation of machine learning applications (2016) (0)
- Session details: Yield estimation and optimization (2004) (0)
- Implementation of Delay Efficient ALU using Vedic Multiplier with AHL (2016) (0)
- Statistical algorithms for circuit synthesis under process variation and high defect density (2007) (0)
- Validating Extreme Scale Resilience with Veracity (Final Project Report) (2020) (0)
- Multiple attempt write strategy for low energy STT-RAM (2016) (0)
- High-Level Simulation of Embedded Software Vulnerabilities to EM Side-Channel Attacks (2022) (0)
- Robust algorithms for area and power optimization of digital integrated circuits under variability (2008) (0)
- Variability and Its Impact on Design (2006) (0)
- Variability-Aware Training and Self-Tuning of Highly Quantized DNNs for Analog PIM (2021) (0)
- Models and algorithms for statistical timing and power analysis of digital integrated circuits (2007) (0)
- Session details: Special session: DFM and variability: theory and practice (2005) (0)
- Logic synthesis for reducing leakage power consumption under workload uncertainty (2008) (0)
- Session details: Design methods for manufacturability enhancements (2005) (0)
- Power-based Attacks on Spatial DNN Accelerators (2021) (0)
- FPGA Synthesis and CAD for Reconfigurable Systems (2009) (0)
- ENHANCING PHYSICAL DEVICE IDENTITY TECHNOLOGY THROUGH PHYSICAL UNCLONABLE FUNCTIONS (2016) (0)
- Gene modification identification under flux capacity uncertainty (2013) (0)
- Session details: Statistical techniques for timing analysis and design (2007) (0)
- Session details: Low power design and validation methodologies (2012) (0)
- Session details: Coping with variability: the end of deterministic design (2003) (0)
- Low-energy digital filter design based on controlled timing error acceptance (2013) (0)
- AnAccurate SparseMatrix BasedFramework for Statistical Static TimingAnalysis (2006) (0)
- Chapter 12 12 WINNING THE POWER STRUGGLE (0)
- Session details: Timing analysis and circuit optimization for novel technologies and DFM (2010) (0)
- Process Variation Aware Low Power Buffer Design APPROVED BY SUPERVISING COMMITTEE: (2010) (0)
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