Ming‐dou Ker

Ming‐dou Ker's AcademicInfluence.com Rankings

Ming‐dou Ker

Engineering

#5906

World Rank

#7193

Historical Rank

Electrical Engineering

#1699

World Rank

#1797

Historical Rank

engineering Degrees

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Engineering

Ming‐dou Ker's Degrees

PhD Electrical Engineering University of California, Berkeley
Masters Electrical Engineering University of California, Berkeley
Bachelors Electrical Engineering National Taiwan University

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Ming‐dou Ker's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI (1999) (296)
Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes (2006) (213)
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control (2013) (189)
Investigation of the gate-driven effect and substrate-triggered effect on ESD robustness of CMOS devices (2001) (91)
New Curvature-Compensation Technique for CMOS Bandgap Reference With Sub-1-V Operation (2005) (82)
A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS ICs (1997) (75)
A new Schmitt trigger circuit in a 0.13-μm 1/2.5-V CMOS process to receive 3.3-V input signals (2005) (71)
Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI (1996) (63)
Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC (1996) (63)
ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications (2000) (63)
Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test (2008) (60)
A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control (2018) (60)
Overview on ESD Protection Designs of Low-Parasitic Capacitance for RF ICs in CMOS Technologies (2011) (57)
Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technology (2003) (57)
Overview and Design of Mixed-Voltage I/O Buffers With Low-Voltage Thin-Oxide CMOS Transistors (2006) (56)
A fully integrated 8-channel closed-loop neural-prosthetic SoC for real-time epileptic seizure control (2013) (54)
New curvature-compensation technique for CMOS bandgap reference with sub-1-V operation (2006) (53)
Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-/spl mu/m silicide CMOS process (2000) (51)
Level shifters for high-speed 1 V to 3.3 V interfaces in a 0.13 /spl mu/m Cu-interconnection/low-k CMOS technology (2001) (51)
Component-Level Measurement for Transient-Induced Latch-up in CMOS ICs Under System-Level ESD Considerations (2006) (49)
Latchup-free ESD protection design with complementary substrate-triggered SCR devices (2003) (48)
ESD test methods on integrated circuits: an overview (2001) (46)
Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method. I. theoretical derivation (1995) (45)
Hardware/firmware co-design in an 8-bits microcontroller to solve the system-level ESD issue on keyboard (1999) (45)
Transient-Induced Latchup in CMOS Integrated Circuits (2009) (45)
Low-Capacitance SCR With Waffle Layout Structure for On-Chip ESD Protection in RF ICs (2007) (44)
ESD protection design with lateral DMOS transistor in 40-V BCD technology (2010) (44)
Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-/spl mu/m CMOS process (2003) (43)
Analysis on the dependence of layout parameters on ESD robustness of CMOS devices for manufacturing in deep-submicron CMOS process (2003) (42)
The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs (2005) (40)
Diode-Triggered Silicon-Controlled Rectifier With Reduced Voltage Overshoot for CDM ESD Protection (2012) (40)
Improving Safe Operating Area of nLDMOS Array With Embedded Silicon Controlled Rectifier for ESD Protection in a 24-V BCD Process (2011) (39)
Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology (2009) (38)
Power-Rail ESD Clamp Circuit With Diode-String ESD Detection to Overcome the Gate Leakage Current in a 40-nm CMOS Process (2013) (37)
Physical mechanism and device simulation on transient-induced latchup in CMOS ICs under system-level ESD test (2005) (37)
Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection (2010) (37)
Ultra-High-Voltage Charge Pump Circuit in Low-Voltage Bulk CMOS Processes With Polysilicon Diodes (2007) (37)
ESD protection design for CMOS RF integrated circuits (2002) (37)
Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-/spl mu/m CMOS technology (2004) (36)
Implantable Stimulator for Epileptic Seizure Suppression With Loading Impedance Adaptability (2013) (36)
Design of Mixed-Voltage I/O Buffer by Using NMOS-Blocking Technique (2006) (36)
On-Chip Transient Detection Circuit for System-Level ESD Protection in CMOS Integrated Circuits to Meet Electromagnetic Compatibility Regulation (2008) (35)
A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process (2016) (34)
Self-substrate-triggered technique to enhance turn-on uniformity of multi-finger ESD protection devices (2006) (34)
ESD Protection Design With On-Chip ESD Bus and High-Voltage-Tolerant ESD Clamp Circuit for Mixed-Voltage I/O Buffers (2008) (33)
Design of Integrated Gate Driver With Threshold Voltage Drop Cancellation in Amorphous Silicon Technology for TFT-LCD Application (2011) (33)
A Latchup-Immune and Robust SCR Device for ESD Protection in 0.25-μm 5-V CMOS Process (2013) (33)
Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit (2014) (32)
SCR device with dynamic holding voltage for on-chip ESD protection in a 0.25-/spl mu/m fully salicided CMOS process (2004) (32)
Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers (2002) (31)
Double snapback characteristics in high-voltage nMOSFETs and the impact to on-chip ESD protection design (2004) (31)
Lateral SCR devices with low-voltage high-current triggering characteristics for output ESD protection in submicron CMOS technology (1998) (31)
Implementation of Initial-On ESD Protection Concept With PMOS-Triggered SCR Devices in Deep-Submicron CMOS Technology (2007) (30)
A CMOS bandgap reference circuit for sub-1-V operation without using extra low-threshold-voltage device (2004) (30)
SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes (2003) (29)
Optimization on Layout Style of ESD Protection Diode for Radio-Frequency Front-End and High-Speed I/O Interface Circuits (2010) (29)
Design of 2.5 V/5 V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic N-well bias circuit (2003) (29)
Novel input ESD protection circuit with substrate-triggering technique in a 0.25-/spl mu/m shallow-trench-isolation CMOS technology (1998) (29)
ESD protection to overcome internal gate oxide damage on digital-analog interface of mixed-mode CMOS IC's (1996) (29)
Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: design concept and circuit implementations (2006) (29)
ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustness (2002) (29)
New Layout Arrangement to Improve ESD Robustness of Large-Array High-Voltage nLDMOS (2010) (27)
ESD implantations for on-chip ESD protection with layout consideration in 0.18-/spl mu/m salicided CMOS technology (2005) (27)
Cascoded LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup danger (2000) (27)
Fabrication of a miniature CMOS-based optical biosensor. (2007) (27)
ESD Protection Design for 60-GHz LNA With Inductor-Triggered SCR in 65-nm CMOS Process (2012) (26)
Evaluation on board-level noise filter networks to suppress transient-induced latchup in CMOS ICs under system-level ESD test (2006) (26)
On-chip ESD protection design by using polysilicon diodes in CMOS process (2001) (26)
High-Voltage-Tolerant ESD Clamp Circuit With Low Standby Leakage in Nanoscale CMOS Process (2010) (26)
Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs (2009) (26)
Impact of MOSFET Gate-Oxide Reliability on CMOS Operational Amplifier in a 130-nm Low-Voltage Process (2008) (25)
On-panel output buffer with offset compensation technique for data driver in LTPS technology (2006) (25)
CMOS chip as luminescent sensor for biochemical reactions (2003) (24)
Optimization of broadband RF performance and ESD robustness by π-model distributed ESD protection scheme (2004) (24)
A novel LC-tank ESD protection design for Giga-Hz RF circuits (2003) (24)
Active ESD Protection Design for Interface Circuits Between Separated Power Domains Against Cross-Power-Domain ESD Stresses (2008) (24)
Evaluation of subcortical grey matter abnormalities in patients with MRI-negative cortical epilepsy determined through structural and tensor magnetic resonance imaging (2014) (24)
SCR device fabricated with dummy-gate structure to improve turn-on speed for effective ESD protection in CMOS technology (2005) (23)
Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-/spl mu/m salicided CMOS process (2001) (23)
ESD implantations in 0.18-/spl mu/m salicided CMOS technology for on-chip ESD protection with layout consideration (2001) (23)
Substrate-triggered technique for on-chip ESD protection design in a 0.18-/spl mu/m salicided CMOS process (2003) (23)
A 5-GHz Differential Low-Noise Amplifier With High Pin-to-Pin ESD Robustness in a 130-nm CMOS Process (2009) (23)
Characterization of SOA in Time Domain and the Improvement Techniques for Using in High-Voltage Integrated Circuits (2012) (22)
Synthesis of uniform core–shell gelatin–alginate microparticles as intestine‐released oral delivery drug carrier (2014) (22)
An Output Buffer for 3.3-V Applications in a 0.13-$\mu\hbox{m}$ 1/2.5-V CMOS Process (2007) (22)
Source-side engineering to increase holding voltage of LDMOS in a 0.5-m 16-V BCD technology to avoid latch-up failure (2009) (22)
ESD Protection Design With Stacked High-Holding-Voltage SCR for High-Voltage Pins in a Battery-Monitoring IC (2016) (21)
Self-protected LDMOS output device with embedded SCR to improve ESD robustness in 0.25-μm 60-V BCD process (2013) (21)
Native-NMOS-Triggered SCR With Faster Turn-On Speed for Effective ESD Protection in a 0.13-$rm murm m$CMOS Process (2005) (21)
An Output Buffer for 3.3-V Applications in a 0.13- m 1/2.5-V CMOS Process (2007) (21)
Transient-to-Digital Converter for System-Level Electrostatic Discharge Protection in CMOS ICs (2009) (20)
Investigation on the Validity of Holding Voltage in High-Voltage Devices Measured by Transmission-Line-Pulsing (TLP) (2008) (20)
ESD protection design in a 0.18-/spl mu/m salicide CMOS technology by using substrate-triggered technique (2001) (20)
On-Chip ESD Protection Device for High-Speed I/O Applications in CMOS Technology (2017) (20)
Whole-chip ESD protection scheme for CMOS mixed-mode IC's in deep-submicron CMOS technology (1997) (19)
A fully integrated closed-loop neuromodulation SoC with wireless power and bi-directional data telemetry for real-time human epileptic seizure control (2017) (19)
Decreasing-size distributed ESD protection scheme for broad-band RF circuits (2005) (19)
Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits (2002) (19)
ESD protection design for giga-Hz RF CMOS LNA with novel impedance-isolation technique (2003) (19)
A new charge pump circuit dealing with gate-oxide reliability issue in low-voltage processes (2004) (19)
Fully process-compatible layout design on bond pad to improve wire bond reliability in CMOS ICs (2002) (19)
Design of negative charge pump circuit with polysilicon diodes in a 0.25 /spl mu/m CMOS process (2002) (18)
Area-Efficient and Low-Leakage Diode String for On-Chip ESD Protection (2016) (18)
Dependence of Device Structures on Latchup Immunity in a High-Voltage 40-V CMOS Process With Drain-Extended MOSFETs (2007) (18)
Low-Leakage and Low-Trigger-Voltage SCR Device for ESD Protection in 28-nm High- $k$ Metal Gate CMOS Process (2016) (18)
Transient-Induced Latchup in CMOS ICs Under Electrical Fast-Transient Test (2009) (18)
A High-Voltage-Tolerant and Power-Efficient Stimulator With Adaptive Power Supply Realized in Low-Voltage CMOS Process for Implantable Biomedical Applications (2018) (18)
Regulated Charge Pump With New Clocking Scheme for Smoothing the Charging Current in Low Voltage CMOS Process (2017) (18)
Design on mixed-voltage I/O buffers with slew-rate control in low-voltage CMOS process (2008) (18)
Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection (2009) (18)
Complementary-SCR ESD protection circuit with interdigitated finger-type layout for input pads of submicron CMOS IC's (1995) (17)
The Effect of IEC-Like Fast Transients on $RC$ -Triggered ESD Power Clamps (2009) (17)
Design of negative high voltage generator for biphasic stimulator with soc integration consideration (2012) (17)
Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration (2008) (17)
Self-Substrate-Triggered Technique to Enhance Turn-On Uniformity of Multi-Finger ESD Protection Devices (2005) (17)
Design on latchup-free power-rail ESD clamp circuit in high-voltage CMOS ICs (2004) (17)
Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product (2002) (17)
On the design of power-rail esd clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process (2009) (17)
Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process (2010) (17)
Area-efficient layout design for CMOS output transistors (1997) (17)
Whole-chip ESD protection design for submicron CMOS VLSI (1997) (17)
ESD-Protection Design With Extra Low-Leakage-Current Diode String for RF Circuits in SiGe BiCMOS Process (2006) (16)
ESD protection for CMOS output buffer by using modified LVTSCR devices with high trigger current (1997) (16)
Complementary-LVTSCR ESD protection scheme for submicron CMOS IC's (1995) (16)
A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI (1991) (16)
New Design of 2 $\times$ VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology (2012) (16)
Design to avoid the over-gate-driven effect on ESD protection circuits in deep-submicron CMOS processes (2004) (16)
High Area-Efficient ESD Clamp Circuit With Equivalent $RC$-Based Detection Mechanism in a 65-nm CMOS Process (2013) (16)
Area-efficient CMOS output buffer with enhanced high ESD reliability for deep submicron CMOS ASIC (1995) (15)
Improving ESD robustness of stacked diodes with embedded SCR for RF applications in 65-nm CMOS (2014) (15)
A Digitally Dynamic Power Supply Technique for 16-Channel 12 V-Tolerant Stimulator Realized in a 0.18- μm 1.8-V/3.3-V Low-Voltage CMOS Process (2017) (15)
ESD failure mechanisms of analog I/O cells in 0.18-/spl mu/m CMOS technology (2006) (15)
ESD protection design for 1- to 10-GHz distributed amplifier in CMOS technology (2005) (15)
Interference of ESD protection diodes on RF performance in Giga-Hz RF circuits (2003) (15)
New Transient Detection Circuit for On-Chip Protection Design Against System-Level Electrical-Transient Disturbance (2010) (15)
Self-matched ESD cell in CMOS technology for 60-GHz broadband RF applications (2010) (15)
ESD Protection for Mixed-Voltage I/O in LowVoltage Thin-Oxide CMOS (2006) (15)
Design of High-Voltage-Tolerant ESD Protection Circuit in Low-Voltage CMOS Processes (2009) (15)
New matching methodology of low-noise amplifier with ESD protection (2006) (14)
Latchup in bulk FinFET technology (2017) (14)
Gate-Bias Circuit to Achieve 3·VDD Input Tolerance by Using 1·VDD Devices and Single VDD Supply (2005) (14)
Electrostatic discharge protection circuits in CMOS ICs using the lateral SCR devices: an overview (1998) (14)
Novel diode structures and ESD protection circuits in a 1.8-V 0.15-/spl mu/m partially-depleted SOI salicided CMOS process (2001) (14)
Substrate-triggered ESD protection circuit without extra process modification (2003) (14)
Design on ESD protection scheme for IC with power-down-mode operation (2004) (14)
Failure analysis of ESD damage in a high-voltage driver IC and the effective ESD protection solution [CMOS] (2002) (14)
Design of 2$\times$VDD-Tolerant Power-Rail ESD Clamp Circuit With Consideration of Gate Leakage Current in 65-nm CMOS Technology (2010) (14)
The Impact of Inner Pickup on ESD Robustness of Multi-Finger NMOS in Nanoscale CMOS Technology (2006) (14)
Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection (2009) (14)
Stimulus driver for epilepsy seizure suppression with adaptive loading impedance (2011) (14)
New Low-Leakage Power-Rail ESD Clamp Circuit in a 65-nm Low-Voltage CMOS Process (2011) (13)
New Ballasting Layout Schemes to Improve ESD Robustness of I/O Buffers in Fully Silicided CMOS Process (2009) (13)
Transient-induced latchup in CMOS technology: physical mechanism and device simulation (2004) (13)
Design of charge pump circuit in low-voltage CMOS process with suppressed return-back leakage current (2010) (13)
Design optimization of ESD protection and latchup prevention for a serial I/O IC (2004) (13)
Comparison Between High-Holding-Voltage SCR and Stacked Low-Voltage Devices for ESD Protection in High-Voltage Applications (2018) (13)
ESD Protection Design for Touch Panel Control IC Against Latchup-Like Failure Induced by System-Level ESD Test (2017) (13)
On-Chip High-Voltage Charge Pump Circuit in Standard CMOS Processes With Polysilicon Diodes (2005) (13)
On the Design of Power-Rail ESD Clamp Circuits With Gate Leakage Consideration in Nanoscale CMOS Technology (2014) (13)
Design of 2 × VDD-Tolerant Power-Rail ESD Clamp Circuit With Consideration of Gate Leakage Current in 65-nm CMOS Technology (2010) (13)
Design of cost-efficient ESD clamp circuits for the power rails of CMOS ASIC's with substrate-triggering technique (1997) (13)
An Efficient, Wide-Output, High-Voltage Charge Pump With a Stage Selection Circuit Realized in a Low-Voltage CMOS Process (2019) (13)
Design on the low-capacitance bond pad for high-frequency I/O circuits in CMOS technology (2001) (13)
Whole-chip ESD protection for CMOS VLSI/ULSI with multiple power pins (1994) (13)
Optimization on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-μm CMOS technology (2008) (13)
ESD protection design to overcome internal damage on interface circuits of a CMOS IC with multiple separated power pins (2004) (13)
Design of Multiple-Charge-Pump System for Implantable Biomedical Applications (2018) (12)
Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-/spl mu/m CMOS integrated circuits (2004) (12)
Design on Mixed-Voltage I/O Buffers with Consideration of Hot-Carrier Reliability (2007) (12)
PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit (2011) (12)
ESD implantation for subquarter-micron CMOS technology to enhance ESD robustness (2003) (12)
New Gate-Bias Voltage-Generating Technique With Threshold-Voltage Compensation for On-Glass Analog Circuits in LTPS Process (2007) (12)
Design of $2 \times {\rm V}_{\rm DD}$-Tolerant I/O Buffer With PVT Compensation Realized by Only $1 \times {\rm V}_{\rm DD}$ Thin-Oxide Devices (2013) (12)
Investigation on Board-Level CDM ESD Issue in IC Products (2008) (12)
Substrate-triggered ESD clamp devices for use in power-rail ESD clamp circuits (2002) (12)
A new output buffer for 3.3-V PCI-X application in a 0.13-/spl mu/m 1/2.5-V CMOS process (2004) (12)
Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process (2011) (12)
Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method. II. Quantitative evaluation (1995) (12)
The Impact of Drift Implant and Layout Parameters on ESD Robustness for On-Chip ESD Protection Devices in 40-V CMOS Technology (2007) (12)
Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process (2009) (12)
High-robust ESD protection structure with embedded SCR in high-voltage CMOS process (2008) (11)
Design of low-capacitance bond pad for high-frequency I/O applications in CMOS integrated circuits (2000) (11)
ESD protection for output pad with well-coupled field-oxide device in 0.5-/spl mu/m CMOS technology (1997) (11)
Evaluation on efficient measurement setup for transient-induced latchup with bi-polar trigger [CMOS IC reliability] (2005) (11)
Active Guard Ring to Improve Latch-Up Immunity (2014) (11)
Mixed-voltage I/O buffer with dynamic gate-bias circuit to achieve 3/spl times/V/sub DD/ input tolerance by using 1/spl times/V/sub DD/ devices and single V/sub DD/ supply (2005) (11)
Monopolar Biphasic Stimulator With Discharge Function and Negative Level Shifter for Neuromodulation SoC Integration in Low-Voltage CMOS Process (2021) (11)
Design of low-leakage power-rail ESD clamp circuit with MOM capacitor and STSCR in a 65-nm CMOS process (2011) (11)
ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology (2005) (11)
Design of 2xVDD-tolerant I/O buffer with 1xVDD CMOS devices (2009) (11)
New 4-Bit Transient-to-Digital Converter for System-Level ESD Protection in Display Panels (2012) (11)
Correlation between transmission-line-pulsing I-V curve and human-body-model ESD level on low temperature poly-Si TFT devices (2004) (11)
Design of 2×VDD-Tolerant I/O Buffer with Considerations of Gate-Oxide Reliability and Hot-Carrier Degradation (2007) (11)
Design and In Vivo Verification of a CMOS Bone-Guided Cochlear Implant Microsystem (2019) (11)
Failure of On-Chip Power-Rail ESD Clamp Circuits During System-Level ESD Test (2007) (11)
Design of Analog Pixel Memory for Low Power Application in TFT-LCDs (2011) (11)
Impact of layout pickups to ESD robustness of MOS transistors in sub 100-nm CMOS process (2010) (10)
A bone-guided cochlear implant CMOS microsystem preserving acoustic hearing (2017) (10)
New experimental methodology to extract compact layout rules for latchup prevention in bulk CMOS IC's (1999) (10)
Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process (2006) (10)
On-Chip ESD Protection Strategies for RF Circuits in CMOS Technology (2006) (10)
System-Level ESD Protection for Automotive Electronics by Co-Design of TVS and CAN Transceiver Chips (2017) (10)
ESD buses for whole-chip ESD protection (1999) (10)
ESD protection for CMOS ASIC in noisy environments with high-current low-voltage triggering SCR devices (1997) (10)
High-voltage-tolerant stimulator with adaptive loading consideration for electronic epilepsy prosthetic SoC in a 0.18-µm CMOS process (2012) (10)
Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process (2009) (10)
Evaluation on board-level noise filter networks to suppress transient-induced latchup under system-level ESD test (2005) (10)
On-Chip ESD detection circuit for system-level ESD protection design (2010) (10)
ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS process (2002) (10)
Resistor-Less Design of Power-Rail ESD Clamp Circuit in Nanoscale CMOS Technology (2012) (9)
Study on ESD protection design with stacked low-voltage devices for high-voltage applications (2014) (9)
Design of Mixed-Voltage-Tolerant Crystal Oscillator Circuit in Low-Voltage CMOS Technology (2009) (9)
Design of Power-Rail ESD Clamp With Dynamic Timing-Voltage Detection Against False Trigger During Fast Power-ON Events (2018) (9)
Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology (2015) (9)
P‐40: Design of Analog Pixel Memory Circuit with Low Temperature Polycrystalline Silicon TFTs for Low Power Application (2010) (9)
Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits (2007) (9)
ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins (2002) (9)
Investigation on Robustness of CMOS Devices Against Cable Discharge Event (CDE) Under Different Layout Parameters in a Deep-Submicrometer CMOS Technology (2008) (9)
On-Chip HBM and HMM ESD Protection Design for RF Applications in 40-nm CMOS Process (2018) (9)
ESD protection design on analog pin with very low input capacitance for RF or current-mode applications (1999) (9)
Area-Efficient ESD Clamp Circuit With a Capacitance-Boosting Technique to Minimize Standby Leakage Current (2015) (9)
Layout design and verification for cell library to improve ESD/latchup reliability in deep-submicron CMOS technology (1998) (9)
Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS Process (2005) (9)
ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit (2005) (9)
ESD protection consideration in nanoscale CMOS technology (2011) (9)
Low-Capacitance and Fast Turn-on SCR for RF ESD Protection (2008) (9)
ESD Protection Design With Low-Capacitance Consideration for High-Speed/High-Frequency I/O Interfaces in Integrated Circuits (2007) (9)
High-Voltage nLDMOS in Waffle-Layout Style With Body-Injected Technique for ESD Protection (2009) (9)
On-Chip Transient Voltage Suppressor Integrated With Silicon-Based Transceiver IC for System-Level ESD Protection (2014) (9)
An ESD-protected 5-GHz differential low-noise amplifier in a 130-nm CMOS process (2008) (9)
Impact of Gate Leakage on Performances of Phase-Locked Loop Circuit in Nanoscale CMOS Technology (2009) (9)
CDM ESD protection design with initial-on concept in nanoscale CMOS process (2010) (8)
Design and implementation of capacitive sensor readout circuit on glass substrate for touch panel applications (2011) (8)
Optimization Design on Active Guard Ring to Improve Latch-Up Immunity of CMOS Integrated Circuits (2019) (8)
51.3: Successful Electrostatic Discharge Protection Design for LTPS Circuits Integrated on Panel (2003) (8)
On-chip ESD protection design by using polysilicon diodes in CMOS technology for smart card application (2000) (8)
Layout Consideration and Circuit Solution to Prevent EOS Failure Induced by Latchup Test in a High-Voltage Integrated Circuits (2014) (8)
On-chip ESD protection design for GHz RF integrated circuits by using polysilicon diodes in sub-quarter-micron CMOS process (2001) (8)
Investigation of Unexpected Latchup Path Between HV-LDMOS and LV-CMOS in a 0.25- $\mu \text{m}$ 60-V/5-V BCD Technology (2017) (8)
ESD protection for deep-submicron CMOS technology using gate-couple CMOS-trigger lateral SCR structure (1995) (8)
Modified LC-tank ESD protection design for 60-GHz RF applications (2011) (8)
Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology (2007) (8)
Investigation on device characteristics of MOSFET transistor placed under bond pad for high-pin-count SOC applications (2004) (8)
ESD Protection Design by Using Only 1×VDD Low-Voltage Devices for Mixed-Voltage I/O Buffers with 3×VDD Input Tolerance (2006) (8)
Design of Dual-Mode Stimulus Chip With Built-In High Voltage Generator for Biomedical Applications (2020) (8)
Board-Level ESD of Driver ICs on LCD Panel (2009) (8)
Design on the turn-on efficient power-rail ESD clamp circuit with stacked polysilicon diodes (2001) (8)
ESD protection design for mixed-voltage I/O buffer by using stacked-NMOS triggered SCR device (2001) (8)
P‐17: On‐Panel Design Technique of Threshold Voltage Compensation for Output Buffer in LTPS Technology (2005) (8)
Robust ESD Protection Design for 40-Gb/s Transceiver in 65-nm CMOS Process (2013) (7)
ESD protection strategy for sub-quarter-micron CMOS technology: gate-driven design versus substrate-triggered design (2001) (7)
The Impact of Gate-Oxide Breakdown on Common-Source Amplifiers With Diode-Connected Active Load in Low-Voltage CMOS Processes (2007) (7)
CMOS Power Amplifier with ESD Protection Design Merged in Matching Network (2007) (7)
Overview of on-Chip Stimulator Designs for Biomedical Applications (2012) (7)
An 82.9%-Efficiency Triple-Output Battery Management Unit for Implantable Neuron Stimulator in 180-nm Standard CMOS (2019) (7)
Power-Rail ESD Clamp Circuit With Ultralow Standby Leakage Current and High Area Efficiency in Nanometer CMOS Technology (2012) (7)
Design on ESD protection circuit with very low and constant input capacitance (2001) (7)
New transient detection circuit for electrical fast transient (EFT) protection design in display panels (2010) (7)
Improved output ESD protection by dynamic gate floating design (1998) (7)
Dependences of damping frequency and damping factor of bi-polar trigger waveforms on transient-induced latchup (2005) (7)
Design of high-voltage-tolerant stimulus driver with adaptive loading consideration to suppress epileptic seizure in a 0.18-μm CMOS process (2014) (7)
ESD protection structure with inductor-triggered SCR for RF applications in 65-nm CMOS process (2012) (7)
Layout styles to improve CDM ESD robustness of integrated circuits in 65-nm CMOS process (2011) (7)
Layout optimization on low-voltage-triggered PNP devices for ESD protection in mixed-voltage I/O interfaces (2004) (7)
ESD robustness of thin-film devices with different layout structures in LTPS technology (2006) (6)
Design of Multi-Channel Monopolar Biphasic Stimulator for Implantable Biomedical Applications (2018) (6)
Study and Verification on the Latch-Up Path Between I/O pMOS and N-Type Decoupling Capacitors in 0.18- $\mu$ m CMOS Technology (2019) (6)
Design and Implementation of Readout Circuit on Glass Substrate for Touch Panel Applications (2010) (6)
Analysis of abnormal ESD failure mechanism in high-pin-count BGA packaged ICs due to stressing non-connected balls (2003) (6)
Design of bandgap voltage reference circuit with all TFT devices on glass substrate in a 3-μm LTPS process (2008) (6)
Design of a Bone-Guided Cochlear Implant Microsystem With Monopolar Biphasic Multiple Stimulations and Evoked Compound Action Potential Acquisition and Its In Vivo Verification (2021) (6)
Low-voltage-triggered PNP devices for ESD protection design in mixed-voltage I/O interface with over-VDD and under-VSS signal levels (2004) (6)
Design of High-Voltage-Tolerant Power-Rail ESD Clamp Circuit in Low-Voltage CMOS Processes (2007) (6)
ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup (2010) (6)
Method to evaluate cable discharge event (CDE) reliability of integrated circuits in CMOS technology (2006) (6)
Design and Analysis of On-Chip ESD Protection Circuit with Very Low Input Capacitance for High-Precision Analog Applications (2002) (6)
Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's (2001) (6)
Design on LVDS receiver with new delay-selecting technique for UXGA flat panel display applications (2006) (6)
Abnormal ESD failure mechanism in high-pin-count BGA packaged ICs due to stressing nonconnected balls (2004) (6)
Optimization of Guard Ring Structures to Improve Latchup Immunity in an 18 V DDDMOS Process (2016) (6)
A microvalve cell printing technique using riboflavin photosensitizer for selective cell patterning onto a retinal chip (2020) (6)
Design of Stage-Selective Negative Voltage Generator to Improve On-Chip Power Conversion Efficiency for Neuron Stimulation (2020) (6)
On-Chip ESD Protection Design for Automotive Vacuum-Fluorescent-Display (VFD) Driver IC to Sustain High ESD Stress (2007) (6)
RF/High-Speed I/O ESD Protection: Co-optimizing Strategy Between BEOL Capacitance and HBM Immunity in Advanced CMOS Process (2020) (6)
On-Chip Transient Detection Circuit for System-Level ESD Protection in CMOS ICs (2006) (6)
Whole-chip ESD protection strategy for CMOS integrated circuits in nanotechnology (2001) (6)
ESD protection design for broadband RF circuits with decreasing-size distributed protection scheme (2004) (6)
Investigation on safe operating area and ESD robustness in a 60-V BCD process with different deep P-Well test structures (2013) (6)
Energy Transformation Between the Inductor and the Power Transistor for the Unclamped Inductive Switching (UIS) Test (2020) (5)
Methodology on Extracting Compact Layout Rules for Latchup Prevention (2009) (5)
Bond Pad Design With Low Capacitance in CMOS Technology for RF Applications (2007) (5)
Digital time‐modulation pixel memory circuit in LTPS technology (2011) (5)
On-chip ESD protection using capacitor-couple technique in 0.5-/spl mu/m 3-V CMOS technology (1995) (5)
Active device under bond pad to save I/O layout for high-pin-count SOC (2003) (5)
Investigating electron depletion effect in amorphous indium–gallium–zinc-oxide thin-film transistor with a floating capping metal by technology computer-aided design simulation and leakage reduction (2014) (5)
Investigation on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-µm CMOS technology (2010) (5)
Local CDM ESD Protection Circuits for Cross-Power Domains in 3D IC Applications (2014) (5)
P‐178: Design of On‐Panel Readout Circuit for Touch Panel Application (2010) (5)
On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process (2002) (5)
Using Schottky Barrier Diode to Improve Latch-Up Immunity for CMOS ICs Operating With Negative Voltage Sources (2021) (5)
Design of Mixed-Voltage Crystal Oscillator Circuit in Low-Voltage CMOS Technology (2007) (5)
Impact of MOSFET gate-oxide reliability on CMOS operational amplifiers in a 130-nm low-voltage CMOS process (2005) (5)
Dynamic Holding Voltage SCR (DHVSCR) Device for ESD Protection with high Latch-up Immunity (2003) (5)
Compact layout rule extraction for latchup prevention in a 0.25-/spl mu/m shallow-trench-isolation silicided bulk CMOS process (2001) (5)
Circuit Performance Degradation of Sample-and-Hold Amplifier Due to Gate-Oxide Overstress in a 130-nm CMOS Process (2006) (5)
ESD protection design with stacked low-voltage devices for high-voltage pins of battery-monitoring IC (2015) (5)
Abnormal ESD Damages Occur in Interface Circuits between Different Power Domains in ND-Mode MM ESD Stress (2006) (5)
Circuit Performance Degradation of Switched-Capacitor Circuit with Bootstrapped Technique due to Gate-Oxide Overstress in a 130-nm CMOS Process (2008) (5)
Investigation of Human-Body-Model and Machine-Model ESD Robustness on Stacked Low-Voltage Field-Oxide Devices for High-Voltage Applications (2016) (5)
Transient detection circuit for system-level ESD protection and its on-board behavior with EMI/EMC filters (2008) (5)
Transient-Induced Latchup Dependence on Power-Pin Damping Frequency and Damping Factor in CMOS Integrated Circuits (2007) (5)
A CMOS-Process-Compatible Low-Voltage Junction-FET With Adjustable Pinch-Off Voltage (2017) (5)
ESD (Electrostatic Discharge) Protection Design for Nanoelectronics in CMOS Technology (2006) (5)
Design considerations and clinical applications of closed-loop neural disorder control SoCs (2017) (5)
Design of Compact ESD Protection Circuit for V-Band RF Applications in a 65-nm CMOS Technology (2012) (5)
Design to suppress return-back leakage current of charge pump circuit in low-voltage CMOS process (2011) (5)
P‐51: Design and Realization of Delta‐Sigma Analog‐To‐Digital Converter in LTPS Technology (2009) (5)
Stacked low-voltage PMOS for high-voltage ESD protection with latchup-free immunity (2015) (5)
ESD protection design for low trigger voltage and high latch-up immunity (2010) (5)
CMOS on-chip electrostatic discharge protection circuit using four-SCR structures with low ESD-trigger voltage (1994) (4)
ESD protection design for high-speed I/O interface of stub series terminated logic (SSTL) in a 0.25-/spl mu/m salicided CMOS process (2004) (4)
Mechanism of snapback failure induced by the latch-up test in high-voltage CMOS integrated circuits (2008) (4)
ASIC with Interpolator for Incremental Optical Encoders (2003) (4)
Active ESD protection for input transistors in a 40-nm CMOS process (2015) (4)
Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications (2012) (4)
Layout optimization on ESD diodes for giga-Hz RF and high-speed I/O circuits (2010) (4)
Test Structure on SCR Device in Waffle Layout for RF ESD Protection (2007) (4)
Investigation on CDM ESD events at core circuits in a 65-nm CMOS process (2012) (4)
Stacked-NMOS triggered silicon-controlled rectifier for ESD protection in high/low-voltage-tolerant I/O interface (2002) (4)
Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technology (2013) (4)
Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applications (2000) (4)
On-glass digital-to-analog converter with gamma correction for panel data driver (2008) (4)
Design of Dual-Band ESD Protection for 24-/60-GHz Millimeter-Wave Circuits (2013) (4)
ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process (2007) (4)
P‐61: Temperature Coefficient of Diode‐Connected LTPS Poly‐Si TFTs and its Application on the Bandgap Reference Circuit (2008) (4)
Latchup test-induced failure within ESD protection diodes in a high-voltage CMOS IC product (2004) (4)
Power-rail ESD clamp circuit with embedded-trigger SCR device in a 65-nm CMOS process (2014) (4)
New design of transient-noise detection circuit with SCR device for system-level ESD protection (2012) (4)
New layout scheme to improve ESD robustness of I/O buffers in fully-silicided CMOS process (2009) (4)
Transient-Induced Latchup in CMOS Integrated Circuits due to Electrical Fast Transient (EFT) Test (2007) (4)
New transient detection circuit for system-level ESD protection (2008) (4)
Methodology to Evaluate the Robustness of Integrated Circuits under Cable Discharge Event (2005) (4)
ESD protection design for mixed-voltage-tolerant I/O buffers with substrate-triggered technique (2003) (4)
Initial-On ESD Protection Design with PMOS-Triggered SCR Device (2005) (4)
Dependence of Layout Parameters on CDE (Cable Discharge Event) Robustness of CMOS Devices in a 0.25-μm Salicided CMOS Process (2006) (4)
Bi-Directional SCR Device with Dual-Triggered Mechanism for ESD Protection in Extended-Voltage-Swing I/O Application (2009) (4)
Dual SCR with low-and-constant parasitic capacitance for ESD protection in 5-GHz RF integrated circuits (2010) (4)
Stacking-MOS Protection Design for Interface Circuits Against Cross-Domain CDM ESD Stresses (2021) (4)
ESD protection design with the low-leakage-current diode string for RF circuits in BiCMOS SiGe process (2005) (4)
ESD protection design for IC with power-down-mode operation (2004) (4)
Investigation on Latch-Up Path Between I/O PMOS and Core PMOS in a 0.18-μm CMOS Process (2019) (4)
Dynamic-floating-gate design for output ESD protection in a 0.35-/spl mu/m CMOS cell library (1998) (4)
Board Level ESD of Driver ICS on LCD Panels (2007) (4)
Temperature Coefficient of Poly-Silicon TFT and its Application on Voltage Reference Circuit With Temperature Compensation in LTPS Process (2008) (4)
Design of differential low-noise amplifier with cross-coupled-SCR ESD protection scheme (2010) (4)
ESD protection design for fully integrated CMOS RF power amplifiers with waffle-structured SCR (2008) (4)
Design of Fin-Diode-Triggered Rotated Silicon-Controlled Rectifier for High- Speed Digital Application in 16-nm FinFET Process (2020) (4)
Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits (2009) (3)
Ultra Low-Capacitance Bond Pad for RF Applications in CMOS Technology (2007) (3)
Transient analysis of submicron CMOS latchup with a physical criterion (1994) (3)
ESD Protection Design With Diode-Triggered Quad-SCR for Separated Power Domains (2019) (3)
Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS technology (2006) (3)
ESD protection design and verification in a 0.35-/spl mu/m CMOS ASIC library (1999) (3)
A 70nW, 0.3V temperature compensation voltage reference consisting of subthreshold MOSFETs in 65nm CMOS technology (2016) (3)
ESD self-protection design on 2.4-GHz T/R switch for RF application in CMOS process (2016) (3)
Quad-SCR Device for Cross-Domain ESD Protection (2016) (3)
Latch-Up Protection Design With Corresponding Complementary Current to Suppress the Effect of External Current Triggers (2015) (3)
Improving Safe-Operating-Area of a 5-V n-Channel Large Array MOSFET in a 0.15- $\mu$ m BCD Process (2018) (3)
Improvement on Turn-on Speed of Substrate-Triggered SCR Device by Using Dummy-Gate Structure for On-Chip ESD Protection (2003) (3)
Design of ESD protection for RF CMOS power amplifier with inductor in matching network (2012) (3)
Complementary substrate-triggered SCR devices for on-chip ESD protection circuits (2002) (3)
Adaptable stimulus driver for epileptic seizure suppression (2011) (3)
Investigation on ESD robustness of CMOS devices in a 1.8-V 0.15-/spl mu/m partially-depleted SOI salicide CMOS technology (2001) (3)
Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits (2013) (3)
Unexpected failure in power-rail ESD clamp circuits of CMOS integrated circuits in microelectronics systems during electrical fast transient (EFT) test and the re-design solution (2007) (3)
A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant (2014) (3)
The Impact of Holding Voltage of Transient Voltage Suppressor (TVS) on Signal Integrity of Microelectronics System With CMOS ICs Under System-Level ESD and EFT/Burst Tests (2021) (3)
Investigation on seal-ring rules for IC product reliability in 0.25-mum CMOS technology (2005) (3)
Layout design to minimize voltage-dependent variation on input capacitance of an analog ESD protection circuit (2002) (3)
ESD protection design for high-speed applications in CMOS technology (2016) (3)
Novel octagonal device structure for output transistors in deep-submicron low-voltage CMOS technology (1996) (3)
On-panel analog output buffer for data driver with consideration of device characteristic variation in LTPS technology (2007) (3)
ESD protection design on T/R switch with embedded SCR in CMOS process (2017) (3)
Through Diffusion Tensor Magnetic Resonance Imaging to Evaluate the Original Properties of Neural Pathways of Patients with Partial Seizures and Secondary Generalization by Individual Anatomic Reference Atlas (2014) (3)
New design on 2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process (2012) (3)
Avalanche Ruggedness Capability and Improvement of 5-V n-Channel Large-Array MOSFET in BCD Process (2019) (3)
CDM ESD protection in CMOS integrated circuits (2008) (3)
Active Electrostatic Discharge (ESD) Device for On-Chip ESD Protection in Sub-Quarter-Micron Complementary Metal-Oxide Semiconductor (CMOS) Process (2004) (3)
ESD protection design for differential low-noise amplifier with cross-coupled SCR (2010) (3)
ESD Robustness of 40-V CMOS Devices With/Without Drift Implant (2006) (3)
Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events (2011) (3)
Low-Leakage Bidirectional SCR With Symmetrical Trigger Circuit for ESD Protection in 40-nm CMOS Process (2016) (3)
MOS-Bounded Diodes for On-Chip ESD Protection in Deep Submicron CMOS Process (2005) (3)
ESD protection circuits with novel MOS-bounded diode structures (2002) (3)
New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness (1999) (3)
Protection for Mixed-Voltage I / O in Low-Voltage Thin-Oxide CMOS (2006) (3)
Gate-Oxide Reliability on CMOS Analog Amplifiers in a 130-nm Low-Voltage CMOS Processes (2006) (3)
2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process (2010) (3)
Whole-chip ESD protection strategy for CMOS IC's with multiple mixed-voltage power pins (1999) (3)
Design on mixed-voltage I/O buffer with blocking NMOS and dynamic gate-controlled circuit for high-voltage-tolerant applications (2005) (3)
Low-Capacitance SCR With Waffle Layout Structure for On-Chip ESD Protection in RF ICs (2007) (3)
Impact of Gate Tunneling Leakage on Performances of Phase Locked Loop Circuit in Nanoscale CMOS Technology (2007) (2)
Mew diode string design with very low leakage current for using in power supply ESD clamp circuits (2000) (2)
Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology (2015) (2)
Study on Latchup Path between HV-LDMOS and LV-CMOS in a 0.16-μm 30-V/1.8-V BCD Technology (2018) (2)
Low-trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering (2017) (2)
Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology (2012) (2)
Optimized layout on ESD protection diode with low parasitic capacitance (2010) (2)
Experimental Evaluation and Device Simulation of Device Structure Influences on Latchup Immunity in High-Voltage 40-V CMOS Process (2006) (2)
Transient Voltage Suppressor (TVS) on Signal Integrity of Microelectronics System with CMOS ICs under System-Level ESD Test (2020) (2)
ESD protection design for wideband RF applications in 65-nm CMOS process (2014) (2)
Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection (2015) (2)
Design of Analog Output Buffer With Level Shifting Function on Glass Substrate for Panel Application (2009) (2)
Failure analysis on gate-driven ESD clamp circuit after TLP stresses of different voltage steps in a 16-V CMOS process (2012) (2)
A new failure mechanism on analog I/O cell under ND-mode ESD stress in deep-submicron CMOS technology (2005) (2)
Novel cascode NCLSCR/PCLSCR design with tunable holding voltage for safe whole-chip ESD protection (1998) (2)
Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process (2011) (2)
Low-Power Wordline Voltage Generator for Low-Voltage Flash Memory (2006) (2)
ESD protection design of low-voltage-triggered p-n-p devices and their failure modes in mixed-voltage I/O interfaces with signal levels higher than VDD and lower than VSS (2005) (2)
New Energy Transformation Model for the Unclamped Inductive Switching (UIS) Test (2020) (2)
NBL Causing Low Latch-up Immunity between HV-PMOS and LV-P/NMOS in a 0.15-µm BCD Process (2021) (2)
SCR device for on-chip ESD protection in RF power amplifier (2013) (2)
Layout design on bond pads to improve the firmness of bond wire in packaged IC products (1999) (2)
The Parasitic Latch-Up Path From Substrate P⁺ Guard Ring to the NMOS in Deep N-Well Operating With Negative Voltage Sources (2022) (2)
Electrostatic Discharge Protection Design for High-Voltage Programming Pin in Fully-Silicided CMOS ICs (2011) (2)
MOS-bounded diodes for on-chip ESD protection in a 0.15-/spl mu/m shallow-trench-isolation salicided CMOS process (2003) (2)
Multiple-cell square-type layout design for output transistors in submicron CMOS technology to save silicon area (1998) (2)
2xVDD-tolerant crystal oscillator circuit realized with 1xVDD CMOS devices without gate-oxide reliability issue (2008) (2)
Self-Reset Transient Detection Circuit for On-Chip Protection Against System-Level Electrical-Transient Disturbance (2018) (2)
High-Current Characterization of Polysilicon Diode for Electrostatic Discharge Protection in Sub-Quarter-Micron Complementary Metal Oxide Semiconductor Technology (2003) (2)
Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS (2009) (2)
Overview on the design of low-leakage power-rail ESD clamp circuits in nanoscale CMOS processes (2011) (2)
Design of High-Voltage-Tolerant Power-Rail ESD Protection Circuit for Power Pin of Negative Voltage in Low-Voltage CMOS Processes (2020) (2)
ESD-transient detection circuit with equivalent capacitance-coupling detection mechanism and high efficiency of layout area in a 65nm CMOS technology (2013) (2)
ESD protection design with latchup-free immunity in 120V SOI process (2015) (2)
Large-Swing-Tolerant ESD Protection Circuit for Gigahertz Power Amplifier in a 65-nm CMOS Process (2013) (2)
Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation (2010) (2)
Schottky-Embedded Silicon-Controlled Rectifier With High Holding Voltage Realized in a 0.18-μm Low-Voltage CMOS Process (2021) (2)
Dummy-gate structure to improve ESD robustness in a fully-salicided 130-nm CMOS technology without using extra salicide-blocking mask (2006) (2)
Study on the Guard Rings for Latchup Prevention between HV-PMOS and LV-PMOS in a 0.15-µm BCD Process (2021) (2)
Investigation on RF Characteristics of Stacked P-I-N Polysilicon Diodes for ESD Protection Design in 0.18-μm CMOS Technology (2006) (2)
Design and Implementation of Readout Circuit with Threshold Voltage Compensation on Glass Substrate for Touch Panel Applications (2011) (2)
Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process (2013) (2)
Protection design against system-level ESD transient disturbance on display panels (2010) (2)
Area-Efficient On-Chip Transient Detection Circuit for System-Level ESD Protection Against Transient-Induced Malfunction (2019) (2)
Ultra-low-leakage power-rail ESD clamp circuit in a 65-nm CMOS technology (2013) (2)
Design of high-voltage-tolerant level shifter in low voltage CMOS process for neuro stimulator (2016) (2)
Design of dynamic-floating-gate technique for output ESD protection in deep-submicron CMOS technology (1999) (2)
Improvement on CDM ESD robustness of high-voltage tolerant nLDMOS SCR devices by using differential doped gate (2014) (2)
Implementation of the cosine law for location awareness system (2010) (2)
Design of AC-coupled circuit for high-speed interconnects (2012) (2)
Digital‐to‐analog converter with gamma correction on glass substrate for TFT‐panel applications (2009) (2)
Implementation of delta—sigma analog‐to‐digital converter in LTPS process (2010) (2)
Electrostatic discharge implantation to improve machine-model ESD robustness of stacked NMOS in mixed I/O interface circuits (2003) (2)
ESD-aware circuit design in CMOS integrated circuits to meet system-level ESD specification in microelectronic systems (2011) (2)
A bending N-Well ballast layout to improve ESD robustness in fully-silicided CMOS technology (2010) (2)
Design of ESD protection cell for dual-band RF applications in a 65-nm CMOS process (2012) (1)
A 13.56 MHz Metamaterial for the Wireless Power Transmission Enhancement in Implantable Biomedical Devices (2019) (1)
Resistor-less power-rail ESD clamp circuit with ultra-low leakage current in 65nm CMOS process (2013) (1)
Improve latch-up immunity by circuit solution (2015) (1)
Transient-to-digital converter for ESD protection design in microelectronic systems (2008) (1)
Improved Design and In Vivo Animal Tests of Bone-Guided Cochlear Implant Microsystem with Monopolar Biphasic Multiple Stimulation and Neural Action Potential Acquisition (2020) (1)
Characterization on ESD devices with test structures in silicon germanium RF BiCMOS process (2004) (1)
ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS technology (1996) (1)
On-chip ESD protection design for HV integrated circuits (2016) (1)
Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-μm CMOS integrated circuits (2004) (1)
Novel electrostatic discharge protection design for nanoelectronics in nanoscale CMOS technology (2003) (1)
ESD Failures of GaN-on-Si D-Mode AlGaN/GaN MIS-HEMT and HEMT Devices for 5G Telecommunications (2021) (1)
Optimization on On-Chip Surge Protection Device for USB Type-C HV Pins (2020) (1)
Design of On-Panel Digital-to-Analog Converter with Reordering Decoder Circuit in LTPS Technology (2008) (1)
Novel ESD implantation for sub-quarter-micron CMOS technology with enhanced machine-model ESD robustness (2002) (1)
Methods to improve machine-model ESD robustness of NMOS devices in fully-salicided CMOS technology (2005) (1)
ESD-Event Detector for ESD Control Applications in Semiconductor Manufacturing Factories (2022) (1)
P‐49: Design of Digital Time‐Modulation Pixel Memory Circuit on Glass Substrate for Low Power Application (2011) (1)
Latch-Up Prevention With Autodetector Circuit to Stop Latch-Up Occurrence in CMOS-Integrated Circuits (2022) (1)
Design and implementation of readout circuit on glass substrate with digital correction for touch‐panel applications (2011) (1)
Latchup-free fully-protected ESD protection circuit for input pad of submicron CMOS ICs (1997) (1)
An on-chip ESD protection circuit with complementary SCR structures for submicron CMOS ICs (1994) (1)
Design of on-chip power-rail ESD clamp circuit with ultra-small capacitance to detect ESD transition (2009) (1)
FOR TRANSIENT-JNDUCED LATCHUP WITH BI-POLAR TRIGGER (2005) (1)
On-panel electrostatic discharge (ESD) protection design with thin-film transistor in LTPS process (2007) (1)
ESD Protection Design for Mixed-Voltage I/O Interfaces -- Overview (2005) (1)
Co-Design on Broadband CMOS RF Distributed Amplifier With On-Chip ESD Protection Circuit (2004) (1)
Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOC IC's (2003) (1)
Transient-to-digital converter to detect electrical fast transient (EFT) disturbance for system protection design (2011) (1)
Automation of Synchronous Bias Transmission Line Pulsing System (2007) (1)
Chip-level and board-level CDM ESD tests on IC products (2009) (1)
A new Schmitt trigger circuit in a 0.13 /spl mu/m 1/2.5 V CMOS process to receive 3.3 V input signals (2004) (1)
Design on new tracking circuit of I/O buffer in 0.13-/spl mu/m cell library for mixed-voltage application (2006) (1)
The Impact of N-Drift Implant on ESD Robustness of High-Voltage NMOS with Embedded SCR Structure in 40-V CMOS Process (2007) (1)
Study on CDM ESD Robustness Among On-Chip Decoupling Capacitors in CMOS Integrated Circuits (2021) (1)
Single Chip of Electrostatic Discharge Detector for IC Manufacturing Field Control (2022) (1)
Power-Rail ESD Clamp Circuit with Polysilicon Diodes Against False Trigger During Fast Power-on Events (2018) (1)
Miniaturized Intracerebral Potential Recorder for Long-Term Local Field Potential of Deep Brain Signals (2020) (1)
ESD Robustness of LTPS Diodes and N-channel TFTs (2003) (1)
Compensation circuit with additional junction sensor to enhance latchup immunity for CMOS integrated circuits (2015) (1)
Live demonstration: Implantable stimulator for epileptic seizure suppression with loading impedance adaptability (2012) (1)
On-Chip Transient Detection Circuit for Microelectronic Systems Against Electrical Transient Disturbances due to ESD Events (2018) (1)
A New Architecture for Charge Pump Circuit Without Suffering Gate-Oxide Reliability in Low-Voltage CMOS Processes (2007) (1)
Evaluation on ESD robustness of LTPS diode and TFT device by transmission line pulsing (TLP) technique (2003) (1)
ESD Protection Design with Low-Leakage Consideration for Silicon Chips of IoT Applications (2017) (1)
ESD-induced latchup-like failure in a touch panel control IC (2017) (1)
ESD protection structure with embedded high-voltage p-type SCR for automotive vacuum-fluorescent-display (VFD) applications (2005) (1)
Modeling the parasitic capacitance of ESD protection SCR to co-design matching network in RF ICs (2010) (1)
Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-μm CMOS technology (2007) (1)
CORDIC implementation of RSSI localization method (2010) (1)
Electrostatic discharge protection scheme without leakage current path for CMOS IC operating in power-down-mode condition on a system board (2006) (1)
Design of stimulus driver to suppress epileptic seizure with adaptive loading consideration (2010) (1)
CMOS on-chip ESD protection design with substrate-triggering technique (1998) (1)
ESD HBM Discharge Model in RF GaN-on-Si (MIS)HEMTs (2021) (1)
New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness in per unit layout area (1997) (1)
Transient-to-digital converter for protection design in CMOS integrated circuits against electrical fast transient (2009) (1)
Design and Realization of Delta-Sigma A/D Converter in LTPS Technology (2009) (0)
A CMOS Synchronized Sample-and-Hold Artifact Blanking Analog Front-End Local Field Potential Acquisition Unit With $\pm$3.6-V Stimulation Artifact Tolerance and Monopolar Electrode-Tissue Impedance Measurement Circuit for Closed-Loop Deep Brain Stimulation SoCs (2023) (0)
SCR-based transient detection circuit for on-chip protection design against system-level electrical transient disturbance (2014) (0)
Analysis and Prevention on NC-ball induced ESD Damages in a 683-Pin BGA Packaged Chipset IC (2003) (0)
On-Chip Over-Voltage Protection Design Against Surge Events on the CC Pin of USB Type-C Interface (2020) (0)
Efficient output ESD protection for 0.5-/spl mu/m high-speed CMOS SRAM IC with well-coupled technique (1996) (0)
Design of On-Chip Transient Detection Circuit for System-Level ESD Protection (2008) (0)
ESD protection design for radio-frequency integrated circuits in nanoscale CMOS technology (2013) (0)
Co-Design Strategy With Low-C Consideration for On-Chip ESD Protection in RF ICs (2008) (0)
System-Level ESD Protection Design with On-Chip Transient Detection Circuit (2006) (0)
ESD HBM Discharge Model in RF GaN-on-Si (MIS)HEMTs (2022) (0)
System-Level ESD-Induced Voltage Fluctuation to the Power of Integrated Circuits on System Board (2022) (0)
Circuit design to achieve whole-chip ESD protection for UXGA/HDTV LCOS IC product (2004) (0)
ESD protection designs with lowcapacitance consideration for radiofrequency integrated circuits (2010) (0)
SD(Eleetrostatic Discharg e Protection Design foranoeectronics inCMOS ecnolo (2006) (0)
25.2: Invited Paper: ESD and EOS Impacts during Module Assembly Processes for Display Panels (2013) (0)
Dummy-Gate Structure to Improve Turn-on Speed of Silicon-Controlled Rectifier (SCR) Device for Effective Electrostatic Discharge (ESD) Protection (2003) (0)
CMOS output buffer with an ESD protection circuit (1995) (0)
Efficient Output Esd Protection Of High-speed Sram Ic With Well-coupled Technique In Sub-pm Cmos Technology (1997) (0)
ESD protection design for RF circuits in CMOS technology with low-c implementation (2008) (0)
Design of high-voltage-tolerant stimulus driver with adaptive loading consideration to suppress epileptic seizure in a 0.18-μm CMOS process (2014) (0)
Appendix A: Practical ApplicationExtractions of Latchup Design Rules in a 0.18m 1.8 V/3.3V Silicided CMOS Process (2009) (0)
DEGRADATION OF SAMPLE-AND-HOLD AMPLIFIER DUE TO GATE-OXIDE OVERSTRESS IN A 130-NM CMOS PROCESS (2006) (0)
Design of On-Chip ESD Protection Circuits with Consideration of Gate-Oxide Reliability (2005) (0)
ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure (2005) (0)
Layout verification to improve ESD/latchup immunity of scaled-down CMOS cell libraries (1997) (0)
SESSION T2A: Tutorial: Advanced ESD protection design for CMOS circuits and systems (2015) (0)
TLU Dependency on Power‐Pin Damping Frequency and Damping Factor in CMOS Integrated Circuits (2010) (0)
Briefs ESD Protection for Output Pad with Well-Coupled Field-Oxide Device in 0 . 5m CMOS Technology (1998) (0)
New design concept for on-chip ESD protection circuits with already-on device in nanoscale CMOS technology (2004) (0)
Schottky-Embedded Isolation Ring to Improve Latch-Up Immunity Between HV and LV Circuits in a 0.18 μm BCD Technology (2022) (0)
Design of Dual-Configuration Dual-Mode Stimulator in Low-Voltage CMOS Process for Neuro-Modulation. (2023) (0)
Kondensatorgetriggerte protection circuit against electrostatic discharges (1996) (0)
Design on the Low-Leakage-Current Diode String for ESD Protection in SiGe BiCMOS Process (2005) (0)
Surge protection design with surge-to-digital converter for microelectronic circuits and systems (2018) (0)
Latchup-Like Failure of Power-Rail ESD Clamp Circuits in CMOS Integrated Circuits Under System-Level ESD Test (2007) (0)
On-Chip Self-Reset Transient Detection Circuit for System-Level ESD Protection (2017) (0)
Comprehensive Investigations of HBM ESD Robustness for GaN-on-Si RF HEMTs (2022) (0)
應用於900–1800MHz GSM規格的高功率CMOS T/R開關之靜電放電防護設計 (2017) (0)
Protection circuitry against electrostatic discharges (1996) (0)
ESD protection for slew-rate-controlled output buffer in a 0.5 μm CMOS SRAM technology (1998) (0)
Electronic input or output buffer circuit having MOS transistor having a plurality of loop-shaped cells (1995) (0)
Test structures to verify ESD robustness of on-glass devices in LTPS technology (2004) (0)
Physical Mechanism of TLU under the SystemLevel ESD Test (2009) (0)
Investigation of CDM ESD Protection Capability Among Power-Rail ESD Clamp Circuits in CMOS ICs With Decoupling Capacitors (2023) (0)
Novel ESD Protection Design for Nanoscale CMOS Integrated Circuits (2003) (0)
On-Chip ESD Protection Design for UXGA / HDTV LCoS in 0 . 35-μ m CMOS Technology (2004) (0)
Circuit Design of Crystal Oscillator in Mixed-Voltage-Tolerant I/O Interfaces with Low-Voltage Devices (2007) (0)
CMOS device with hexagonal cells (1996) (0)
P‐45: On‐Chip ESD Protection Design for UXGA/HDTV LCoS in 0.35‐μm CMOS Technology (2004) (0)
TLU in CMOS ICs in the Electrical Fast Transient Test (2009) (0)
DESIGN AND IMPLEMENTATION OF CRYSTAL-LESS CLOCK GENERATOR WITH PROCESS VOLTAGE TEMPERATURE COMPENSATION (2017) (0)
TLU Prevention in PowerRail ESD Clamp Circuits (2010) (0)
ROT-Harris: A Dynamic Approach to Asynchronous Interest Point Detection (2021) (0)
Guest Editorial: Special Issue on Selected Papers From IEEE ISCAS 2019 (2019) (0)
Editorial: Microelectronic Implants for Central and Peripheral Nervous System: Overview of Circuit and System Technology (2021) (0)
Study on Transmitter with Stacking-MOS Structure of Interface Circuits for Cross-Domain CDM ESD Protection (2021) (0)
On-Chip Transient Detection Circuit with SCR as Memory Unit for System-Level ESD Protection (2011) (0)
High-Voltage Generator with Multi-Stage Selection in Low-Voltage CMOS Process (2017) (0)
Design of 2xVDD-Tolerant Power-Rail ESD Clamp Circuit Against False Trigger During Fast Power-ON Events (2021) (0)
Study of Voltage-Step Dependency on the TLP-Measured Secondary Breakdown Current (It 2 ) of ESD Clamp Circuit in a 16V Double-Diffused Drain MOS (DDDMOS) Process (2012) (0)
An Ultra-Low Voltage CMOS Voltage Controlled Oscillator with Process and Temperature Compensation (2017) (0)
Design of Electrical Stimulator with High-Voltage-Tolerant Stimulus Driver in a 0 . 18 μ m Low-Voltage CMOS Process (2014) (0)
Foreword for the Special Issue on ESD Technology (2012) (0)
Optimization on SCR device with low capacitance for on-chip ESD protection in UWB RF circuits (2008) (0)
Overview on Latch-Up Prevention in CMOS Integrated Circuits by Circuit Solutions (2023) (0)
Closed-Loop Neuromodulation System-on-Chip (SoC) for Detection and Treatment of Epilepsy (2021) (0)
The Failure Mechanism of the Guard-Rings in Two Different Power Domains during the Latch-Up Test (2022) (0)
Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology (2009) (0)
ESD Protection Design for CMOS Integrated Circuits with Mixed-Voltage I/O Interfaces (2006) (0)
Closed-loop Stimulation and Control of Epileptic Seizures in an Implantable Neural-Prosthetic Device (2015) (0)
Study of board-level noise filters to prevent transient-induced latchup in CMOS integrated circuits during EMC/ESD test (2006) (0)
On-chip detection circuit for protection design in display panel against electrical fast transient (EFT) disturbance (2011) (0)
Protection circuit against electrostatic discharge comprising a capacitor circuit (1995) (0)
Electrostatic discharge (ESD) protection for CMOS output buffers in scaled-down VLSI technology (1998) (0)
MOS cell, multiple cell transistor and IC chip (1995) (0)
Verification of the beta oscillations in the subthalamic nucleus of the MPTP-induced parkinsonian minipig model (2022) (0)
Design of a Bone-Guided Cochlear Implant Microsystem With Monopolar Biphasic Multiple Stimulations and Evoked Compound Action Potential Acquisition and Its <italic>In Vivo</italic> Verification (2021) (0)
US 7 , 466 , 188 B 2 Page 2 OTHER PUBLICATIONS Taw ? (2013) (0)
On-Glass Bandgap Voltage Reference Circuit in a 3-μ m LTPS Process (2008) (0)
Design of Low-Voltage-Trigger SCR for ESD Protection in 28nm CMOS Process (0)
2xVDD-Tolerant Power-Rail ESD Clamp Circuit With Low Standby Leakage in 65-nm CMOS Process (2010) (0)
Design of 2×VDD logic gates with only 1×VDD devices in nanoscale CMOS technology (2013) (0)
Circuit Design of Electrical Stimulator Realized in 0.18μm CMOS Process for Epileptic Seizure Suppression (2015) (0)
ESD Protection Design of High-Linearity SPDT CMOS T/R Switch for Cellular Applications (2019) (0)
Whole-Chip ESD Protection Design with SCR for RF Applications in 65-nm CMOS Process (2014) (0)
Novel Implantation Method to Improve Machine-Model Electrostatic Discharge Robustness of Stacked N-Channel Metal-Oxide Semiconductors (NMOS) in Sub-Quarter-Micron Complementary Metal-Oxide Semiconductors (CMOS) Technology (2002) (0)
From Bioelectronics to Nanobioelectronics: The Biomedical Electronics Translational Research Center [Highlights] (2021) (0)
A Gigahertz Low-Noise Amplifier with ESD Protection in Nanoscale CMOS Technology (2016) (0)
Optimization on Bi-Directional PNP ESD Protection Device for High-Voltage FlexRay Applications (2022) (0)
Efficient layout style of CMOS output buffer to improve driving capability of low-voltage submicron CMOS IC's (1995) (0)
Low-Capacitance and Low-Loss Bond Pad Design using LC-Resonator Structure in CMOS Technology for RF and High-Speed Applications (2009) (0)
Introductory Invited Paper Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology q (2006) (0)
Cmos electrostatic discharge protection circuit using low-voltage trigger silicon control rectifier (1995) (0)
lementary- CR ESD Protecti (1996) (0)
Layout Verification For Submicron CMOS Cell Libraries To Improve ESD/latchup Reliability (1997) (0)
On-Panel Analog Output Buffer with Level Shifting Function in LTPS Technology (2009) (0)
On-chip ESD protection designs in RF integrated circuits for radio and wireless applications (2013) (0)
New transient detection circuit to detect ESD-induced disturbance for automatic recovery design in display panels (2011) (0)
Design of Analog Circuits on Glass Substrate (2008) (0)
Analyze the ESD Discrepancy between Grounded-Gate and Floating-Gate Power Transistors with Gate Electric Field and Magnetic Field Induced by ESD (2022) (0)
A protection circuit against electrostatic discharge substrate tripping on an integrated circuit integration depth (1998) (0)
Area-efficient layout design for output transistors with consideration of ESD reliability (1996) (0)
Editorial Introduction to the Special Issue on Electrostatic Discharge and Immunity—From IC to System (2022) (0)
2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, Hsinchu, Taiwan, April 22-24, 2013 (2013) (0)
New on-chip transient detection circuit to improve electromagnetic susceptibility of microelectronic systems (2017) (0)
Special Layout Issues for Latchup Prevention (2009) (0)
Optimization on Layout Structures of LTPS TFTs for On-Panel ESD Protection Design (2006) (0)
A 8 Phases 192MHz Crystal-Less Clock Generator with PVT Calibration (2017) (0)
29.7 ESD Protection for Mixed-Voltage I/O in Low- (2006) (0)
CMOS RF VCO Design with Substrate Noise Consideration (2005) (0)
Design of 2.4-GHz T/R switch with embedded ESD protection devices in CMOS process (2017) (0)
Design of Transient Detection Circuit for On-Chip System-Level ESD Protection (2006) (0)
應用於2.4GHz T/R開關前端電路之靜電放電防護設計 (2015) (0)
Over-Voltage Protection on the CC Pin of USB Type-C Interface against Electrical Overstress Events (2020) (0)
Abnormal ESDDamagesOccurinInterface Circuits between Different PowerDomainsinND-ModeMM ESDStress (2006) (0)
A 56–67 GHz low-noise amplifier with 5.1-dB NF and 2.5-kV HBM ESD protection in 65-nm CMOS (2012) (0)

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