Mircea R. Stan
#162,275
Most Influential Person Now
Mircea R. Stan's AcademicInfluence.com Rankings
Mircea R. Stanengineering Degrees
Engineering
#7035
World Rank
#8394
Historical Rank
Electrical Engineering
#2163
World Rank
#2269
Historical Rank
Mircea R. Stancomputer-science Degrees
Computer Science
#9431
World Rank
#9905
Historical Rank
Computer Architecture
#60
World Rank
#62
Historical Rank
Database
#6397
World Rank
#6630
Historical Rank
Download Badge
Engineering Computer Science
Mircea R. Stan's Degrees
- PhD Electrical Engineering Stanford University
- Masters Electrical Engineering Stanford University
Why Is Mircea R. Stan Influential?
(Suggest an Edit or Addition)Mircea R. Stan's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- Temperature-aware microarchitecture (2003) (1281)
- Bus-invert coding for low-power I/O (1995) (1024)
- HotSpot: a compact thermal modeling methodology for early-stage VLSI design (2006) (962)
- Temperature-aware microarchitecture: Modeling and implementation (2004) (773)
- Control-theoretic techniques and thermal-RC modeling for accurate and localized dynamic thermal management (2002) (423)
- Relaxing non-volatility for fast and energy-efficient STT-RAM caches (2011) (404)
- Compact thermal modeling for temperature-aware design (2004) (347)
- Advances and Future Prospects of Spin-Transfer Torque Random Access Memory (2010) (336)
- The Promise of Nanomagnetics and Spintronics for Future Logic and Universal Memory (2010) (311)
- HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects (2003) (305)
- Molecular electronics: from devices and interconnect to circuits and architecture (2003) (284)
- A Case for Thermal-Aware Floorplanning at the Microarchitectural Level (2005) (207)
- CMOS/nano co-design for crossbar-based molecular electronic systems (2003) (185)
- Low-power encodings for global communication in CMOS VLSI (1997) (184)
- Odd/Even bus invert with two-phase transfer for buses with coupling (2002) (143)
- Temperature-Aware Computer Systems: Opportunities and Challenges (2003) (128)
- Power issues related to branch prediction (2002) (127)
- Scaling with Design Constraints: Predicting the Future of Big Chips (2011) (120)
- Control-theoretic dynamic frequency and voltage scaling for multimedia workloads (2002) (118)
- Many-core design from a thermal perspective (2008) (114)
- Delivering on the promise of universal memory for spin-transfer torque RAM (STT-RAM) (2011) (111)
- Monitoring temperature in FPGA based SoCs (2005) (108)
- HotSpot: a dynamic compact thermal model at the processor-architecture level (2003) (108)
- HotSpot 6.0: Validation, Acceleration and Extension (2015) (108)
- Circuit-level techniques to control gate leakage for sub-100nm CMOS (2002) (108)
- Power-aware computing (2003) (107)
- Limited-weight codes for low-power I/O (1994) (107)
- Accurate, Pre-RTL Temperature-Aware Design Using a Parameterized, Geometric Thermal Model (2008) (103)
- Reducing multimedia decode power using feedback control (2003) (85)
- Differentiating the roles of IR measurement and simulation for power and temperature-aware design (2009) (84)
- System level leakage reduction considering the interdependence of temperature and leakage (2004) (80)
- Interconnect lifetime prediction under dynamic stress for reliability-aware design (2004) (79)
- Temperature-Aware Microarchitecture: Extended Discussion and Results (2003) (79)
- State-preserving vs. non-state-preserving leakage control in caches (2004) (79)
- Long and Fast Up/Down Counters (1998) (74)
- An Improved Block-Based Thermal Model in HotSpot 4.0 with Granularity Considerations (2007) (70)
- How I Learned to Stop Worrying and Love Flash Endurance (2010) (69)
- Dual-VT SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.13 μm technology generation (2000) (67)
- Association Rule Mining with the Micron Automata Processor (2015) (67)
- CLEAR: Cross-layer exploration for architecting resilience: Combining hardware and software techniques to tolerate soft errors in processor cores (2016) (66)
- NBTI resilient circuits using adaptive body biasing (2008) (66)
- Architecture implications of pads as a scarce resource (2014) (61)
- Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay (2009) (61)
- Coding a terminated bus for low power (1995) (58)
- The need for a full-chip and package thermal model for thermally optimized IC designs (2005) (58)
- Power-aware branch prediction: characterization and design (2004) (57)
- ANMLzoo: a benchmark suite for exploring bottlenecks in automata processing engines and architectures (2016) (56)
- Challenges in clockgating for a low power ASIC methodology (1999) (53)
- Improved thermal management with reliability banking (2005) (51)
- Interconnect Lifetime Prediction for Reliability-Aware Systems (2007) (48)
- Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache (2002) (47)
- Parameterized physical compact thermal modeling (2005) (47)
- Circuit-level techniques to control gate leakage for sub-100 nm CMOS (2002) (44)
- FlashPower: A detailed power model for NAND flash memory (2010) (43)
- Spintronics technology: past, present and future (2016) (42)
- Modeling Power Consumption of NAND Flash Memories Using FlashPower (2013) (41)
- Optimal voltages and sizing for low power [CMOS VLSI] (1999) (40)
- Diluted chirality dependence in edge rough graphene nanoribbon field-effect transistors (2009) (40)
- A case for CMOS/nano co-design (2002) (40)
- SRAM-based NBTI/PBTI sensor system design (2010) (38)
- Interaction of scaling trends in processor architecture and cooling (2010) (38)
- Optimal procrastinating voltage scheduling for hard real-time systems (2005) (38)
- Modeling and analyzing NBTI in the presence of Process Variation (2011) (37)
- Low power architecture of the soft-output Viterbi algorithm (1998) (37)
- A 25 GHz 32 b integer-execution core in 130 nm dual-V/sub T/ CMOS (2002) (37)
- HotSpot : Techniques for Modeling Thermal Effects at the Processor-Architecture Level (2002) (37)
- An overview of micron's automata processor (2016) (35)
- 5-GHz 32-bit Integer Execution Core in 130-nm Dual-VT CMOS (2001) (35)
- A unified design space for regular parallel prefix adders (2004) (34)
- A Programmable Majority Logic Array Using Molecular Scale Electronics (2006) (33)
- Two-dimensional codes for low power (1996) (33)
- ArchFP: Rapid prototyping of pre-RTL floorplans (2012) (33)
- Designing CMOS/molecular memories while considering device parameter variations (2007) (33)
- REAPR: Reconfigurable engine for automata processing (2017) (32)
- Analog VLSI for robot path planning (1994) (32)
- Low threshold CMOS circuits with low standby current (1998) (31)
- Intra-disk Parallelism: An Idea Whose Time Has Come (2008) (30)
- Progress and Prospects of Spin Transfer Torque Random Access Memory (2012) (30)
- The STeTSiMS STT-RAM simulation and modeling system (2011) (28)
- Procrastinating voltage scheduling with discrete frequency sets (2006) (27)
- Design approaches for hybrid CMOS/molecular memory based on experimental device data (2006) (27)
- Exploring the thermal impact on manycore processor performance (2010) (27)
- Temperature-Aware Architecture: Lessons and Opportunities (2011) (26)
- Nondeterministic Finite Automata in Hardware-the Case of the Levenshtein Automaton (2015) (26)
- Graphene devices, interconnect and circuits — challenges and opportunities (2009) (26)
- Temperature-to-power mapping (2010) (25)
- Impala: Algorithm/Architecture Co-Design for In-Memory Multi-Stride Pattern Matching (2020) (24)
- Monolithically Patterned Wide–Narrow–Wide All-Graphene Devices (2008) (23)
- Low-power CMOS with subvolt supply voltages (2001) (23)
- eAP: A Scalable and Efficient In-Memory Accelerator for Automata Processing (2019) (21)
- Back to the Future: Digital Circuit Design in the FinFET Era (2017) (20)
- The CMOS/nano interface from a circuits perspective (2003) (20)
- MNCaRT: An Open-Source, Multi-Architecture Automata-Processing Research and Execution Ecosystem (2018) (20)
- DyHard-DNN: Even More DNN Acceleration with Dynamic Hardware Reconfiguration (2018) (20)
- Limits to voltage scaling from the low power perspective (2000) (20)
- Synchronous up/down counter with clock period independent of counter size (1997) (19)
- Large-signal two-terminal device model for nanoelectronic circuit analysis (2004) (19)
- Modeling and experimental demonstration of accelerated self-healing techniques (2014) (19)
- AutomataZoo: A Modern Automata Processing Benchmark Suite (2018) (18)
- Stacking SRAM banks for ultra low power standby mode operation (2010) (18)
- Attacking an SRAM-Based PUF through Wearout (2016) (17)
- Power reduction techniques for a spread spectrum based correlator (1997) (17)
- Fulcrum: A Simplified Control and Access Mechanism Toward Flexible and Practical In-Situ Accelerators (2020) (17)
- Split-path skewed (SPS) CMOS buffer for high performance and low power applications (2001) (16)
- Work hard, sleep well - Avoid irreversible IC wearout with proactive rejuvenation (2016) (16)
- Improving SRAM Vmin and yield by using variation-aware BTI stress (2010) (16)
- Skyrmionics—Computing and memory technologies based on topological excitations in magnets (2021) (16)
- Alloyed Branch History: Combining Global and Local Branch History for Robust Performance (2003) (16)
- Optimal logarithmic adder structures with a fanout of two for minimizing the area-delay product (2001) (16)
- Grapefruit: An Open-Source, Full-Stack, and Customizable Automata Processing on FPGAs (2020) (16)
- An ahead pipelined alloyed perceptron with single cycle access time (2004) (16)
- FlexAmata: A Universal and Efficient Adaption of Applications to Spatial Automata Processing Accelerators (2020) (16)
- Hierarchical Temporal Memory on the Automata Processor (2017) (15)
- Breaking the power delivery wall using voltage stacking (2012) (14)
- SODA: Sensitivity Based Optimization of Disk Architecture (2007) (14)
- Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience) (2017) (14)
- A computer-architecture approach to thermal management in computer systems: opportunities and challenges (2004) (14)
- Near-Memory Data Services (2016) (14)
- Generating efficient and high-quality pseudo-random behavior on Automata Processors (2016) (14)
- Tracking On-Chip Age Using Distributed, Embedded Sensors (2012) (13)
- Architecture-Level Compact Thermal R-C Modeling (2002) (13)
- Self consistent parameterized physical MTJ compact model for STT-RAM (2010) (13)
- Banking Chip Lifetime: Opportunities and Implementation (2005) (12)
- Walking pads: Managing C4 placement for transient voltage noise minimization (2014) (12)
- Microarchitectural Floorplanning for Thermal Management: A Technical Report (2005) (12)
- Systolic counters with unique zero state (2004) (12)
- Transient voltage noise in charge-recycled power delivery networks for many-layer 3D-IC (2015) (11)
- Toward an Architectural Treatment of Parameter Variations (2005) (11)
- Graphene Nanoribbons: From Chemistry to Circuits (2011) (11)
- Computing and Memory Technologies based on Magnetic Skyrmions (2021) (11)
- Many Core Design from a Thermal Perspective: Extended Analysis and Results (2008) (11)
- Using Intradisk Parallelism to Build Energy-Efficient Storage Systems (2009) (11)
- Hybrid CMOS/Molecular Electronic Circuits (2006) (10)
- Sensitivity-Based Optimization of Disk Architecture (2009) (10)
- SC-SD: Towards Low Power Stochastic Computing Using Sigma Delta Streams (2018) (10)
- A Scalable and Efficient In-Memory Interconnect Architecture for Automata Processing (2019) (10)
- Non-Manhattan maze routing (2004) (10)
- A cross-layer design exploration of charge-recycled power-delivery in many-layer 3D-IC (2015) (10)
- Temporal Memory With Magnetic Racetracks (2020) (10)
- Low-Power Encodings for Global Communication (1997) (10)
- A 2.5 Mb/s, 23 mW SOVA traceback chip for turbo decoding applications (2001) (9)
- Walking pads: Fast power-supply pad-placement optimization (2014) (9)
- MTCMOS with outer feedback (MTOF) flip-flops (2003) (9)
- Sensitivity Based Power Management of Enterprise Storage Systems (2008) (9)
- Spin-torque oscillation in large size nano-magnet with perpendicular magnetic fields (2016) (9)
- Active threshold compensation circuit for improved performance in cooled CMOS systems (2001) (9)
- Control-theoretic dynamic frequency and voltage scaling (2002) (8)
- When “things” get older: Exploring circuit aging in IoT applications (2018) (8)
- ASC-FFT: Area-Efficient Low-Latency FFT Design Based on Asynchronous Stochastic Computing (2019) (8)
- Circadian Rhythms for Future Resilient Electronic Systems (2020) (8)
- CORDIC implementation with parameterizable ASIC/SoC flow (2010) (8)
- Electronic ratchet: A non-equilibrium, low power switch (2011) (8)
- Very Low Voltage (VLV) Design (2017) (8)
- Dual-V/sub T/ SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.13 /spl mu/m technology generation (2000) (8)
- Computing With Nonequilibrium Ratchets (2013) (8)
- Temperature-Aware Modeling and Banking of IC Lifetime Reliability (2005) (8)
- Hot Leakage: An Architectural, Temperature-Aware Model of Subthreshold and Gate Leakage (2012) (8)
- RAMA: a self-assembled multiferroic magnetic QCA for low power systems (2011) (7)
- Integrated Synthesis Methodology for Crossbar Arrays (2018) (7)
- Analysis of Temporal and Spatial Temperature Gradients for IC Reliability (2012) (7)
- Comparative delay, noise and energy of high-performance domino adders with stack node preconditioning (SNP) (2000) (7)
- Architectural implications of spatial thermal filtering (2013) (7)
- Report for the NSF Workshop on Cross ‐ layer Power Optimization and Management (2012) (7)
- Tolerating the Consequences of Multiple EM-Induced C4 Bump Failures (2016) (7)
- Multi-Dimensional Circuit and Micro-Architecture Level Optimization (2007) (7)
- Analog VLSI for robot path planning (1992) (7)
- Computing with hybrid CMOS/STO circuits (2014) (6)
- A multi-output on-chip switched-capacitor DC-DC converter for near- and sub-threshold power modes (2014) (6)
- Towards on-node Machine Learning for Ultra-low-power Sensors Using Asynchronous Σ Δ Streams (2020) (6)
- Spin torque nano oscillators as key building blocks for the Systems-on-Chip of the future (2014) (6)
- Physically-Based Compact Thermal Modeling — Achieving Parametrization and Boundary Condition Independence (2004) (6)
- Charge recycling on-chip DC-DC conversion for near-threshold operation (2012) (6)
- Transactions on Vlsi Systems 1 Low Power Cmos with Sub-volt Supply Voltages (2001) (6)
- Atomistic deconstruction of clear performance advantages of a monolithically patterned wide-narrow-wide all-graphene FET (2009) (6)
- Pre-RTL Voltage and Power Optimization for Low-Cost, Thermally Challenged Multicore Chips (2017) (5)
- MCPENS : Multiple-Critical-Path Embeddable NBTI Sensors for Dynamic Wearout Management (2015) (5)
- Breaking the 3D IC power delivery wall (2012) (5)
- Low power parallel spread-spectrum correlator (1999) (5)
- Cross-Layer Resilience: Challenges, Insights, and the Road Ahead (2019) (5)
- Electromigration-aware design (2009) (5)
- Implications of accelerated self-healing as a key design knob for cross-layer resilience (2017) (5)
- Design and Implementation of an Energy Efficient Multimedia Playback System (2006) (5)
- Conformational Molecular Switches for Post-CMOS Nanoelectronics (2007) (5)
- Flexi-AES: A Highly-Parameterizable Cipher for a Wide Range of Design Constraints (2019) (5)
- CMOS circuits with subvolt supply voltages (2002) (5)
- Accurate Back-of-the-Envelope Transistor Model for Deep Sub-micron MOS (2007) (4)
- Low Power Design for ASIC Cores (2001) (4)
- Analog Turbo Decoder Implemented in SiGe BiCMOS Technology (2003) (4)
- Towards low-power random forest using asynchronous computing with streams (2019) (4)
- Deep Healing: Ease the BTI and EM Wearout Crisis by Activating Recovery (2017) (4)
- Controlling the Reliability of SRAM PUFs With Directed NBTI Aging and Recovery (2018) (4)
- OldSpot: A Pre-RTL Model for Fine-Grained Aging and Lifetime Optimization (2018) (4)
- Reliable Processing in Flash With High Temperature (2021) (4)
- Hardware based spatio-temporal neural processing backend for imaging sensors: towards a smart camera (2018) (4)
- Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights (2017) (4)
- An Overflow-free Quantized Memory Hierarchy in General-purpose Processors (2019) (4)
- A three-level toggle-avoid bus signaling scheme (2005) (4)
- SRAM based Opportunistic Energy Efficiency Improvement in Dual-Supply Near-Threshold Processors (2018) (4)
- Granularity of Microprocessor Thermal Management: A Technical Report (2012) (4)
- Synchronized Spin Torque Nano-Oscillators: From Theory to Applications (2015) (4)
- CLEAR: Cross-Layer Exploration for Architecting Resilience (2017) (4)
- Agile-AES: Implementation of configurable AES primitive with agile design approach (2022) (4)
- Low-Power, Highly Reliable Dynamic Thermal Management by Exploiting Approximate Computing (2020) (4)
- Perfect 3-Limited-Weight Code for Low Power I/O (2004) (4)
- Interconnect Lifetime Prediction with Temporal and Spatial Temperature Gradients for Reliability-Aware Design and Runtime Management: Modeling and Applications (2006) (4)
- A new taxonomy for reconfigurable prefix adders (2012) (3)
- PiMulator: a Fast and Flexible Processing-in-Memory Emulation Platform (2022) (3)
- Nano-pattemed coupled spin torque nano oscillator (STNO) arrays — A potentially disruptive multipurpose nanotechnology (2013) (3)
- Asynchronous Stochastic Computing (2019) (3)
- Microfluidic Cooling for 3D-IC with 3D Printing Package (2019) (3)
- Optimal Procrastinating Voltage for Hard Real-Time Systems (2005) (3)
- Thermal benefit of multi-core floorplanning: A limits study (2011) (3)
- Reducing stray currents in molecular memory through data encoding (2007) (3)
- An Improved Hotspot Block-based Thermal Model with Granularity Considerations (Extended Discussion) (2012) (3)
- Magnetic skyrmion-based programmable hardware (2020) (3)
- Automata Processing in Reconfigurable Architectures (2019) (3)
- Error-latency Trade-off for Asynchronous Stochastic Computing with ΣΔ Streams for the IoT (2019) (3)
- A digitally-controlled power-aware low-dropout regulator to reduce standby current drain in ultra-low-power MCU (2015) (2)
- Switching limits in nano-electronic devices (2010) (2)
- ATCPiM: Analog to Time Coded Processing in Memory for IoT at the Edge (2021) (2)
- Method for characterizing the contact resistance of metal-vanadium dioxide thin film interfaces (2014) (2)
- Asynchronous Stream Computing for Low Power IoT (2019) (2)
- Power and Thermal Modeling of In-3D-Memory Computing (2021) (2)
- Uses for Random and Stochastic Input on Micron’s Automata Processor (2016) (2)
- Thermal Simulation of Processing-in-Memory Devices using HotSpot 7.0 (2021) (2)
- MTTF Enhancement Power-C4 Bump Placement Optimization (2019) (2)
- Teaching Top-Down ASIC/SoC Design vs Bottom-Up Custom VLSI (2007) (2)
- Circuit Techniques for BTI and EM Accelerated and Active Recovery (2019) (2)
- Memristive Learning Cellular Automata: Theory and Applications (2020) (2)
- Design and Aging Challenges in FinFET Circuits and Internet of Things (IoT) Applications (2019) (2)
- VLSI for Next Generation CE (2020) (2)
- The selective pull-up (SP) noise immunity scheme for dynamic circuits (2002) (2)
- Compact SPICE Model of Topological Textures on Magnetic Racetracks for Design Space Exploration (2021) (2)
- Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003 (2003) (2)
- Self-assembled multiferroic magnetic QCA structures for low power systems (2012) (2)
- PPE-ARX: Area- and power-efficient VLIW programmable processing element for IoT crypto-systems (2017) (2)
- Thermal Modeling for Processors and Systems-on-Chip (2010) (2)
- A complete set of spintronic hardware building blocks for low power, small footprint, high performance neuromorphic architectures (2019) (2)
- Temperature-aware circuit design using adaptive body biasing (2007) (2)
- Experimental demonstration of standby power reduction using voltage stacking in an 8Kb embedded FDSOI SRAM (2011) (2)
- 5GHz 32b integer-execution core in 130nm dual-V/sub T/ CMOS (2002) (1)
- Schematic Driven Layout Using the MOSIS Design Kit for Advanced Analog and Mixed-Signal Design (2007) (1)
- Absolute control of chirality unnecessary for wide-narrow-wide graphene field effect transistor (2009) (1)
- Integrated microelectrode arrays for in vitro neuronal recording (2000) (1)
- Dual-Data Rate Transpose-Memory Architecture Improves the Performance, Power and Area of Signal-Processing Systems (2017) (1)
- Gate Overdrive with Split-Circuit Biasing to Substitute for Body Biasing in FinFET and UTB FDSOI Circuits (2016) (1)
- eAP (2019) (1)
- Ultra-low-power dual-phase latch based digital accelerator for continuous monitoring of wheezing episodes (2017) (1)
- Towards Everlasting Flash: Preventing Permanent Flash Cell Damage using Circadian Rhythms (2022) (1)
- Exploiting Read/Write Asymmetry to Achieve Opportunistic SRAM Voltage Switching in Dual-Supply Near-Threshold Processors (2018) (1)
- SymmTop: A Symmetric Circuit Topology for Ultra Low Power Wide Temperature-Range Applications (2015) (1)
- Experiences Using Fpgas for Temperature-aware Microarchitecture Research (1)
- Thermal Analysis of Microfluidic cooling in Processing-in-3D-Stacked Memory (2021) (1)
- Closing the power delivery/heat removal cycle for heterogeneous multi-scale systems (2016) (1)
- Gearbox: a case for supporting accumulation dispatching and hybrid partitioning in PIM-based accelerators (2022) (1)
- Reservoir Computing Based Neural Image Filters (2018) (1)
- Fourier-based Error Analysis for Computing with Asynchronous Sigma-Delta Streams (2019) (1)
- Processing-in-Memory with Temporal Encoding (2022) (1)
- Hybrid CMOS/Molecular Integrated Circuits (2009) (1)
- Low power techniques for global communication in CMOS VLSI (1996) (1)
- Regularly structured design for coping with nanoscale integration complexity (2004) (1)
- Investigating the impact of on-chip interconnection noise on dynamic thermal management efficiency (2015) (1)
- Power Issues Related to Branch Prediction — University Of Virginia Tech . Report CS-2001-25 — (2001) (1)
- Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory (2019) (1)
- Structured and tuned array generation (STAG) for high-performance random logic (2007) (0)
- Design Methods for Low-Power Implementation (2020) (0)
- Session details: Keynote (2006) (0)
- Session details: Session 3A: Low Power Circuits (2008) (0)
- Design of near threshold All Digital Delay Locked Loops (2012) (0)
- Publisher’s Note: “Skyrmionics—Computing and memory technologies based on topological excitations in magnets” [J. Appl. Phys. 130, 070908 (2021)] (2021) (0)
- Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization With Fault Tolerance (2021) (0)
- Power-aware design in modern computing systems (2007) (0)
- Accurate Back-ofthe-Envelope Transistor Model for Deep Submicron MOS Zhenyu ( Jerry ) (2007) (0)
- Scheduling Active and Accelerated Recovery to Combat Aging in Integrated Circuits (2022) (0)
- Dynamic Way Allocation for High Performance , Low Power Caches (2001) (0)
- Exploration of Charge Recycling DC-DC Conversion Using a Switched Capacitor Regulator (2013) (0)
- Cross-Layer Modeling Framework for Energy-Efficient Resilience (2014) (0)
- Microarchitecture Optimization for Asynchronous Stochastic Computing (2021) (0)
- Accelerating and Activating Recovery Against EM Wearout (2019) (0)
- Teaching processor architecture with a VLSI perspective (2002) (0)
- Intra-Disk Parallelism (2008) (0)
- TECHNICAL PROGRAM LASCAS / IBERCHIP / LAEDC (2019) (0)
- Panel discussion: Autonomy, technology, safety - Where will automotive electronics go in the next decade? (2017) (0)
- Nano-Crossbar based Computing: Lessons Learned and Future Directions (2020) (0)
- SSRL: Single Skyrmion Reconfigurable Logic Utilizing 2-D Magnus Force on Magnetic Racetracks (2022) (0)
- Analog Neural Network based on Memristor Crossbar Arrays (2019) (0)
- The Promise of Nanomagnetics andSpintronicsforFutureLogic and Universal Memory This paper provides an overview of basic principles associated with representing information in the form of magnetic polarization; spin-based memory and logic devices are reviewed. (2010) (0)
- Performance Advantages of Monolithically Patterned Wide-Narrow-Wide All-Graphene on Insulator Devices (2008) (0)
- Merged CMOS/Molecular Integrated Circuit Fabrication, Analysis, and Design (2003) (0)
- Spin-torque switching in large size nano-magnet with perpendicular magnetic fields. (2016) (0)
- Introduction to Wearout (2019) (0)
- A Design Methodology for a Low-Power, Temperature-Aware SoC Developed for Medical Image Processors (2006) (0)
- A Case for CMOShano CO-design (2002) (0)
- Accelerated and Active Self-healing Techniques for BTI Wearout (2019) (0)
- Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006 (2006) (0)
- Session 3 – Technology Variability Modeling (2010) (0)
- Cross-Layer Resilience Exploration (2015) (0)
- Panel discussion: Distributed intelligence in IoT (2016) (0)
- Interconnect Lifetime Prediction for Temperature-Aware Design (2012) (0)
- Reliability/wearout-aware design (2010) (0)
- Hybrid Mole Computer Using Vapor Phase Assembly (2006) (0)
- Reducing Design Margins by Adaptive Compensation for Thermal and Aging Variations (2012) (0)
- Breaking power delivery walls using voltage stacking (2013) (0)
- (Invited) Cross-Layer Resilience: Challenges, Insights, and the Road Ahead (2019) (0)
- From 2.5D to 3D Chiplet Systems: Investigation of Thermal Implications with HotSpot 7.0 (2022) (0)
- Future Directions in Self-healing (2019) (0)
- Gearbox (2022) (0)
- AI-PiM—Extending the RISC-V processor with Processing-in-Memory functional units for AI inference at the edge of IoT (2022) (0)
- FreezeTime: Towards System Emulation through Architectural Virtualization (2023) (0)
- Integrated planar multimicroelectrode array for in vitro recording (1997) (0)
- A post-silicon hold time closure technique using data-path tunable-buffers for variation-tolerance in sub-threshold designs (2018) (0)
- Dual-Data Rate Transpose-Memory Architecture Improves the Performance, Power and Area of Signal-Processing Systems (2016) (0)
- EXTREM-EDGE - EXtensions To RISC-V for Energy-efficient ML inference at the EDGE of IoT (2022) (0)
- ISKEVA: in-SSD key-value database engine for video analytics applications (2022) (0)
- Low-Power Design with Open-Source Hardware : Opportunities and Challenges (2018) (0)
- Thermal Performance Analysis of Mempool RISC-V Multicore SoC (2022) (0)
- An SRAD Image Processor as a Reconfigurable, Temperature-Aware SoC Designed for Low-Power Operation (2005) (0)
- Active Accelerated Self-healing as a Key Design Knob for Cross-Layer Resilience (2019) (0)
- A Discussion on the Thermal Benefit of Multicore Floorplanning at the Microarchitectural Level (2012) (0)
- New Findings on Using Queue Occupancy to Integrate Runtime Power-Saving Techniques Across the Pipeline (2003) (0)
- Co-Optimizing CPUs and Accelerators in Constrained Systems (2018) (0)
- The Importance of Temporal and Spatial Temperature Gradients in IC Reliability Analysis (2012) (0)
- Towards Wearout-aware and Accelerated Self-healing Digital Systems (2015) (0)
- Performance Evaluation of Regular Expression Matching Engines Across Different Computer Architectures (2016) (0)
- M o deling a nd Ana ly zing NB T I in t he Pres ence o f Pro ces s Va ri (2011) (0)
This paper list is powered by the following services:
What Schools Are Affiliated With Mircea R. Stan?
Mircea R. Stan is affiliated with the following schools:
