Mohamed Elmasry

Q: What Schools Are Affiliated With Mohamed Elmasry

Mohamed Elmasry is affiliated with the following schools: University of Waterloo, University of Ottawa, Cairo University

Mohamed Elmasry's AcademicInfluence.com Rankings

Mohamed Elmasry

Engineering

#5376

World Rank

#6631

Historical Rank

Electrical Engineering

#1776

World Rank

#1875

Historical Rank

Applied Physics

#2293

World Rank

#2332

Historical Rank

engineering Degrees

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Engineering

Mohamed Elmasry's Degrees

Bachelors Electrical Engineering Cairo University

Why Is Mohamed Elmasry Influential?

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According to Wikipedia, Mohamed Elmasry is a Canadian engineering professor, imam, and Muslim community leader. Biography He was born in Cairo, Egypt and received his Bachelor of Science in 1965 from Cairo University. He continued his studies in Canada earning masters and doctorate degrees in electrical engineering from the University of Ottawa in 1970 and 1974. He has worked in the area of digital integrated microchip design for over four decades.

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Mohamed Elmasry's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Low-Power Digital VLSI Design: Circuits and Systems (1995) (375)
Circuit techniques for CMOS low-power high-performance multipliers (1996) (301)
Power dissipation analysis and optimization of deep submicron CMOS digital circuits (1996) (204)
Design and optimization of multithreshold CMOS (MTCMOS) circuits (2003) (202)
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique (2002) (184)
Dynamic current mode logic (DyCML): a new low-power high-performance logic style (2001) (172)
Low-power direct digital frequency synthesis for wireless communications (2000) (170)
A global optimization approach for architectural synthesis (1990) (149)
Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies (2002) (148)
Architectural synthesis for DSP silicon compilers (1989) (140)
MOS current mode circuits: analysis, design, and variability (2005) (138)
Modeling and comparing CMOS implementations of the C-element (1998) (136)
High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies (2000) (128)
STAIC: an interactive framework for synthesizing CMOS and BiCMOS analog circuits (1992) (95)
A deep sub-V, single power-supply SRAM cell with multi-V/sub T/, boosted storage node and dynamic load (1996) (86)
Simultaneous scheduling and allocation for cost constrained optimal architectural synthesis (1991) (76)
Adaptive Body Bias for Reducing the Impacts of NBTI and Process Variations on 6T SRAM Cells (2011) (73)
Capacitance calculations in MOSFET VLSI (1982) (72)
Optimal VLSI Architectural Synthesis (1992) (69)
A Low-Noise CMOS Distributed Amplifier for Ultra-Wide-Band Applications (2008) (67)
Multi-Threshold CMOS Digital Circuits (2003) (64)
An electrically pre-equalized 10-Gb/s duobinary transmission system (2005) (63)
Multi-Threshold CMOS Digital Circuits: Managing Leakage Power (2003) (62)
A comparison of CMOS implementations of an asynchronous circuits primitive: the C-element (1996) (60)
Optimal synthesis of high-performance architectures (1992) (59)
Modified register-exchange Viterbi decoder for low-power wireless communications (2004) (54)
A 6-Bit 1.6-GS/sLow-Power Wideband Flash ADC Converter in 0.13-µm CMOS Technology (2008) (54)
The digi-neocognitron: a digital neocognitron neural network model for VLSI (1992) (53)
VLSI design synthesis with testability (1988) (52)
All-N-logic high-speed true-single-phase dynamic CMOS logic (1996) (50)
Discrete cooperative particle swarm optimization for FPGA placement (2010) (48)
Low Power Digital Vlsi Design (2015) (46)
Digital BiCMOS Integrated Circuit Design (1992) (44)
Optimal VLSI Architectural Synthesis: Area, Performance and Testability (1991) (42)
NBTI and Process Variations Compensation Circuits Using Adaptive Body Bias (2012) (41)
A 10dB 44GHz Loss-Compensated CMOS Distributed Amplifier (2007) (41)
Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional Units (2006) (40)
Scaling of digital BiCMOS circuits (1990) (39)
Advanced Low-Power Digital Circuit Techniques (1997) (38)
Analysis of the correlation structure for a neural predictive model with application to speech recognition (1994) (35)
Novel Timing Yield Improvement Circuits for High-Performance Low-Power Wide Fan-In Dynamic OR Gates (2011) (34)
A Novel Low Area Overhead Direct Adaptive Body Bias (D-ABB) Circuit for Die-to-Die and Within-Die Variations Compensation (2011) (34)
Automatic synthesis of a multi-bus architecture for DSP (1988) (33)
Power reduction via an MTCMOS implementation of MOS current mode logic (2002) (33)
Optimizing CMOS implementations of the C-element (1997) (32)
A wideband sigma-delta phase-locked-loop modulator for wireless applications (2003) (31)
Fast and efficient parametric modeling of contact-to-substratecoupling (2000) (30)
Digital MOS integrated circuits (1981) (30)
A fast lock digital phase-locked-loop architecture for wireless applications (2003) (30)
New full-voltage-swing BiCMOS buffers (1991) (30)
Generation of noise by electronic iteration of the logistic map (1987) (30)
An accurate analytical propagation delay model for high-speed CML bipolar circuits (1994) (29)
Use of charge sharing to reduce energy consumption in wide fan-in gates (1998) (29)
Mixed Signal VLSI Wireless Design: Circuits and Systems (1999) (28)
Power minimization of high-performance submicron CMOS circuits using a dual-Vdd dual-Vth (DVDV) approach (1999) (27)
Comparative Analysis of Timing Yield Improvement under Process Variations of Flip-Flops Circuits (2009) (25)
Digital bipolar integrated circuits (1983) (25)
A Design-Oriented Soft Error Rate Variation Model Accounting for Both Die-to-Die and Within-Die Variations in Submicrometer CMOS SRAM Cells (2010) (25)
A Comparative Study Between Static and Dynamic Sleep Signal Generation Techniques for Leakage Tolerant Designs (2008) (24)
A novel analytical model for evaluation of substrate crosstalk in VLSI circuits (2002) (24)
Low-power design of decimation filters for a digital IF receiver (2000) (23)
VLSI compressor design with applications to digital neural networks (1997) (22)
Low-power CMOS/BiCMOS drivers and receivers for on-chip interconnects (1995) (22)
Bootstrapped full-swing BiCMOS/BiNMOS logic circuits for 1.2-3.3 V supply voltage regime (1995) (21)
SPAID: an architectural synthesis tool for DSP custom applications (1988) (21)
VLSI Artificial Neural Networks Engineering (1994) (20)
Analysis and optimization of BiCMOS digital circuit structures (1991) (20)
Dynamic current mode logic (DyCML), a new low-power high-performance logic family (2000) (19)
Analysis and optimization of series-gated CML and ECL high-speed bipolar circuits (1996) (19)
Low-power high-performance arithmetic circuits and architectures (2002) (19)
Integration of algorithmic VLSI synthesis with testability incorporation (1988) (18)
Impact of technology scaling and process variations on RF CMOS devices (2006) (18)
A low power design approach for MOS current mode logic (2003) (17)
Energy-Efficient Noise-Tolerant Dynamic Styles for (2002) (17)
A low-power high-performance current-mode multiport SRAM (2001) (17)
On-Chip Process Variations Compensation Using an Analog Adaptive Body Bias (A-ABB) (2012) (17)
Analysis and design of low-power multi-threshold MCML (2004) (17)
Self-timed MOS current mode logic for digital applications (2002) (16)
Folded-collector integrated injection logic (1976) (15)
A low-power direct digital frequency synthesizer architecture for wireless communications (1999) (15)
Mixed analog/digital hardware synthesis of artificial neural networks (1994) (15)
Functional modeling of integrated injection logic—DC analysis (1977) (15)
Fault characterization, testing considerations, and design for testability of BiCMOS logic circuits (1992) (15)
Functional modelling of non-volatile MOS memory devices for computer-aided design (1976) (14)
MOS current mode logic: design, optimization, and variability (2004) (14)
Design and optimization of MOS current mode logic for parameter variations (2004) (14)
Impact of technology scaling on RF CMOS (2004) (14)
A low-power partitioning methodology by maximizing sleep time and minimizing cut nets (2005) (14)
Activity packing in FPGAs for leakage power reduction (2005) (14)
A 1-V low-power high-performance 32-bit conditional sum adder (1994) (14)
Low-power register-exchange Viterbi decoder for high-speed wireless communications (2002) (14)
Statistical SRAM Read Access Yield Improvement Using Negative Capacitance Circuits (2013) (13)
Analytical Soft Error Models Accounting for Die-to-Die and Within-Die Variations in Sub-Threshold SRAM Cells (2011) (13)
A low-power 5 Mb/s turbo decoder for third-generation wireless terminals (2004) (13)
TRASIM: compact and efficient two-dimensional transient simulator for arbitrary planar semiconductor devices (1995) (13)
A New Loss Compensation Technique for CMOS Distributed Amplifiers (2009) (13)
Effect of technology scaling on digital CMOS logic styles (2000) (12)
Memoryless Viterbi decoder (2005) (12)
A contention-free domino logic for scaled-down CMOS technologies with ultra low threshold voltages (2000) (12)
Single-device-well MOSFET's (1981) (12)
Analysis of the Flash ADC Bandwidth–Accuracy Tradeoff in Deep-Submicron CMOS Technologies (2008) (12)
Novel low-voltage low-power full-swing BiCMOS circuits (1994) (12)
Impact of technology scaling on leakage reduction techniques (2007) (11)
Total Power Modeling in FPGAs Under Spatial Correlation (2009) (11)
ACE: A Hierarchical Graphical Interface for Architectural Synthesis (1989) (11)
Input Vector Reordering for Leakage Power Reduction in FPGAs (2008) (11)
Low-power multi-threshold MCML: Analysis, design, and variability (2006) (11)
Analog neural network building blocks based on current mode subthreshold operation (1993) (11)
Active-pull-down nonthreshold logic BiCMOS circuits for high-speed low-power applications (1995) (11)
Fuzzy Clustering Neural Network (FCNN): Competitive Learning and Parallel Architecture (1994) (10)
POMR: a power-aware interconnect optimization methodology (2005) (10)
Low-voltage scaled CMOS and BiCMOS digital circuits (1992) (10)
On the scaling of Si-MESFETs (1980) (10)
Nanosecond NMOS VLSI current mode logic (1982) (10)
Low-power design of high-capacitive CMOS circuits using a new charge sharing scheme (1999) (10)
Interconnection delays in MOSFET VLSI (1981) (10)
Low-Power VLSI Design (1997) (10)
Scaling of BiCMOS digital circuit structures (1989) (10)
Low power implementation of fast addition algorithms (1998) (9)
A fast learning technique for the multilayer perceptron (1990) (9)
Low power VLSI CMOS circuit design (2000) (9)
The Icewater Language and Interpreter (1984) (9)
Efficient gate clustering for MTCMOS circuits (2001) (9)
Effective capacitance macro-modelling for architectural-level power estimation (1998) (9)
SDW MOSFET static memory cell (1981) (9)
Differential PLL for wireless applications using differential CMOS LC-VCO and differential charge pump (1999) (8)
A Novel JCMOS Dynamic RAM Cell for VLSI Memories (1984) (8)
Circuit/architecture for low-power high-performance 32-bit adder (1995) (8)
Fractional-N frequency synthesizer for wireless communications (2002) (8)
Circuit techniques for high-speed and low-power multi-port SRAMs (1998) (8)
Integrated injection logic for a linear/digital LSI environment (1978) (8)
Analytical and numerical analyses of the delay time of BiCMOS structures (1992) (8)
Testing and design for testability of BiCMOS logic circuits (1992) (8)
A new efficient dynamic-iterative technique for turbo decoders (2002) (8)
Design and optimization of buffer chains and logic circuits in a BiCMOS environment (1992) (8)
A programmable power-efficient decimation filter for software radios (1997) (8)
A low-power CMOS frequency synthesizer design methodology for wireless applications (1999) (7)
Full-swing Schottky BiCMOS/BiNMOS and the effects of operating frequency and supply voltage scaling (1994) (7)
On the design of low power MCML based ring oscillators (2004) (7)
An all-N-logic high-speed single-phase dynamic CMOS logic (1994) (7)
LAP: a logic activity packing methodology for leakage power-tolerant FPGAs (2005) (7)
A fully-integrated low phase-noise nested-loop PLL for frequency synthesis (2000) (7)
Simulation of Temperature Dependence of Microwave Noise in Metal-Oxide-Semiconductor Field-Effect Transistors (2000) (7)
A novel single-device-well MOSFET gate (1979) (6)
Comparative analysis of process variation impact on flip-flops soft error rate (2009) (6)
A low power monolithic subsampled phase-locked loop architecture for wireless transceivers (1999) (6)
High-Performance Digital VLSI Circuit Design (2012) (6)
Split-Gate Logic circuits for multi-threshold technologies (2001) (6)
Analysis of load structures for current-mode logic (1975) (6)
Novel merged BiCMOS circuit structures (1990) (6)
Low-power implementation of discrete cosine transform (1996) (6)
Design of broadband bandpass CMOS amplifiers based on modified distributed amplification technique (2005) (6)
Highly testable design of BiCMOS logic circuits (1994) (6)
A Low-Power Multi-Pin Maze Routing Methodology (2007) (6)
A Power-Efficient Multipin ILP-Based Routing Technique (2010) (6)
An ultra-low-power CMOS on-chip interconnect architecture (1995) (6)
SC2L: a low-power high-performance dynamic differential logic family (1999) (5)
A training approach based on linear separability analysis for layered perceptrons (1994) (5)
Low-power design of finite field multipliers for wireless applications (1998) (5)
STAIC: a synthesis tool for CMOS and BiCMOS analog integrated circuits (1991) (5)
Nonsaturated integrated injection logic (1975) (5)
A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs (2007) (5)
Area-efficient CMOS distributed amplifier using compact CMOS interconnects (2006) (5)
High-level analog synthesis using signal flow graph transformations (1995) (5)
Differential BiCMOS logic circuits: fault characterization and design-for-testability (1995) (5)
BiCMOS at low supply voltage (1993) (5)
Phase-domain fractional-N frequency synthesizers (2004) (5)
TIME SERIES ANALYSIS FOR THE PREDICTION OF RC MATERIAL COMPONENTS PRICES IN EGYPT (2012) (5)
Mo1607 – Baseline Predictive Factors for Fore and Hind Gut Response to Long-Term Gi Electrical Stimulation (2019) (5)
Multidrain NMOS for VLSI logic design (1982) (5)
An Analytical Study of Improving Beam-Column Joints Behavior Under Earthquakes (2017) (5)
SDW MOSFETs in LSI analog circuit design (1982) (4)
Fuzzy clustering neural network system design and implementation (1994) (4)
A 16-bit high-speed low-power hybrid adder (2016) (4)
A Bias-Dependent Model for the Impact of Process Variations on the SRAM Soft Error Immunity (2011) (4)
Digital VLSI systems (1985) (4)
A new model for bipolar transistors at high current (1993) (4)
SPEEDING‐UP OF CONVERGENCE OF GUMMEL ITERATIONS FOR TRANSIENT SIMULATION (1993) (4)
Pipelined architecture for neural-network-based speech recognition (1994) (4)
Power dissipation in deep submicron CMOS digital circuits (1995) (4)
Power minimization of high-performance submicron CMOS circuits using a dual-V/sub dd/ dual-V/sub th/ (DVDV) approach (1999) (4)
Low-energy design of a 3G-compliant turbo decoder (2004) (4)
Delay optimization of CMOS logic circuits using closed-form expressions (1999) (4)
New Dynamic Logic and Memory Circuit Structures For BICMOS Technologies (1986) (4)
BiCMOS integrated circuit design : with analog, digital, and smart power applications (1994) (4)
Novel CMOS sampled-data VLSI implementation of artificial neural networks (1992) (4)
A design for-testability technique for shorts and bridging faults in BiCMOS logic families (1995) (4)
A novel loss compensation technique for broadband CMOS distributed amplifiers (2006) (4)
Digital MOS integrated circuits II : with applications to processors and memory design (1992) (4)
Towards connectionist production systems (1991) (4)
Post layout simulation of RF CMOS integrated circuits with passive components (2005) (4)
Design of an energy-efficient turbo decoder for 3/sup RD/ generation wireless applications (2003) (3)
An efficient and accurate model for RF/microwave spiral inductors using microstrip lines theory (2000) (3)
Low-Power VLSI Design: An Overview (1995) (3)
Low-Voltage Low-Power VLSI CMOS Circuit Design (1995) (3)
On the Power Management of Simultaneous Multithreading Processors (2010) (3)
Power-efficient multiplier-accumulator design for FIR filters (1997) (3)
Functional modeling of integrated injection logic—Transient analysis (1978) (3)
Decimation filters: low-power design and optimization (1997) (3)
A DOL CMOS static memory cell (1981) (3)
VLSI implementation of a modular ANN chip for character recognition (1993) (3)
A Fast Parametric Model for Contact-Substrate Coupling (1999) (3)
CAD for VLSI: Symple: a symbolic layout tool for bipolar and MOS VLSI (1988) (3)
A 3-10 GHz Low-Noise Amplifier for Ultra-Wideband Applications (2006) (3)
A novel multiple threshold MOSFET structure for A/D and D/A conversion (1984) (3)
Acute blue finger: a diagnostic challenge (2014) (3)
BiCMOS nonthreshold logic for high-speed low-power applications (1991) (3)
Mapping fuzzy clustering neural networks onto systolic arrays (1994) (3)
Two-Level Emitter-Function Logic Structures for Logic-in-Memory Computers (1975) (3)
A 10-GHz 15-dB Four-Stage Distributed Amplifier in 0.18μm CMOS Process (2006) (3)
Comparative analysis of power yield improvement under process variation of sub-threshold flip-flops (2010) (3)
Logic partition for multiemitter two-level structures (1974) (3)
Novel high speed low voltage circuit structures for BiCMOS SRAMs (1993) (3)
Bipolar structures for BIMOS technologies (1980) (3)
Lumped-element analysis and design of CMOS distributed amplifiers with image impedance termination (2006) (3)
A 0.5 /spl mu/m SiGe pre-equalizer for 10 Gb/s single-mode fiber optic links (2005) (3)
Vowel classification using a neural predictive HMM: a discriminative training approach (1994) (3)
Statistical timing yield improvement of dynamic circuits using negative capacitance technique (2010) (3)
A low-power high-performance embedded SRAM macrocell (1998) (3)
A low power algorithm for division in residue number system (RNS) (1998) (3)
A formulation for quick evaluation and optimization of digital CMOS circuits (1999) (3)
CMOS distributed amplifiers: an integrated solution for broadband optical and wireless communication applications (2005) (2)
Temperature-dependent characteristics of BiCMOS digital circuits (1993) (2)
Integrated injection logic for VLSI (1980) (2)
Delay optimization and energy estimation in CMOS differential cascade voltage switch logic circuits (2000) (2)
A Design Automation Environment for Mixed Analog/Digital ANNs (1994) (2)
A novel matrix-based lumped-element analysis method for CMOS distributed amplifiers (2004) (2)
A 4Gb/s 1:16 DEMUX using an all-static 0.18-/spl mu/m CMOS logic (2003) (2)
On the DC characteristics of MOS differential stages (1981) (2)
Analysis of latchup and parasitic effects in merged BiCMOS structures (1993) (2)
A leakage-aware CAD flow for MTCMOS FPGA architectures (abstract only) (2005) (2)
A novel low power low phase-noise PLL architecture for wireless transceivers (1999) (2)
Quadrature Direct Digital Frequency Synthesizer Using FPGA (2006) (2)
Low-power BiCMOS circuits for high-speed interchip communication (1997) (2)
Novel high speed circuit structures for BiCMOS environment (1995) (2)
The impact of timing yield improvement under process variation on flip-flops soft error rate (2009) (2)
Series-Gated CML and ECL Bipolar Circuits (1996) (2)
MTCMOS Combinational Circuits Using Sleep Transistors (2003) (2)
Logic Design Using EFL Structures (1976) (2)
Cost constrained optimal architectural synthesis (1991) (2)
A Compact VLSI Implementation of Neural Networks (1994) (2)
Low-Power CMOS Random Access Memory Circuits (1995) (2)
A semi-analytical quasi-static approach for substrate coupling modeling in VLSI circuits (2000) (2)
A 6-Bit 1.6-GS/<emphasis emphasistype="roman">s</emphasis> Low-Power Wideband Flash ADC Converter in 0.13-<formula formulatype="inline"><tex Notation="TeX">$\mu$</tex> </formula><emphasis emphasistype="roman">m</emphasis> CMOS Technology (2008) (2)
Schottky merged BiCMOS structures (1994) (2)
Design of CMOS distributed amplifiers for maximum bandwidth (2004) (2)
Pipelined Neural Network Architecture For Speech Recognition (1994) (2)
Methodology for generating behavioral specifications of analog hardware for artificial neural network implementations (1993) (2)
Estimation and optimization of delay in popular CMOS logic styles (2001) (2)
Response spectra for differential motion of structures supports during earthquakes in Egypt (2012) (2)
MMI training of minimum complexity adaptive nearest neighbor classifiers (1994) (2)
Minimum description length pruning and maximum mutual information training of adaptive probabilistic neural networks (1993) (2)
Integrated design and test synthesis (1988) (2)
Modular switched-resistor ANN chip for character recognition using novel parallel VLSI architecture (1993) (2)
Introduction to Integer Programming (1992) (2)
A termination technique for the averaging network of flash ADC's (2006) (2)
Analog-to-digital conversion for SONET OC-192 (2004) (2)
A methodology for substrate crosstalk evaluation for system-on-a-chip (2002) (2)
Summary and Future Research (1991) (2)
Design optimization of JCMOS structures (1987) (2)
Symbolic Layout for Bipolar and MOS VLSI (1987) (2)
Low power CMOS logic families (1998) (2)
Synthesis of Multiple Bus Architectures For DSP Applications (1994) (2)
Low-Power High-Performance Adders (1997) (2)
Modeling techniques for substrate coupling for system-on-a-chip (2001) (2)
The user interface and program structure of a graphical VLSI layout editor (1987) (1)
Negative capacitance circuits for process variations compensation and timing yield improvement (2013) (1)
Substrate-Coupling Noise Analysis of a Mixed-Signal RF IC Using an Efficient Technique for Substrate Parasitic Extraction (1)
A structure design approach using a priori knowledge for artificial neural networks (1997) (1)
COMPARISON OF COUPLED AND DECOUPLED METHODS FOR SEMICONDUCTOR DEVICE MODELING (1994) (1)
Leakage aware full adder cell (2007) (1)
Base component of gain and delay time in base-implanted bipolar transistors☆ (1981) (1)
A ROM based fractional-N frequency synthesizer for wireless communications (2002) (1)
Su1717 CHEMOKINE ELEVATION IN PATIENTS WITH THE SYMPTOMS OF GASTROPARESIS (2020) (1)
Ultra-Widband Distributed Amplifier Using Loss Compensation Technique on Both Input and Output Circuit (2004) (1)
Low-Power VLSI Design Methodology (1995) (1)
Structural Health Monitoring for Reinforced Concrete Containment Using Inner Electrical Resistivity Method (2021) (1)
A mixed-mode vlsi implementation of artificial neural networks for character recognition (1995) (1)
Leakage Power: Challenges and Solutions (2003) (1)
MTCMOS Dynamic Circuits (2003) (1)
BiCMOS active-pull-down non-threshold logic circuits for high-speed low-power applications (1994) (1)
A low–voltage energy scalable static differential logic (ES2DL) family (1999) (1)
Leakage control for large fan-in Domino gates using substrate biasing (2003) (1)
Load-line analysis of i.i.l. (1975) (1)
Low-power differential CML and ECL BiCMOS circuit techniques (1994) (1)
SC/sup 2/L; a low-power high-performance dynamic differential logic family (1999) (1)
Damage Identification in RC Beams Using Internal Electrical Resistivity Measurements (2012) (1)
Using internal electrical resistivity measurements as a tool for structural health monitoring (2012) (1)
Low-Voltage Device Modeling (1995) (1)
On the Fault Tolerance of Stochastic Decoders (2017) (1)
Bipolar structures for BIMOS VLSI (1978) (1)
Low-power radix 2 division algorithm with minimum add/sub operations (1996) (1)
Mapping neural networks onto systolic arrays (1996) (1)
A pipelined VLSI arithmetic architecture (1992) (1)
Digital compressor structure in neural network implementation using complex complementary pass-transistor logic (C/sup 2/PL) (1994) (1)
Energy saving and environment protection solution for the submarine pipelines based on deep learning technology (2022) (1)
Scaling merged single-device-well MOSFETs for very large scale integration (1981) (1)
A low–voltage energy scalable static differential logic (ES 2 DL) family (1999) (1)
Minimum Complexity Neural Networks for Classification (1994) (1)
Multiemitter BiCMOS CML circuits (1992) (1)
Optimization of digital BiCMOS circuits, an overview (1992) (1)
State of the Art Synthesis (1992) (1)
A VLSI neural network design approach using a priori knowledge (1992) (1)
A Digital Perceptron Learning Implementation with Look-up Table Feedback Layer (1996) (0)
On the Power Management of (2010) (0)
POMR: a power-optimal maze routing methodology (2004) (0)
CMOS High-Performance Circuits (1996) (0)
MOS Digital Integrated Circuits (1993) (0)
Embedded MTCMOS Combinational Circuits (2003) (0)
Parametric Frequency Domain Identification Using Variable Stiffness and Damping Device [Final Report] (2003) (0)
An efficient technique for substrate coupling parasitic extraction with application to RF/microwave spiral inductors (2000) (0)
A Teaching Assistant for Microelectronic Circuits Problems (2021) (0)
Stacked I/sup 2/L structures (1980) (0)
Asynchronous Circuits 1 Motivations for Asynchronous Circuits (2007) (0)
A Low-Voltage High-Performance Differential Static Logic (LVDSL) family (1999) (0)
The Catree Architectural Synthesis with Testability (1991) (0)
Fully integrated low phase-noise PLLs using closed-loop voltage-to-frequency converter architectures (1999) (0)
PROJECT Project 0110 PARAMETRIC FREQUENCY DOMAIN IDENTIFICATION USING VARIABLE STIFFNESS AND DAMPING DEVICES FINAL REPORT (2004) (0)
A NON-DESTRUCTIVE TEST FOR THE EVALUATION OF THE INTEGRITY OF PIERS DURING CONSTRUCION (2006) (0)
Behavioral and Structural Interfaces (1992) (0)
An All-Digital VLSI ANN (1994) (0)
High-Performance CML, ECL and NTL Bicmos Circuits (1996) (0)
Low-Power High-Performance Multipliers (1997) (0)
AGAM: automatic generation of asynchronous machines (1991) (0)
Low-Power Embedded BiCMOS/ECL SRAMS (1997) (0)
A Pipelined ANN Architecture for Speech Recognition (1994) (0)
Inter-Chip Low-Voltage-Swing Transceivers (1997) (0)
The effect of dispersion on the bandwidth of distributed amplifier (2003) (0)
BiCMOS Digital Integrated Circuits (1993) (0)
BiCMOS On-Chip Drivers (1997) (0)
Logic and circuit design of high speed digital systems. (1970) (0)
High-Performance System Applications (1996) (0)
High-Performance Bicmos Circuit Structures (1996) (0)
A Parallel ANN Architecture for Fuzzy Clustering (1994) (0)
Bipolar CML Integrated Circuits (1993) (0)
Low-power subband coding algorithm (1996) (0)
A clustering algorithm for circuit partitioning (1997) (0)
Application of integer linear programming in the design of decimation filters for multi-standard transceivers (2004) (0)
Frequency SynthesizerUsing FPGA (2006) (0)
Low power high speed analog-to-digital converter for wireless communications (2000) (0)
Functional modelling of floating substrate MOS structures (1977) (0)
A TWO-LEVEL HIERARCHICAL MOBILE NETWORK: STRUCTURE AND NETWORK CONTROL (1996) (0)
Testability In Architectural Synthesis (1991) (0)
Corrections to "On the scaling of Si-MESFETs" (1981) (0)
Semi-deterministic fault-independent test generation and its impact on ATPG performance (1994) (0)
Transient Phenomena in High Speed Bipolar Devices (1998) (0)
Low-Power Circuit Techniques for High-Speed ECL SRAMs (1995) (0)
An Improved Programmable Neural Network and VLSI Architecture Using BiCMOS Building Blocks (2021) (0)
3D Double-Lambda-Diode VLSI SRAM Cells (1988) (0)
BiCMOS Digital Circuit Applications (1993) (0)
Low-Power Register File (1997) (0)
A Sampled-Data CMOS VLSI Implementation of a Multi-Character ANN Recognition System (1994) (0)
A Neural Predictive Hidden Markov Model Architecture for Speech and Speaker Recognition (1994) (0)
Low-Voltage VLSI BiCMOS Circuit Design (1995) (0)
Support for Algorithmic Constructs (1992) (0)
A Low-Power High-Performance Current-Mode (2001) (0)
High-speed dynamic reference voltage (DRV) CMOS/ECL interface circuits (1994) (0)
Distributed Current Mode Logic (2006) (0)
An experimental low-power CMOS pipeline ADC using feedforward sample-and-hold amplifier (1998) (0)
A novel parallel architecture for a switched-capacitor bandpass sigma-delta modulator (1997) (0)
Nonsaturated Integrated Injection Logic in Circuit Design (1975) (0)
A Termination Technique forTheAveraging Network ofFlash ADC's (2006) (0)
Simultaneous Scheduling, and Selection and Allocation of Functional Units (1992) (0)
A CMOS time-multiplexed digital filter for vocoder applications (1982) (0)
MTCMOS Sequential Circuits (2003) (0)
Retrofitting Gravity Load Designed R.C Frames Using FRP (2018) (0)
MTCMOS Current-Steering Circuits (2003) (0)
MAPPING HAZARD POTENTIALS IN SEISMIC ZONES BASED ON GEOTECHNICAL DATA FOR DESIGNING TRANSPORTATION NETWORKS INFRASTRUCTURE (2015) (0)
Studying the Impact foundations on the Seismic Resp (2014) (0)
Sa401 BASELINE FACTORS COMBINED WITH TEMPORARY TRIAL CAN PREDICT LONG TERM OUTCOME WITH GASTRIC ELECTRICAL STIMULATION (2021) (0)
Interdigitated I/sup 2/L structures (1978) (0)
ANALYSIS OF RC CONTAINMENTS OF NUCLEAR PLANTS UNDER AEROPLANE IMPACT LOADS (2020) (0)
Oasic Synthesis Results (1991) (0)
A parallel digital layered perceptrons implementation (1996) (0)
A CMOS pipelined single channel digital echo canceller (1981) (0)
A systematic approach for design of broadband CMOS amplifiers (2005) (0)
Modelling a 1.25 Gb/s optical transmitter in IEEE 1076.1 standard VHDL-AMS (2003) (0)
A programmable neural network architecture using BiCMOS technology (1995) (0)
A linear phase distributed amplifier for wide band optical transceiver using transversal filter concept (2004) (0)
A CML Propagation Delay Model (1996) (0)
BiCMOS at Low Supply Voltage (Invited Tutorial) (1993) (0)
A novel inductor-free broadband cmos amplification technique (2005) (0)
Effect of Impact Boeing 707-320 on External RC Containment of Nuclear Power Plant for Different Compressive Strength of Concrete (2021) (0)
Design for Yield and Reliability for Nanometer CMOS Digital Circuits (2014) (0)
Global VLSI Design Cycle (1992) (0)
The effect of collector location on βuof I2L structures (1977) (0)
Low-Voltage Process Technology (1995) (0)
Device Design Considerations (1993) (0)
WATPC: A Computer-Aided Design Package for Digital Bipolar Integrated Circuits (1982) (0)
A fully integrated 3.3-V, 325-MHz, /spl plusmn/95-ps jitter CMOS PLL (2002) (0)
Stability of Concrete Containments of Nuclear Plants Under Jet Impact Loads (2018) (0)
A modular design approach to large-scale-integration of high-speed digital systems. (1974) (0)
Oasic: Area-Delay Constrained Architectural Synthesis (1992) (0)
A 20-Stage CMOS Distributed Amplifier using CMOS Interconnects for Artificial Transmission Lines (2006) (0)
A Methodology for Architectural Synthesis (1992) (0)
Simulation of internal distribution of microwave noise sources in a short-channel nMOSFET (2000) (0)
Potential Risks of Using Disconnected Composite Foundation Systems in Active Seismic Zones (2018) (0)
VLSI CMOS Subsystem Design (1995) (0)
On the Power Management of (2010) (0)

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