Nagarajan Ranganathan

Nagarajan Ranganathan's AcademicInfluence.com Rankings

Computer Science

#4743

World Rank

#5008

Historical Rank

Computer Engineering

#113

World Rank

#114

Historical Rank

Database

#7788

World Rank

#8100

Historical Rank

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Computer Science

Why Is Nagarajan Ranganathan Influential?

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According to Wikipedia, Nagarajan Ranganathan was a Distinguished University Professor of Computer Science and Engineering at the University of South Florida, Tampa, United States. He was elected as a Fellow of IEEE in 2002 for his contributions to algorithms and architectures for VLSI systems. He was elected Fellow of AAAS in 2012. He served as the Editor-in-Chief of IEEE Transactions on VLSI Systems.

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Nagarajan Ranganathan's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Gabor filter-based edge detection (1992) (372)
Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs (2010) (248)
LECTOR: a technique for leakage reduction in CMOS circuits (2004) (224)
Reversible Logic-Based Concurrently Testable Latches for Molecular QCA (2010) (174)
Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate (2009) (169)
JAGUAR: a fully pipelined VLSI architecture for JPEG image compression standard (1995) (128)
Design of a Reversible ALU Based on Novel Programmable Reversible Logic Gate Structures (2011) (125)
Design of Testable Reversible Sequential Circuits (2013) (122)
Corner detection (1990) (113)
Design of efficient reversible logic-based binary and BCD adder circuits (2013) (87)
Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition (2006) (86)
High-speed VLSI designs for Lempel-Ziv-based data compression (1993) (86)
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits (2008) (86)
Efficient VLSI designs for data transformation of tree-based codes (1991) (84)
A new reversible design of BCD adder (2011) (83)
A new design of the reversible subtractor circuit (2011) (81)
VLSI architecture and chip for combined invisible robust and fragile watermarking (2007) (79)
Mach-Zehnder interferometer based design of all optical reversible binary adder (2012) (79)
Design of a comparator tree based on reversible logic (2010) (72)
A dual voltage-frequency VLSI chip for image watermarking in DCT domain (2006) (71)
Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs (2010) (66)
IDUTC: an intelligent decision-making system for urban traffic-control applications (2001) (59)
Switching activity estimation of VLSI circuits using Bayesian networks (2003) (59)
Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing Ancilla and Garbage Bits (2014) (57)
Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits (2009) (52)
Design of a reversible single precision floating point multiplier based on operand decomposition (2010) (51)
Design of static and dynamic RAM arrays using a novel reversible logic gate and decoder (2011) (50)
VLSI implementation of visible watermarking for secure digital still camera design (2004) (49)
Design of a reversible bidirectional barrel shifter (2011) (47)
A VLSI Architecture and Algorithm for Lucas–Kanade-Based Optical Flow Computation (2010) (47)
Mach-Zehnder Interferometer Based All Optical Reversible NOR Gates (2012) (45)
MARVLE: a VLSI chip for data compression using tree-based codes (1993) (44)
A VLSI architecture for visible watermarking in a secure still digital camera (S/sup 2/DC) design (Corrected)* (2005) (39)
CASM: A VLSI Chip for Approximate String Matching (1995) (39)
Design of a reversible floating-point adder architecture (2011) (39)
Simultaneous peak and average power minimization during datapath scheduling (2003) (39)
Design of A ternary barrel shifter using multiple-valued reversible logic (2010) (38)
A VLSI Architecture for Visible Watermarking in a Secure Still Digital Camera ( S 2 DC ) Design (2005) (37)
Design of a novel reversible ALU using an enhanced carry look- ahead adder (2011) (36)
Simultaneous interconnect delay and crosstalk noise optimization through gate sizing using game theory (2006) (35)
Testable Reversible Latches for Molecular QCA (2008) (35)
Synthesis of Dual-Rail Adiabatic Logic for Low Power Security Applications (2014) (34)
A high speed systolic architecture for labeling connected components in an image (1991) (34)
Control and data flow graph extraction for high-level synthesis (2004) (34)
SIGMA: a VLSI systolic array implementation of a Galois field GF(2 m) based multiplication and division algorithm (1993) (34)
An intelligent system for failure detection and control in an autonomous underwater vehicle (2001) (33)
Dependency preserving probabilistic modeling of switching activity using Bayesian networks (2001) (32)
A framework for energy and transient power reduction during behavioral synthesis (2003) (32)
Peak power minimization through datapath scheduling (2003) (32)
A new technique for leakage reduction in CMOS circuits using self-controlled stacked transistors (2004) (30)
A game theoretic approach for power optimization during behavioral synthesis (2003) (29)
Efficient computation of gabor filter based multiresolution responses (1994) (29)
Design and analysis of a novel reversible encoder/decoder (2011) (28)
A Game Theoretic Approach for Simultaneous Compaction and Equipartitioning of Spatial Data Sets (2010) (28)
A Framework for Correction of Multi-Bit Soft Errors in L2 Caches Based on Redundancy (2009) (27)
Design of a Tree-Based Comparator and Memory Unit Based on a Novel Reversible Logic Structure (2012) (26)
A linear programming formulation for security-aware gate sizing (2008) (26)
Reversible logic based multiplication computing unit using binary tree data structure (2015) (25)
Energy-efficient datapath scheduling using multiple voltages and dynamic clocking (2005) (25)
Gate sizing and buffer insertion using economic models for power optimization (2004) (24)
Design of a Moore finite state machine using a novel reversible logic gate, decoder and synchronous up-counter (2011) (24)
Cascaded Bayesian inferencing for switching activity estimation with correlated inputs (2004) (24)
Edge detection models based on Gabor filters (1992) (24)
ILP models for energy and transient power minimization during behavioral synthesis (2004) (24)
Estimation of switching activity in sequential circuits using dynamic Bayesian networks (2005) (24)
Reversible logic based concurrent error detection methodology for emerging nanocircuits (2010) (23)
Least-square estimation of average power in digital CMOS circuits (2002) (22)
Adaptive VBR video traffic management for higher utilization of ATM networks (1998) (22)
Multiple cost optimization for task assignment in heterogeneous computing systems using learning automata (1999) (21)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2018) (21)
Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies (2012) (20)
Multievent Crisis Management Using Noncooperative Multistep Games (2007) (20)
Petri net modeling of gate and interconnect delays for power estimation (2002) (20)
A linear time algorithm for wire sizing with simultaneous optimization of interconnect delay and crosstalk noise (2006) (19)
Energy efficient scheduling for datapath synthesis (2003) (19)
A Clock Control Strategy for Peak Power and RMS Current Reduction Using Path Clustering (2013) (18)
An efficient and accurate logarithmic multiplier based on operand decomposition (2006) (18)
A VLSI architecture for watermarking in a secure still digital camera (S/sup 2/DC) design (2005) (16)
An Automated Decision Support System Based on Game Theoretic Optimization for Emergency Management in Urban Environments (2007) (16)
A parallel architecture for data compression (1990) (15)
A VLSI architecture for computing scale space (1988) (15)
A novel optimization method for reversible logic circuit minimization (2013) (15)
Efficient reversible NOR gates and their mapping in optical computing domain (2014) (14)
Concurrently testable FPGA design for molecular QCA using conservative reversible logic gate (2009) (14)
RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits (2009) (14)
A VLSI architecture for dynamic scene analysis (1991) (14)
A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing (2008) (13)
Reversible Logic Based Design and Test of Field Coupled Nanocomputing Circuits (2014) (13)
ILP models for simultaneous energy and transient power minimization during behavioral synthesis (2006) (13)
Design of Adiabatic Dynamic Differential Logic for DPA-Resistant Secure Integrated Circuits (2015) (13)
Behavioral model of integrated qubit gates for quantum reversible logic design (2013) (12)
Utilization of cache area in on-chip multiprocessor (1999) (12)
Post-layout gate sizing for interconnect delay and crosstalk noise optimization (2006) (12)
A Novel Approach for Variation Aware Power Minimization during Gate Sizing (2006) (11)
A game-theoretic approach for binding in behavioral synthesis (2003) (11)
A nonlinear programming based power optimization methodology for gate sizing and voltage selection (2005) (11)
Design of a low power image watermarking encoder using dual voltage and frequency (2005) (11)
A systolic array for approximate string matching (1993) (11)
VLSI Architectures for Pattern Matching (1994) (11)
Multiterminal net routing for partial crossbar-based multi-FPGA systems (2003) (11)
Multi-terminal net routing for partial crossbar-based multi-FPGA systems (1999) (11)
A low power scheduler using game theory (2003) (11)
A scene-based generalized Markov chain model for VBR video traffic (1998) (11)
CHESS: a comprehensive tool for CDFG extraction and synthesis of low power designs from VHDL (2006) (10)
Average power in digital CMOS circuits using least square estimation (2001) (10)
An ILP-based scheduling scheme for energy efficient high performance datapath synthesis (2003) (10)
Social Fairness in Multi-Emergency Resource Management (2006) (10)
A framework for energy and transient power reduction during behavioral synthesis (2004) (9)
C/sup 3/L: a chip for connected component labeling (1997) (9)
SYSTOLIC ARCHITECTURES FOR PARTIAL POLYGON RECOGNITION (1993) (9)
Forward Body Biased Adiabatic Logic for Peak and Average Power Reduction in 22nm CMOS (2014) (9)
Improving the reliability of on-chip L2 cache using redundancy (2007) (9)
Performance Analysis of the Bidirectional Ring-Based Multiprocessor (1997) (9)
A VLSI chip for computing the medial axis transform of an image (1995) (8)
A learning automata based framework for task assignment in heterogeneous computing systems (1999) (8)
A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks (2004) (8)
Modeling switching activity using cascaded Bayesian networks for correlated input streams (2002) (8)
Dynamic clock stretching for variation compensation in VLSI circuit design (2012) (8)
VLSI & parallel computing for pattern recognition & artificial intelligence (1995) (8)
A new CRL gate as super class of Fredkin gate to design reversible quantum circuits (2013) (8)
Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power (2008) (8)
Effect of message length and processor speed on the performance of the bidirectional ring-based multiprocessor (1997) (8)
A systolic algorithm and architecture for image thinning (1995) (8)
Statistical Gate Sizing for Yield Enhancement at Post Layout Level (2007) (8)
CREAM: combined register and module assignment with floorplanning for low power datapath synthesis (2000) (8)
VLSI and Parallel Computing for Pattern Recognition and Artificial Intelligence (1995) (7)
Enhancing arithmetic and tree-based coding (1989) (7)
A strategy for soft error reduction in multi core designs (2009) (7)
ACE: a VLSI chip for Galois field GF(2/sup m/) based exponentiation (1994) (7)
Switching activity estimation of large circuits using multiple Bayesian networks (2002) (7)
Variation Aware Timing Based Placement Using Fuzzy Programming (2007) (7)
Routing on switch matrix multi-FPGA systems (2000) (7)
SMAC: A VLSI Architecture for Scene Matching (1998) (7)
Routing on field-programmable switch matrices (2003) (7)
Tutorial T2: Reversible Logic: Fundamentals and Applications in Ultra-Low Power, Fault Testing and Emerging Nanotechnologies, and Challenges in Future (2012) (6)
A Two-dimensional Systolic Array Processor for Image Processing (1992) (6)
An intelligent system architecture for urban traffic control applications (1996) (6)
A New Placement Algorithm for Reduction of Soft Errors in Macrocell Based Design of Nanometer Circuits (2009) (6)
A comparative study of bidirectional ring and crossbar interconnection networks (2002) (6)
Power estimation of sequential circuits using hierarchical colored hardware Petri net modeling (2002) (6)
A prototype VLSI chip architecture for JPEG image compression (1995) (6)
A VLSI ATM switch architecture for VBR traffic (1998) (6)
A Cache Coherence Protocol for the Bidirectional Ring Based Multiprocessor (2003) (6)
JAGUAR: a high speed VLSI chip for JPEG image compression standard (1995) (6)
An efficient VLSI architecture for template matching based on moment preserving pattern matching (1994) (6)
A flexible MPEG audio decoder layer III chip architecture (1998) (6)
A VLSI hardware accelerator for dynamic time warping (1992) (6)
A VLSI chip for template matching (1994) (5)
A Utilitarian Approach to Variation Aware Delay, Power, and Crosstalk Noise Optimization (2011) (5)
Placement for Immunity of Transient Faults in Cell-Based Design of Nanometer Circuits (2011) (5)
A real delay switching activity simulator based on Petri net modeling (2002) (5)
Systolic algorithms for tree pattern matching (1995) (5)
A systolic algorithm and architecture for Galois field arithmetic (1992) (5)
A tree matching chip (1996) (5)
Power Reduction Fundamentals (2008) (5)
A microeconomic approach to multi-robot team formation (2007) (5)
Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty (2008) (5)
A microeconomic model for simultaneous gate sizing and voltage scaling for power optimization (2003) (5)
Power fluctuation minimization during behavioral synthesis using ILP-based datapath scheduling (2003) (5)
LECTOR: A Technique for Leakage Reduction (2004) (4)
Vlsi Algorithms and Architectures (1993) (4)
Analysis of Reversible Logic Based Sequential Computing Structures Using Quantum Mechanics Principles (2012) (4)
A high speed VLSI chip for data compression (1991) (4)
VLSI Algorithms and Architectures: Fundamentals (1993) (4)
A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variations (2009) (4)
Hardware Algorithms for Polygon Matching (1993) (4)
Transient power minimization through datapath scheduling in multiple supply voltage environment (2003) (4)
VLSI Architectures for High-Speed Range Estimation (1995) (4)
Design partitioning on single-chip emulation systems (2000) (4)
PANTHER: a parallel neuro-systolic architecture for real-time processing (1996) (4)
GTFUZZ: A novel algorithm for robust dynamic power optimization via gate sizing with fuzzy games (2015) (4)
A VLSI Architecture for Approximate Tree Matching (1998) (4)
A VLSI architecture for computing the tree-to-tree distance (1995) (3)
A VLSI system architecture for real-time intelligent decision making (1996) (3)
A VLSI architecture for computing the optimal correspondence of string subsequences (1997) (3)
A scheme for data compression in supercomputers (1988) (3)
Timing-Based Placement Considering Uncertainty Due to Process Variations (2010) (3)
A systolic chip for LZ based data compression (1991) (3)
SAP: design of a systolic array processor for computation in vision (1990) (3)
SIGMA: A VLSI Chip for Galois Field GF(2m) Based Multiplication and Division (1993) (3)
PMAC: A Polygon Matching Chip (1995) (3)
MARVLE: a VLSI chip for variable length encoding and decoding (1992) (3)
A VLSI architecture for object recognition using tree matching (2002) (3)
An adaptive scheme for better utilization with QoS constraints for VBR video traffic in ATM networks (1998) (3)
Game theoretic modeling of voltage and frequency scaling during behavioral synthesis (2004) (3)
SMAC: A scene matching chip (1993) (3)
Guest editorial - Design methodologies for nanoelectronic digital and analogue circuits (2013) (3)
An expected-utility based approach to variation aware VLSI optimization under scarce information (2008) (3)
A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing (2008) (3)
High-Level Synthesis Fundamentals (2008) (3)
A microeconomic approach to multi-objective spatial clustering (2008) (2)
A Variation Aware Circuit Design Using Dynamic Clock Stretching (2010) (2)
Mapping and parallel implementation of Bayesian belief networks (1996) (2)
An Efficient VLSI Architecture for Template Matching (1994) (2)
Design and optimization of the VLSI architecture for discrete cosine transform used in image compression (1996) (2)
SIBA: a VLSI systolic array chip for image processing (1992) (2)
A VLSI system architecture for optical flow computation (2009) (2)
A suggestion for performance improvement in a relational database machine (1991) (2)
A VLSI architecture for a half-edge-based corner detector (1991) (2)
VLSI algorithms and architectures, Advanced concepts (1993) (2)
New cost metrics for iterative task assignment algorithms in heterogeneous computing systems (2000) (2)
Hardware Implementation of Data Compression (2003) (2)
Effect of data compression hardware on the performance of a relational database machine (1990) (2)
Task assignment and scheduling algorithms for heterogeneous computing systems (2000) (1)
Editorial the responsibility of reviewers (2004) (1)
VLSI algorithms for data compression (1991) (1)
VLSI architectures for polygon recognition (1993) (1)
Transactions on Computational Science XXIV (2014) (1)
Design of Reversible Adder-Subtractor and its Mapping in Optical Computing Domain (2014) (1)
Design and performance evaluation of the bidirectional ring-based shared memory multiprocessor (1999) (1)
Leakage Power Reduction (2008) (1)
Another Step in the Right Direction for TVLSI (2004) (1)
New methods for dynamic power estimation and optimization in vlsi circuits (2003) (1)
On software and hardware techniques of data engineering (1989) (1)
Systolic VLSI implementations of a Galois field arithmetic algorithms (1993) (1)
A CMOS VLSI Chip for Motion Detection (1992) (1)
Foreword for March 1996 issue (1996) (1)
A simple adaptive wormhole routing algorithm for MIMD systems (1998) (1)
A VLSI SYSTEM FOR INTELLIGENT DECISION MAKING IN REAL-TIME (2002) (1)
Editorial Appointments for 2005–2006 Term (2005) (1)
A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems (2001) (1)
VLSI architectures for depth estimation using intensity gradient analysis (1993) (1)
Proceedings : IEEE Computer Society Annual Symposium on VLSI : new frontiers in VLSI design : 11-12 May 2005, Tampa, Florida (2005) (1)
A parallel algorithm for 3D point pattern matching (1991) (1)
Efficient transportation of vbr video traffic in atm networks (1998) (1)
A Forum for VLSI Practitioners (1998) (0)
Power Modeling and Estimation at Transistor and Logic Gate Levels (2008) (0)
~go~it~~§ For Tree Pattern (1995) (0)
Variation-aware multimetric optimization during gate sizing (2009) (0)
A VLSI system for difference picture-based motion analysis (1989) (0)
VLSI Design 2006 Conference Awards (2006) (0)
Energy or Average Power Reduction (2008) (0)
A game theoretic framework for interconnect optimization in deep submicron and nanometer design (2006) (0)
A Cache Coherence Protocol for the BidirectionalRing Based MultiprocessorHitoshi OiDept (1999) (0)
A linear systolic algorithm and architecture for convex bipartite matching (1996) (0)
Session details: Session 5B: VLSI Design (2008) (0)
Reversible logic based multiplication computing unit using binary tree data structure (2015) (0)
Integrated Gate and Wire Sizing at Post Layout Level (2007) (0)
A Reflection on the TVLSI Editorial Process and the Announcement of a New Editor-In-Chief (2007) (0)
Editorial: new members of the TVLSI editorial board (2006) (0)
Structure de circuit vlsi pour la mise en application du standard de compression d'images jpeg (1995) (0)
Transient Power Reduction (2008) (0)
"High Speed Optoelectronic Receivers in Si-Ge" (2004) (0)
A VLSI systolic array processor chip for computing joins in a relational database (1992) (0)
Conclusions and Future Direction (2008) (0)
Architectural Power Modeling and Estimation (2008) (0)
Peak Power Reduction (2008) (0)
ANovelApproach forVariation Aware PowerMinimization during GateSizing (2006) (0)
A parallel algorithm and architecture for object recognition in images (2003) (0)
Design of a systolic VLSI chip for computing scale space (1992) (0)
A CacheCoherenceProtocol for the Bidir ectionalRing BasedMultipr ocessor (2003) (0)
FPGA Synthesis and CAD for Reconfigurable Systems (2009) (0)
Design of Efficient Reversible Multiply Accumulate (MAC) Unit (2015) (0)
Proceedings : IEEE Computer Society Annual Symposium on VLSI : new trends and technologies for VLSI systems design : ISVLSI 2003, 20-21 February 2003, Tempa, Florida (2003) (0)
Workshop on traffic management - IX Asian Games, New Delhi, February 15, 1982. (1982) (0)

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Published Works

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What Schools Are Affiliated With Nagarajan Ranganathan?

Nagarajan Ranganathan's AcademicInfluence.com Rankings