Narayanan Vijaykrishnan

Narayanan Vijaykrishnan's AcademicInfluence.com Rankings

Engineering

#5452

World Rank

#6711

Historical Rank

Electrical Engineering

#1517

World Rank

#1611

Historical Rank

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Engineering

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Narayanan Vijaykrishnan's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Leakage Current: Moore's Law Meets Static Power (2003) (1259)
The design and use of simplePower: a cycle-accurate energy estimation tool (2000) (517)
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory (2006) (415)
Analysis of error recovery schemes for networks on chips (2005) (352)
Energy-driven integrated hardware-software optimizations using SimplePower (2000) (341)
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers (2006) (330)
A novel dimensionally-decomposed router for on-chip communication in 3D architectures (2007) (279)
Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs (2012) (274)
Dynamic management of scratch-pad memory space (2001) (272)
A low latency router supporting adaptivity for on-chip interconnects (2005) (264)
Exploring Fault-Tolerant Network-on-Chip Architectures (2006) (247)
Using complete machine simulation for software power estimation: the SoftWatt approach (2002) (234)
A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks (2006) (232)
Fault tolerant algorithms for network-on-chip interconnect (2004) (230)
MIRA: A Multi-layered On-Chip Interconnect Router Architecture (2008) (219)
Influence of compiler optimizations on system power (2000) (219)
Architecture exploration for ambient energy harvesting nonvolatile processors (2015) (211)
On the Detection of Clones in Sensor Networks Using Random Key Predistribution (2007) (203)
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs (2009) (202)
Interconnect and thermal-aware floorplanning for 3D microprocessors (2006) (192)
DRAM energy management using software and hardware directed power mode control (2001) (190)
Studying energy trade offs in offloading computation/compilation in Java-enabled mobile devices (2004) (161)
Reliability concerns in embedded system designs (2006) (155)
Scheduler-based DRAM energy management (2002) (148)
Tunnel FET technology: A reliability perspective (2014) (147)
Reducing leakage energy in FPGAs using region-constrained placement (2004) (142)
Power attack resistant cryptosystem design: a dynamic voltage and frequency switching approach (2005) (137)
Soft error and energy consumption interactions: a data cache perspective (2004) (135)
Evaluating run-time techniques for leakage power reduction (2002) (129)
A case for heterogeneous on-chip interconnects for CMPs (2011) (128)
The Sleep Deprivation Attack in Sensor Networks: Analysis and Methods of Defense (2006) (125)
SEAT-LA: a soft error analysis tool for combinational logic (2006) (122)
Design and analysis of an NoC architecture from performance, reliability and energy perspective (2005) (120)
Hardware and Software Techniques for Controlling DRAM Power Modes (2001) (119)
A case for dynamic frequency tuning in on-chip networks (2009) (119)
Thermal-aware floorplanning using genetic algorithms (2005) (118)
Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design (2011) (114)
Three-dimensional cache design exploration using 3DCacti (2005) (106)
A Dual-VDD Low Power FPGA Architecture (2004) (105)
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs (2011) (103)
Energy optimization techniques in cluster interconnects (2003) (99)
Leakage energy management in cache hierarchies (2002) (98)
Embedded hardware face detection (2004) (98)
Thermal-aware IP virtualization and placement for networks-on-chip architecture (2004) (97)
Thermal-aware task allocation and scheduling for embedded systems (2005) (97)
Energy-conscious compilation based on voltage scaling (2002) (95)
A hybrid SoC interconnect with dynamic TDMA-based transaction-less buses and on-chip networks (2006) (94)
A novel Si-Tunnel FET based SRAM design for ultra low-power 0.3V VDD applications (2010) (94)
A clock power model to evaluate impact of architectural and technology optimizations (2002) (91)
Performance and power optimization through data compression in Network-on-Chip architectures (2008) (91)
Compiler-directed instruction cache leakage optimization (2002) (89)
Reliability-aware Co-synthesis for Embedded Systems (2004) (89)
Thermally Robust Clocking Schemes for 3D Integrated Circuits (2007) (87)
Toward Increasing FPGA Lifetime (2008) (85)
Design Space Exploration for 3-D Cache (2008) (84)
Nonvolatile memory design based on ferroelectric FETs (2016) (84)
A power estimation methodology for systemC transaction level models (2005) (84)
Masking the Energy Behavior of DES Encryption (2003) (84)
Java Runtime Systems: Characterization and Architectural Implications (2001) (79)
A compiler-based approach for dynamically managing scratch-pad memories in embedded systems (2004) (78)
A parallel architecture for hardware face detection (2006) (78)
Assessing Carbon Nanotube Bundle Interconnect for Future FPGA Architectures (2007) (77)
Soft errors issues in low-power caches (2005) (75)
Thermal trends in emerging technologies (2006) (75)
Improving soft-error tolerance of FPGA configuration bits (2004) (74)
Variation-aware task allocation and scheduling for MPSoC (2007) (74)
An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores (2011) (72)
Exploiting VLIW schedule slacks for dynamic and leakage energy reduction (2001) (72)
Priority Scheduling in Digital Microfluidics-Based Biochips (2006) (69)
Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects (2007) (68)
Compiler-directed instruction duplication for soft error detection (2005) (68)
Steep switching tunnel FET: A promise to extend the energy efficient roadmap for post-CMOS digital and analog/RF applications (2013) (67)
Interplay of energy and performance for disk arrays running transaction processing workloads (2003) (67)
Tunnel FET RF Rectifier Design for Energy Harvesting Applications (2014) (67)
Heap compression for memory-constrained Java environments (2003) (67)
Architectural issues in Java runtime systems (2000) (66)
vEC: virtual energy counters (2001) (66)
A low-power phase change memory based hybrid cache architecture (2008) (65)
Network-on-Chip Architectures - A Holistic Design Exploration (2009) (64)
FLAW: FPGA lifetime awareness (2006) (64)
Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors (2011) (64)
Adaptive error protection for energy efficiency (2003) (64)
Energy-oriented compiler optimizations for partitioned memory architectures (2000) (63)
Accurate stacking effect macro-modeling of leakage power in sub-100 nm circuits (2005) (63)
Power and performance analysis of motion estimation based on hardware and software realizations (2005) (62)
On the Effects of Process Variation in Network-on-Chip Architectures (2010) (60)
Impact of scaling on the effectiveness of dynamic power reduction schemes (2002) (59)
Characterization and modeling of run-time techniques for leakage power reduction (2004) (59)
A crosstalk aware interconnect with variable cycle transmission (2004) (59)
Using complete system simulation to characterize SPECjvm98 benchmarks (2000) (58)
Nonvolatile Processor Architecture Exploration for Energy-Harvesting Applications (2015) (56)
Analyzing soft errors in leakage optimized SRAM design (2003) (56)
Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues (2008) (55)
Tuning garbage collection in an embedded Java environment (2002) (55)
The effect of threshold voltages on the soft error rate [memory and logic circuits] (2004) (54)
Architecting Microprocessor Components in 3D Design Space (2007) (54)
Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits (2009) (54)
A Hardware Efficient Support Vector Machine Architecture for FPGA (2008) (52)
Variation Impact on SER of Combinational Circuits (2007) (52)
Temperature-aware voltage islands architecting in system-on-chip design (2005) (52)
Compiler support for reducing leakage energy consumption (2003) (52)
Incidental Computing on IoT Nonvolatile Processors (2017) (51)
Analysis of soft error rate in flip-flops and scannable latches (2003) (51)
Accelerating neuromorphic vision algorithms for recognition (2012) (49)
Exploring technology alternatives for nano-scale FPGA interconnects (2005) (47)
Instruction Scheduling for Low Power (2004) (47)
Implications of technology scaling on leakage reduction techniques (2003) (46)
Impact of technology scaling in the clock system power (2002) (46)
Compiler-assisted soft error detection under performance and energy constraints in embedded systems (2009) (45)
A parallel architecture for secure FPGA symmetric encryption (2004) (45)
Object-Oriented Architectural Support for a Java Processor (1998) (45)
Adapting instruction level parallelism for optimizing leakage in VLIW architectures (2003) (44)
Total power optimization through simultaneously multiple-vDD multiple-vTH assignment and device sizing with stack forcing (2004) (44)
Investigating the impact of NBTI on different power saving cache strategies (2010) (44)
Third Eye: A Shopping Assistant for the Visually Impaired (2017) (43)
Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers (2007) (43)
Exploiting program hotspots and code sequentiality for instruction cache leakage management (2003) (42)
Device Circuit Co Design of FEFET Based Logic for Low Voltage Processors (2016) (41)
Steep-Slope Devices: From Dark to Dim Silicon (2013) (41)
Compiler optimizations for low power systems (2002) (41)
Energy Behavior of Java Applications from the Memory Perspective (2001) (41)
Masking the energy behavior of DES encryption [smart cards] (2003) (41)
Rf-powered systems using steep-slope devices (2014) (40)
Reliability-aware design for nanometer-scale devices (2008) (38)
Compiler-directed array interleaving for reducing energy in multi-bank memories (2002) (38)
Hotspot prevention through runtime reconfiguration in network-on-chip (2005) (38)
Designing energy-efficient NoC for real-time embedded systems through slack optimization (2013) (38)
Thermal-aware reliability analysis for Platform FPGAs (2008) (37)
A generic reconfigurable neural network architecture as a network on chip (2004) (37)
Understanding and improving operating system effects in control flow prediction (2002) (36)
Compiler-directed thermal management for VLIW functional units (2006) (36)
Power-aware partitioned cache architectures (2001) (36)
Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework (2003) (36)
Ultra Low Power Circuit Design Using Tunnel FETs (2012) (36)
Tuning garbage collection for reducing memory system energy in an embedded java environment (2002) (36)
Partitioned instruction cache architecture for energy efficiency (2003) (35)
Clock power issues in system-on-a-chip designs (1999) (34)
Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power (2016) (34)
Working with Process Variation Aware Caches (2007) (33)
An FPGA Implementation of Information Theoretic Visual-Saliency System and Its Optimization (2011) (33)
A reconfigurable accelerator for neuromorphic object recognition (2012) (33)
Exploring Wakeup-Free Instruction Scheduling (2004) (32)
A holistic approach to designing energy-efficient cluster interconnects (2005) (32)
A novel low power CAM design (2001) (32)
Emulating Mammalian Vision on Reconfigurable Hardware (2012) (32)
Tunnel FET-based ultra-low power, high-sensitivity UHF RFID rectifier (2013) (31)
Implementing LDPC decoding on network-on-chip (2005) (31)
Ferroelectric Transistor based Non-Volatile Flip-Flop (2016) (31)
Variation-Aware Task and Communication Mapping for MPSoC Architecture (2011) (30)
Data Organization and Retrieval on Parallel Air Channels: Performance and Energy Issues (2004) (30)
RAFT: A router architecture with frequency tuning for on-chip networks (2011) (29)
Multidimensional DFT IP Generator for FPGA Platforms (2011) (29)
FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-sized Data (2009) (29)
Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores (2012) (29)
Exploring architectural heterogeneity in intelligent vision systems (2015) (29)
Instruction scheduling based on energy and performance constraints (2000) (28)
ChipPower: an architecture-level leakage simulator (2004) (28)
Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores (2011) (28)
Reconfigurable BDD based quantum circuits (2008) (28)
Spendthrift: Machine learning based resource and frequency scaling for ambient energy harvesting nonvolatile processors (2017) (28)
Thermal Characterization and Optimization in Platform FPGAs (2006) (28)
Leakage control in FPGA routing fabric (2005) (27)
Nonvolatile processors: Why is it trending? (2017) (27)
Process-Variation-Aware Adaptive Cache Architecture and Management (2009) (27)
A linear array processor with dynamic frequency clocking for image processing applications (1998) (27)
Automated mapping for reconfigurable single-electron transistor arrays (2011) (26)
EAC: a compiler framework for high-level energy estimation and optimization (2002) (26)
Enabling New Computation Paradigms with HyperFET - An Emerging Device (2016) (26)
PennBench: a benchmark suite for embedded Java (2002) (26)
Comparative Area and Parasitics Analysis in FinFET and Heterojunction Vertical TFET Standard Cells (2016) (26)
Computational Architectures Based on Coupled Oscillators (2014) (26)
Energy savings through compression in embedded Java environments (2002) (25)
Detecting SEU-caused routing errors in SRAM-based FPGAs (2005) (25)
Compiler-directed high-level energy estimation and optimization (2005) (25)
Impact of NBTI on FPGAs (2007) (24)
Improving Java performance using dynamic method migration on FPGAs (2004) (24)
Low-leakage robust SRAM cell design for sub-100nm technologies (2005) (24)
Memory system energy: Influence of hardware-software optimizations (2000) (24)
Simultaneous partitioning and frequency assignment for on-chip bus architectures (2005) (24)
Hierarchical Soft Error Estimation Tool (HSEET) (2008) (23)
Evaluation of tunnel FET-based flip-flop designs for low power, high performance applications (2013) (23)
A Multitask Grocery Assist System for the Visually Impaired: Smart glasses, gloves, and shopping carts provide auditory and tactile feedback (2017) (23)
TS-Router: On maximizing the Quality-of-Allocation in the On-Chip Network (2013) (23)
Supporting object accesses in a Java processor (2000) (23)
Always-On Speech Recognition Using TrueNorth, a Reconfigurable, Neurosynaptic Processor (2017) (22)
Influence of leakage reduction techniques on delay/leakage uncertainty (2005) (22)
Accelerating the Nonuniform Fast Fourier Transform Using FPGAs (2010) (22)
On-chip Bus Thermal Analysis and Optimization (2006) (22)
Predicting the performance and reliability of future field programmable gate arrays routing architectures with carbon nanotube bundle interconnect (2009) (22)
System-On-Chip for Biologically Inspired Vision Applications (2012) (22)
Emerging Reconfigurable Nanotechnologies: Can they support Future Electronics? (2018) (22)
Variation aware placement for FPGAs (2006) (22)
Design of Thermally Robust Clock Trees Using Dynamically Adaptive Clock Buffers (2009) (21)
Dynamic machine learning based matching of nonvolatile processor microarchitecture to harvested energy profile (2015) (21)
New-Age: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components (2009) (21)
Comparative analysis of NBTI effects on low power and high performance flip-flops (2008) (21)
A comparative study of power efficient SRAM designs (2000) (21)
NEBULA: A Neuromorphic Spin-Based Ultra-Low Power Architecture for SNNs and ANNs (2020) (21)
Estimating influence of data layout optimizations on SDRAM energy consumption (2003) (20)
Multiple access caches: Energy implications (2000) (20)
Formulation and validation of an energy dissipation model for the clock generation circuitry and distribution networks (2001) (20)
An efficient architecture for motion estimation and compensation in the transform domain (2006) (20)
ShieldUS: A novel design of dynamic shielding for eliminating 3D TSV crosstalk coupling noise (2013) (20)
Tunnel FET-based ultra-low power, low-noise amplifier design for bio-signal acquisition (2014) (20)
On reconfigurable Single-Electron Transistor arrays synthesis using reordering techniques (2013) (19)
Delay and energy efficient data transmission for on-chip buses (2006) (19)
On load latency in low-power caches (2003) (19)
Modeling steep slope devices: From circuits to architectures (2014) (19)
Visual co-occurrence network: using context for large-scale object recognition in retail (2015) (19)
Characterizing dynamic and leakage power behavior in flip-flops (2002) (19)
A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs (2004) (19)
Effect of compiler optimizations on memory energy (2000) (19)
A Scalable Bandwidth Aware Architecture for Connected Component Labeling (2010) (19)
Simultaneous memory and bus partitioning for SoC architectures (2005) (18)
Dynamic Power and Energy Management for Energy Harvesting Nonvolatile Processor Systems (2017) (18)
A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays (2013) (18)
Using dynamic branch behavior for power-efficient instruction fetch (2003) (18)
A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support (2018) (18)
A framework for estimating NBTI degradation of microarchitectural components (2009) (17)
A hardware architecture for accelerating neuromorphic vision algorithms (2011) (17)
A multi-resolution saliency framework to drive foveation (2013) (17)
Enabling Internet-of-Things: Opportunities brought by emerging devices, circuits, and architectures (2016) (17)
Tuning Branch Predictors to Support Virtual Method Invocation in Java (1999) (17)
Reducing instruction cache energy consumption using a compiler-based strategy (2004) (17)
An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization (2009) (17)
Use of local memory for efficient Java execution (2001) (16)
Optimizing the NoC Slack Through Voltage and Frequency Scaling in Hard Real-Time Embedded Systems (2014) (16)
Energy-Delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated Logic Circuits (2010) (16)
Steep slope devices: Enabling new architectural paradigms (2014) (16)
Optimizing power and performance for reliable on-chip networks (2010) (16)
Look-Up Table based Energy Efficient Processing in Cache Support for Neural Network Acceleration (2020) (16)
A Distributed Multi-Point Network Interface for Low-Latency, Deadlock-Free On-Chip Interconnects (2006) (15)
Three-Dimensional Network-on-Chip Architecture (2010) (15)
A scalable architecture for multi-class visual object detection (2015) (15)
Design of a nanosensor array architecture (2004) (15)
Energy efficient datapath synthesis using dynamic frequency clocking and multiple voltages (1999) (15)
A complete phase-locked loop power consumption model (2002) (14)
Adaptive Garbage Collection for Battery-Operated Environments (2002) (14)
An integer linear programming-based tool for wireless sensor networks (2005) (14)
Case Study of Reliability-Aware and Low-Power Design (2008) (14)
SUBGEN: a genetic approach for subcircuit extraction (1996) (14)
An examination of the architecture and system-level tradeoffs of employing steep slope devices in 3D CMPs (2014) (14)
Analyzing energy behavior of spatial access methods for memory-resident data (2001) (14)
FeFET-based low-power bitwise logic-in-memory with direct write-back and data-adaptive dynamic sensing interface (2020) (14)
Dual Mode Ferroelectric Transistor based Non-Volatile Flip-Flops for Intermittently-Powered Systems (2018) (14)
Exploration of Low-Power High-SFDR Current-Steering D/A Converter Design Using Steep-Slope Heterojunction Tunnel FETs (2016) (14)
Impact of technology scaling and packaging on dynamic voltage scaling techniques (2002) (14)
Exploring Gabor Filter Implementations for Visual Cortex Modeling on FPGA (2011) (14)
When to forget: A system-level perspective on STT-RAMs (2012) (13)
Video analytics using beyond CMOS devices (2014) (13)
Inverse discrete cosine transform architecture exploiting sparseness and symmetry properties (2004) (13)
An FPGA-based accelerator for cortical object classification (2012) (13)
Mitigating electromigration of power supply networks using bidirectional current stress (2012) (13)
Energy-aware code cache management for memory-constrained Java devices (2003) (13)
Run-time adaption for highly-complex multi-core systems (2013) (13)
Efficient Function Evaluations with Lookup Tables for Structured Matrix Operations (2007) (13)
A High-Efficiency Switched-Capacitance HTFET Charge Pump for Low-Input-Voltage Applications (2015) (13)
A Unified Streaming Architecture for Real Time Face Detection and Gender Classification (2007) (13)
ResiRCA: A Resilient Energy Harvesting ReRAM Crossbar-Based Accelerator for Intelligent Embedded Processors (2020) (13)
Analyzing data reuse for cache reconfiguration (2005) (13)
Influence of array allocation mechanisms on memory system energy (2001) (13)
Memory system energy (poster session): influence of hardware-software optimizations (2000) (13)
MDACache: Caching for Multi-Dimensional-Access Memories (2018) (12)
A Holistic Approach to System Level Energy Optimization (2000) (12)
Width minimization in the Single-Electron Transistor array synthesis (2014) (12)
Energy-performance trade-offs for spatial access methods on memory-resident data (2002) (12)
Impact of dynamic voltage and frequency scaling on the architectural vulnerability of GALS architectures (2008) (12)
Memory Energy Management Using Software and Hardware Directed Power Mode Control (2000) (12)
SHARC: A streaming model for FPGA accelerators and its application to Saliency (2011) (12)
Independently-Controlled-Gate FinFET 6T SRAM Cell Design for Leakage Current Reduction and Enhanced Read Access Speed (2014) (12)
AIGuide: An Augmented Reality Hand Guidance Application for People with Visual Impairments (2020) (12)
NEOFog: Nonvolatility-Exploiting Optimizations for Fog Computing (2018) (12)
Experimental Evaluation of Energy Behavior of Iteration Space Tiling (2000) (12)
SLAT : Secure Localization with Attack Tolerance (2005) (11)
Compiler-directed cache polymorphism (2002) (11)
Variation-Aware Low-Power Buffer Design (2007) (10)
Hardware Acceleration for Neuromorphic Vision Algorithms (2013) (10)
Energy-aware compilation and execution in Java-enabled mobile devices (2003) (10)
A framework for accelerating neuromorphic-vision algorithms on FPGAs (2011) (10)
Evaluating alternative implementations for LDPC decoder check node function (2004) (10)
Transaction level error susceptibility model for bus based SoC architectures (2006) (10)
A data-driven approach for embedded security (2005) (10)
Context-Aware Convolutional Neural Network over Distributed System in Collaborative Computing (2019) (10)
Refresh Enabled Video Analytics (REVA): Implications on power and performance of DRAM supported embedded visual systems (2014) (10)
Reducing dynamic and leakage energy in VLIW architectures (2006) (10)
Reliability-aware SOC voltage islands partition and floorplan (2006) (10)
Designing energy-efficient software (2002) (10)
A VLSI array architecture with dynamic frequency clocking (1996) (10)
Impact of process scaling on the efficacy of leakage reduction schemes (2004) (9)
Energy-efficient Java execution using local memory and object co-location (2004) (9)
TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platform (2007) (9)
A hardware accelerated multilevel visual classifier for embedded visual-assist systems (2014) (9)
Power-efficient trace caches (2002) (9)
An algorithm-architecture co-design framework for gridding reconstruction using FPGAs (2011) (9)
Geometric Tiling for Reducing Power Consumption in Structured Matrix Operations (2006) (9)
Design of energy-efficient circuits and systems using tunnel field effect transistors (2013) (9)
Variation Analysis of CAM Cells (2007) (9)
VLIW scheduling for energy and performance (2001) (9)
Test Generation for Precise Interrupts on Out-of-Order Microprocessors (2009) (9)
Single-Ended and Differential MRAMs Based on Spin Hall Effect: A Layout-Aware Design Perspective (2015) (9)
Online detection and diagnosis of multiple configuration upsets in LUTs of SRAM-based FPGAs (2005) (9)
Networks on Chip (NoC): Interconnects of Next Generation Systems on Chip (2005) (9)
Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling (2012) (9)
Low-power high-speed current mode logic using Tunnel-FETs (2014) (9)
Soft errors: is the concern for soft-errors overblown? (2005) (8)
A reconfigurable platform for the design and verification of domain-specific accelerators (2012) (8)
A framework for energy estimation of VLIW architecture (2001) (8)
Total Power Optimization for Combinational Logic Using Genetic Algorithms (2010) (8)
Efficient image reconstruction using partial 2D Fourier transform (2008) (8)
Managing Leakage Energy in Cache Hierarchies (2003) (8)
CAPE: A Content-Addressable Processing Engine (2021) (8)
Masking the energy behaviour of encryption algorithms (2003) (8)
Sequential tests for integrated-circuit failures (1998) (8)
Power-efficient implementation of turbo decoder in SDR system (2004) (8)
Analyzing heap error behavior in embedded JVM environments (2004) (8)
SESEE: A soft error simulation and estimation engine (2004) (8)
CCC: crossbar connected caches for reducing energy consumption of on-chip multiprocessors (2003) (8)
Bandwidth-intensive FPGA architecture for multi-dimensional DFT (2010) (8)
Monolithic-3D Integration Augmented Design Techniques for Computing in SRAMs (2019) (8)
Energy-Aware Instruction Scheduling (2000) (7)
A Unified Energy Estimation Framework with Integrated Hardware-Software Optimizations (2000) (7)
Field level analysis for heap space optimization in embedded java environments (2004) (7)
Enabling architectural innovations using non-volatile memory (2011) (7)
Reducing dTLB energy through dynamic resizing (2003) (7)
IAA: Incidental Approximate Architectures for Extremely Energy-Constrained Energy Harvesting Scenarios using IoT Nonvolatile Processors (2018) (7)
Gesture-SNN: Co-optimizing accuracy, latency and energy of SNNs for neuromorphic vision sensors (2021) (7)
Harnessing ferroelectrics for non-volatile memories and logic (2017) (7)
VL-CDRAM: variable line sized cached DRAMs (2003) (7)
Thermal-Aware Application Scheduling on Device-Heterogeneous Embedded Architectures (2015) (7)
Predictive Precharging for Bitline Leakage Energy Reduction (2002) (7)
Effect of Power Optimizations on Soft Error Rate (2003) (7)
MaxTracker: Continuously Tracking the Maximum Computation Progress for Energy Harvesting ReRAM-based CNN Accelerators (2021) (7)
A dynamic frequency linear array processor for image processing (1996) (6)
Improving FPGA Design with Monolithic 3D Integration Using High Dense Inter-Stack Via (2017) (6)
Switch Box Architectures for Three-Dimensional FPGAs (2006) (6)
An architecture for motion estimation in the transform domain (2004) (6)
Asymmetric Double-Gate Ferroelectric FET to Decouple the Tradeoff Between Thickness Scaling and Memory Window (2022) (6)
An Accuracy Tunable Non-Boolean Co-Processor Using Coupled Nano-Oscillators (2017) (6)
An energy efficient scheduling scheme for signal processing applications (1998) (6)
Block-based frequency scalable technique for efficient hierarchical coding (2006) (6)
A Probabilistic Model for Soft-Error Rate Estimation in Combinational Logic (2004) (6)
Saliency aware display power management (2013) (6)
Sparse to Dense Depth Completion using a Generative Adversarial Network with Intelligent Sampling Strategies (2021) (6)
Comparing Energy, Area, Delay Tradeoffs in Going Vertical with CMOS and Asymmetric HTFETs (2015) (6)
A Novel Low Area Overhead Body Bias FPGA Architecture for Low Power Applications (2009) (6)
Analysis and solutions to issue queue process variation (2008) (6)
Co-training of feature extraction and classification using partitioned convolutional neural networks (2017) (6)
Energy-efficient instruction cache using page-based placement (2001) (6)
Saliency-driven dynamic configuration of HMAX for energy-efficient multi-object recognition (2013) (6)
Energy and performance considerations in work partitioning for mobile spatial queries (2003) (5)
Techniques for Designing Energy-Aware MPSoCs (2005) (5)
A highly reliable NBTI Resilient 6T SRAM cell (2013) (5)
A criticality-driven microarchitectural three dimensional (3D) floorplanner (2009) (5)
Object duplication for improving reliability (2006) (5)
Soft errors in adder circuits (2004) (5)
Scheduling reusable instructions for power reduction (2004) (5)
Morphable Cache Architectures: Potential Benefits (2001) (5)
A scalable multi-FPGA framework for real-time digital signal processing (2009) (5)
Harnessing Emerging Technology for Compute-in-Memory Support (2018) (5)
Process Variation Aware Parallelization Strategies for MPSoCs (2006) (5)
A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays (2015) (5)
LATTE: Low-power Audio Transform with TrueNorth Ecosystem (2016) (5)
Programmable Non-Volatile Memory Design Featuring Reconfigurable In-Memory Operations (2019) (5)
Drones as collaborative sensors for image recognition (2018) (5)
SoC design skills: collaboration builds a stronger SoC design team (2001) (5)
Security and Dependability of Embedded Systems: A Computer Architects' Perspective (2009) (5)
Tracking object life cycle for leakage energy optimization (2003) (5)
Multiresolution Gabor Feature Extraction for Real Time Applications (2012) (5)
Data Organization and Retrieval on Parallel Air Channels (2000) (5)
IMC-Sort: In-Memory Parallel Sorting Architecture using Hybrid Memory Cube (2020) (5)
Towards Energy-Aware Iteration Space Tiling (2000) (5)
Symmetric encryption in reconfigurable and custom hardware (2005) (5)
Optimizing Leakage Energy Consumption in Cache Bitlines (2004) (5)
A Low-Voltage Low-Power LC Oscillator Using the Diode-Connected SymFET (2014) (5)
FPGA-accelerator system for computing biologically inspired feature extraction models (2011) (5)
Investigating Simple Low Latency Reliable Multiported Register Files (2007) (5)
Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays (2016) (5)
Synthesis for Width Minimization in the Single-Electron Transistor Array (2015) (5)
Towards Resilient Micro-architectures: Datapath Reliability Enhancement Using STT-MRAM (2011) (5)
Optimising power efficiency in trace cache fetch unit (2007) (4)
Input sensitive high-level power analysis (2001) (4)
Design space exploration of workload-specific last-level caches (2012) (4)
A clock power model to evaluate impact of architectural and technology optimizations - a summary (2003) (4)
Predictive precharging for bitline leakage energy reduction [microprocessor caches] (2002) (4)
FARM: A Flexible Accelerator for Recurrent and Memory Augmented Neural Networks (2020) (4)
Design considerations for databus charge recovery (2001) (4)
A nanosensor array-based VLSI gas discriminator (2005) (4)
Stochastic Functional Verification of DNN Design through Progressive Virtual Dataset Generation (2018) (4)
Temperature and Voltage Scaling Effects on Electrical Masking (4)
Leakage-aware interconnect for on-chip network (2005) (4)
Leveraging Emerging Technology Through Architectural Exploration for the Routing Fabric of Future FPGAs (2011) (4)
Accelerating Multiresolution Gabor Feature Extraction for Real Time Vision Applications (2014) (4)
PSB-RNN: A Processing-in-Memory Systolic Array Architecture using Block Circulant Matrices for Recurrent Neural Networks (2020) (4)
Memory energy characterization and optimization for the SPEC2000 benchmarks (2001) (4)
Exploiting value locality for secure-energy aware communication (2003) (4)
Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures (2007) (4)
A unified energy framework with integrated hardware-software optimizations (2000) (4)
Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors (2009) (4)
Efficient VLSI implementation of inverse discrete cosine transform [image coding applications] (2004) (4)
Exploiting clock skew scheduling for FPGA (2009) (4)
SimplePower : A Cycle-Accurate Energy Simulator (2000) (4)
A streaming FPGA implementation of a steerable filter for real-time applications (abstract only) (2011) (4)
Analyzing Energy-Delay Behavior in Room Temperature Single Electron Transistors (2010) (4)
Clone Detection in Sensor Networks with Ad Hoc and Grid Topologies (2009) (4)
Transformer-based Machine Learning for Fast SAT Solvers and Logic Synthesis (2021) (4)
The substrate noise detector for noise tolerant mixed-signal IC (2003) (3)
Cryogenic Memory Array based on Ferroelectric SQUID and Heater Cryotron (2022) (3)
Design of power-aware FPGA fabrics (2007) (3)
Area-Aware Decomposition for Single-Electron Transistor Arrays (2016) (3)
OS-Aware Branch Prediction: Improving Microprocessor Control Flow Prediction for Operating Systems (2007) (3)
Leakage-aware compilation for VLIW architectures (2005) (3)
DFLAP: a dynamic frequency linear array processor (1996) (3)
High performance array processor for video decoding (2005) (3)
Impact of Circuit Degradation on FPGA Design Security (2011) (3)
Lifetime Reliability Aware Design Flow Techniques for Dual-Vdd Based Platform FPGAs (2009) (3)
Overview of Ferroelectric Memory Devices and Reliability Aware Design Optimization (2021) (3)
Towards a unified multiresolution vision model for autonomous ground robots (2016) (2)
Investigating Memory System Energy Behavior Using Software and Hardware Optimizations (2001) (2)
Design space for scaling-in general purpose computing within the DDR DRAM hierarchy for map-reduce workloads (2021) (2)
Exploiting natural redundancy in visual information (2014) (2)
SPRT for Weibull distributed integrated circuit failures (1998) (2)
A Power-Efficient Hybrid Architecture Design for Image Recognition Using CNNs (2018) (2)
Origin: Enabling On-Device Intelligence for Human Activity Recognition Using Energy Harvesting Wireless Sensor Networks (2021) (2)
Designing leakage aware multipliers (2004) (2)
Characterization of memory energy behavior (2001) (2)
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006 (2006) (2)
Search speed and power driven integrated software and hardware optimizations for motion estimation algorithms (2004) (2)
CMOS-compatible ising machines built using bistable latches coupled through ferroelectric transistor arrays (2022) (2)
Masking the Energy Behavior of Encryption Algorithms (2003) (2)
Code protection for resource-constrained embedded devices (2004) (2)
Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network (2009) (2)
In-Network Caching for Chip Multiprocessors (2008) (2)
EMERALD: Characterization of emerging applications and algorithms for low-power devices (2013) (2)
Non-volatile Logic and Memory based on Reconfigurable Ferroelectric Transistors (2019) (2)
Influence of MPEG-4 parameters on system energy (2002) (2)
Indoor Navigation using Text Extraction (2018) (2)
Exploring memory controller configurations for many-core systems with 3D stacked DRAMs (2015) (2)
Reducing non-deterministic loads in low-power caches via early cache set resolution (2007) (2)
Computation and transmission energy modeling through profiling for MPEG4 video transmission (2003) (1)
Thermal Gradient Aware Clock Skew Scheduling for FPGAs (2010) (1)
Reducing Energy Consumption in Chip Multiprocessors Using Workload Variations (2004) (1)
Leakage Optimized DECAP Design for FPGAs (2006) (1)
FAST: A Fully-Concurrent Access Technique to All SRAM Rows for Enhanced Speed and Energy Efficiency in Data-Intensive Applications (2022) (1)
A Configurable Architecture for a Visual Saliency System and Its Application in Retail (2013) (1)
Ferroelectric-based Accelerators for Computationally Hard Problems (2021) (1)
Staggered latch bus: A reliable offset switched architecture for long on-chip interconnect (2013) (1)
Cognitive cameras: Assistive vision systems (2015) (1)
A GPU based implementation of Center-Surround Distribution Distance for feature extraction and matching (2010) (1)
Security issues in embedded system design (2005) (1)
Achieving Crash Consistency by Employing Persistent L1 Cache (2022) (1)
Exploiting temporal loads for low latency and high bandwidth memory (2005) (1)
Exploiting Activation based Gradient Output Sparsity to Accelerate Backpropagation in CNNs (2021) (1)
Invited paper: Accelerating neuromorphic vision on FPGAs (2011) (1)
Exploring architectural solutions for energy optimisations in bus-based system-on-chip (2008) (1)
FPRA: A Fine-grained Parallel RRAM Architecture (2021) (1)
Improving ILP with instruction-reuse cache hierarchy (2002) (1)
Integrated CAM-RAM Functionality using Ferroelectric FETs (2020) (1)
Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs (2005) (1)
Hardware-software co-adaptation for data-intensive embedded applications (2002) (1)
TESTING NEUTRON-INDUCED SOFT ERRORS IN SEMICONDUCTOR MEMORIES Participants: (2007) (1)
Energy and timing characterization of VLSI charge-pump phase-locked loops (2003) (1)
Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only) (2005) (1)
Using Multiple-Input NEMS for Parallel A/D Conversion and Image Processing (2015) (1)
Editorial (2005) (1)
Technology-Assisted Computing-In-Memory Design for Matrix Multiplication Workloads (2019) (1)
X-VS: Crossbar-Based Processing-in-Memory Architecture for Video Summarization (2020) (1)
Platform-aware dynamic configuration support for efficient text processing on heterogeneous system (2015) (1)
Power efficient adaptive M-QAM design using adaptive pipelined analog-to-digital converter (2002) (1)
Introduction to Special Issue on Neuromorphic Computing (2015) (1)
Hazard driven test generation for SMT processors (2012) (1)
FPGA routing architecture analysis under variations (2007) (1)
How can hardware support Just-In-Time compilation? (1999) (1)
Heuristic Approximation of Early-Stage CNN Data Representation for Vision Intelligence Systems (2018) (1)
An Oscillator-based MaxSAT solver (2021) (1)
Hardware and software techniques for DRAM energy management (2001) (1)
Mixed Precision Quantization Scheme for Re-configurable ReRAM Crossbars Targeting Different Energy Harvesting Scenarios (2019) (1)
Robust Multimodal Depth Estimation using Transformer based Generative Adversarial Networks (2022) (1)
Testing neutron-induced soft errors in semiconductor memory, invited (2004) (1)
Guest Editorial (2004) (0)
Editorial (2008) (0)
The sandbox design experience course (2003) (0)
DoubtNet: Using Semantic Context to Enable Adaptive Inference for the IoT (2020) (0)
Intelligent Vision Systems: Exploring the State-of-the-Art and Opportunities for the Future (2015) (0)
Circuits and systems society VLSI transactions best paper award-2003 (2003) (0)
Green transistors to green architectures (2009) (0)
An Energy-Aware Approach for Sensor Data Communication (2012) (0)
ASMCap: An Approximate String Matching Accelerator for Genome Sequence Analysis Based on Capacitive Content Addressable Memory (2023) (0)
Tota I Power 0 pt i m izat i o n t h rough Si mu Ita neous I y Multiple-V,, Multiple-V,, Assignment and Device Sizing with Stack Forcing (2004) (0)
Testing Neutron-induced Soft Errors (2007) (0)
Targeted random test generation for power-aware multicore designs (2012) (0)
Performance Evaluation of Video Analytics Workloads on Emerging Processing-In-Memory Architectures (2022) (0)
Seeker: Synergizing Mobile and Energy Harvesting Wearable Sensors for Human Activity Recognition (2022) (0)
Dynamic bandwidth adaptation using recognition accuracy prediction through pre-classification for embedded vision systems (2013) (0)
An efficient implementation of hierarchical image coding (2003) (0)
Resolution-Aware Deep Multi-View Camera Systems (2021) (0)
Noise Aware Power Adaptive Partitioned Deep Networks for Mobile Visual Assist Platforms (2018) (0)
Introduction to the Special Issue on Domain-Specific Multicore Computing (2014) (0)
Data driven adaptation for QoS aware embedded vision systems (2014) (0)
Total power optimization through simultaneously multiple-V/sub DD/ multiple-V/sub TH/ assignment and device sizing with stack forcing (2004) (0)
Software power optimisation (2006) (0)
Microprocessor at 50: A Time to Celebrate and Energize for the Future (2021) (0)
Editorial (2017) (0)
Analyzing software influences on substrate noise: an ADC perspective (2004) (0)
Designing reliable circuit in the presence of soft errors (2005) (0)
Microprocessor at 50: Industry Leaders Speak (2021) (0)
Ultra low power signal processing architectures (2008) (0)
Extending Action Recognition in the Compressed Domain (2023) (0)
Voltage-controlled Cryogenic Boolean Logic Family Based on Ferroelectric SQUID (2022) (0)
A task-oriented vision system (2014) (0)
A Scheduling Framework for Decomposable Kernels on Energy Harvesting IoT Edge Nodes (2022) (0)
- Compiler-Directed Communication Energy Optimizations for Microsensor Networks (2012) (0)
AutoFLEX: A Framework for Image Processing Applications on Multiple-FPGA Systems (2010) (0)
Analyzing heap error behavior in embedded JVM environments (2004) (0)
Hotspot Avoidance Through Runtime Reconfiguration in Network-On-Chip Designs (2004) (0)
Energy Efficient and Reliable System Design (2003) (0)
Performance Improvements through Timing Driven Reconfiguration of Black-Boxes in Platform FPGAs (2006) (0)
Editorial (2016) (0)
Guest Editorial Advances in Design of Energy-Efficient Circuits and Systems (Second Issue) (2011) (0)
GRAPHIC: GatheR-And-Process in Highly parallel with In-SSD Compression Architecture in Very Large-Scale Graph (2022) (0)
Ultra low power TFET-based circuits (2013) (0)
Context-Aware Collaborative Object Recognition For Distributed Multi Camera Time Series Data (2019) (0)
Ferroelectric FET-based strong physical unclonable function: a low-power, high-reliable and reconfigurable solution for Internet-of-Things security (2022) (0)
EFFECTOFCOMPILEROPTIMIZATIONS ON MEMORY ENERGY (2000) (0)
Influence of Stacked 3D Memory/Cache Architectures on GPUs (2011) (0)
Tools and Techniques for Integrated Hardware-Software Energy Optimizations (2002) (0)
Going Vertical: The Future of Electronics (2019) (0)
A CLB architecture for Online correction of SEU-based Errors in LUTs of SRAM-based FPGAs (2005) (0)
Using Memory Compression for Energy Reduction in an Embedded Java System (2002) (0)
Keynote talk: Embedded vision systems (2013) (0)
Skipper: Enabling efficient SNN training through activation-checkpointing and time-skipping (2022) (0)
An 8T/Cell FeFET-Based Nonvolatile SRAM with Improved Density and Sub-fJ Backup and Restore Energy (2022) (0)
A Saliency-Driven LCD Power Management System (2016) (0)
Energy Optimization Using Object Co-Location in Java (2007) (0)
An Exploration of Hardware Architectures for Face Detection (2006) (0)
Proceedings of Deisgn, Automation & Test in Europe IEEE International Conference, DATE, 2010, Germany (2010) (0)
Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET (2023) (0)
Designing Energy-Aware Sensor Systems (2012) (0)
Ultra Low Power Signal Processing Architectures Enabling Next-Generation BioSensing and Biomimetic Systems (2015) (0)
Soft error rate measurements in semiconductor memories at Pennsylvania state university (2007) (0)
Architecture and Design Flow Optimizations for Power-Aware FPGAs (2006) (0)
Editorial (2014) (0)
ALL-MASK: A Reconfigurable Logic Locking Method for Multicore Architecture with Sequential-Instruction-Oriented Key (2022) (0)
Trends and Opportunities for SRAM Based In-Memory and Near-Memory Computation (2021) (0)
Token and Head Adaptive Transformers for Efficient Natural Language Processing (2022) (0)
Editorial (2015) (0)
PowerPrep: A power management proposal for user-facing datacenter workloads (2021) (0)
The 4th Artificial Intelligence of Things (AIoT) Workshop (2021) (0)
FUNCTIONAL RECONFIGURATION FOR FAULT-TOLERANCE : A NEW APPROACH (2007) (0)

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