Nikil Dutt

Q: What Schools Are Affiliated With Nikil Dutt

Nikil Dutt is affiliated with the following schools: University of California, Irvine, Pennsylvania State University, BITS Pilani, University of Illinois Urbana-Champaign

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Nikil Dutt

Computer Science

#1933

World Rank

#2008

Historical Rank

#913

USA Rank

Database

#1747

World Rank

#1832

Historical Rank

#442

USA Rank

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Computer Science

Why Is Nikil Dutt Influential?

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According to Wikipedia, Nikil Dutt is a Chancellor's Professor of Computer Science at University of California, Irvine, United States. Professor Dutt's research interests are in embedded systems, electronic design automation, computer architecture, optimizing compilers, system specification techniques, distributed systems, and formal methods.

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Nikil Dutt's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

High ― Level Synthesis: Introduction to Chip and System Design (1992) (1173)
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability (1999) (439)
SPARK: a high-level synthesis framework for applying parallelizing compiler transformations (2003) (429)
Data and memory optimization techniques for embedded systems (2001) (370)
Efficient utilization of scratch-pad memory in embedded processor applications (1997) (294)
On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems (2000) (247)
A configurable simulation environment for the efficient simulation of large-scale spiking neural networks on graphics processors (2009) (209)
Reliable on-chip systems in the nano-era: Lessons learnt and future trends (2013) (204)
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration (1998) (179)
Profile-based dynamic voltage scheduling using program checkpoints (2002) (177)
Partitioned Register Files For VLIWs: A Preliminary Analysis Of Tradeoffs (1992) (172)
On-Chip Communication Architectures: System on Chip Interconnect (2008) (159)
SPECTR (2018) (155)
Memory Issues in Embedded Systems-on-Chip (1999) (152)
Underdesigned and Opportunistic Computing in Presence of Hardware Variability (2013) (152)
Instruction set compiled simulation: a technique for fast and flexible instruction set simulation (2003) (141)
Integrated power management for video streaming to mobile handheld devices (2003) (133)
HiCH: Hierarchical Fog-Assisted Computing Architecture for Healthcare IoT (2017) (127)
Extending the transaction level modeling approach for fast communication architecture exploration (2004) (126)
Fast Configurable-Cache Tuning With a Unified Second-Level Cache (2005) (116)
Categorization and decision-making in a neurobiologically plausible spiking network using a STDP-like learning rule (2013) (114)
Automatic tuning of two-level caches to embedded applications (2004) (111)
COVID Symptoms, Symptom Clusters, and Predictors for Becoming a Long-Hauler: Looking for Clarity in the Haze of the Pandemic (2021) (110)
Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration (2005) (109)
Augmenting Loop Tiling with Data Alignment for Improved Cache Performance (1999) (108)
Efficient simulation of large-scale Spiking Neural Networks using CUDA graphics processors (2009) (107)
Coordinated parallelizing compiler optimizations and high-level synthesis (2004) (105)
Compilation approach for coarse-grained reconfigurable architectures (2003) (96)
1995 high level synthesis design repository (1995) (92)
Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration (2006) (91)
Processor Description Languages (2008) (90)
An Enhanced Power Estimation Model for On-Chip Caches (2004) (88)
Low-power memory mapping through reducing address bus activity (1999) (86)
SPARTA: Runtime task allocation for energy efficient heterogeneous manycores (2016) (83)
Memory data organization for improved cache performance in embedded processor applications (1997) (80)
Program path analysis to bound cache-related preemption delay in preemptive real-time systems (2000) (80)
Local memory exploration and optimization in embedded systems (1999) (79)
Architectural exploration and optimization of local memory in embedded systems (1997) (77)
Functional coverage driven test generation for validation of pipelined processors (2005) (77)
Mitigating soft error failures for multimedia applications by selective data protection (2006) (77)
Data reuse analysis technique for software-controlled memory hierarchies (2004) (76)
An Efficient Simulation Environment for Modeling Large-Scale Cortical Processing (2011) (74)
Constraint-driven bus matrix synthesis for MPSoC (2006) (71)
An efficient automated parameter tuning framework for spiking neural networks (2014) (71)
Introduction of local memory elements in instruction set extensions (2004) (71)
DYNAMO: A Cross-Layer Framework for End-to-End QoS and Energy Optimization in Mobile Handheld Devices (2007) (70)
Using global code motions to improve the quality of results for high-level synthesis (2004) (68)
Data Memory Organization and Optimizations in Application-Specific Systems (2001) (68)
Floorplan-aware automated synthesis of bus-based communication architectures (2005) (68)
Network topology exploration of mesh-based coarse-grain reconfigurable architectures (2004) (66)
Graph-based functional test program generation for pipelined processors (2004) (66)
Mapping Spiking Neural Networks to Neuromorphic Hardware (2019) (65)
Toward Smart Embedded Systems (2016) (64)
CARLsim 4: An Open Source Library for Large Scale, Biologically Detailed Spiking Neural Network Simulation using Heterogeneous Clusters (2018) (63)
Memory size estimation for multimedia applications (1998) (63)
Exploiting Partially-Forgetful Memories for Approximate Computing (2015) (62)
Post-quantum Lattice-based Cryptography Implementations: A Survey (2019) (62)
Post-quantum Lattice-based Cryptography Implementations: A Survey (2019) (62)
Compilation techniques for energy reduction in horizontally partitioned cache architectures (2005) (61)
Post-Quantum Lattice-Based Cryptography Implementations (2019) (60)
Memory aware compilation through accurate timing extraction (2000) (59)
A cross-layer approach for power-performance optimization in distributed mobile systems (2005) (59)
Instruction set synthesis with efficient instruction encoding for configurable processors (2007) (58)
ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip (2008) (57)
Unsupervised Heart-rate Estimation in Wearables With Liquid States and A Probabilistic Readout (2017) (57)
Efficient instruction encoding for automatic instruction set design of configurable ASIPs (2002) (57)
Memory organization for improved data cache performance in embedded processors (1996) (56)
Dynamic backlight adaptation for low-power handheld devices (2004) (56)
Reducing Backlight Power Consumption for Streaming Video Applications on Mobile Handheld Devices (2003) (56)
Code Transformations for Data Transfer and Storage Exploration Preprocessing in Multimedia Processors (2001) (56)
ISEGEN: generation of high-quality instruction set extensions by iterative improvement (2005) (54)
Neural correlates of sparse coding and dimensionality reduction (2019) (54)
Functional abstraction driven design space exploration of heterogeneous programmable architectures (2001) (53)
An algorithm for mapping loops onto coarse-grained reconfigurable architectures (2003) (53)
Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable Architectures (2011) (53)
V-SAT: a visual specification and analysis tool for system-on-chip exploration (2001) (52)
DRDU: A data reuse analysis technique for efficient scratch-pad memory management (2007) (51)
Self-awareness in remote health monitoring systems using wearable electronics (2017) (51)
Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies (2006) (51)
An efficient compiler technique for code size reduction using reduced bit-width ISAs (2002) (50)
RTGEN: an algorithm for automatic generation of reservation tables from architectural descriptions (1999) (50)
Loop shifting and compaction for the high-level synthesis of designs with complex control flow (2004) (50)
Bypass aware instruction scheduling for register file power reduction (2006) (49)
CARLsim 3: A user-friendly and highly optimized library for the creation of neurobiologically detailed spiking neural networks (2015) (49)
Sleep Tracking of a Commercially Available Smart Ring and Smartwatch Against Medical-Grade Actigraphy in Everyday Settings: Instrument Validation Study (2020) (48)
COSMECA: Application Specific Co-Synthesis of Memory and Communication Architectures for MPSoC (2006) (47)
SPECTR: Formal Supervisory Control and Coordination for Many-core Systems Resource Management (2018) (47)
An efficient retargetable framework for instruction-set simulation (2003) (47)
Trends in Emerging On-Chip Interconnect Technologies (2008) (45)
FABSYN: floorplan-aware bus architecture synthesis (2006) (45)
Architecture Description Languages for Systems-on-Chip Design (1999) (44)
Resilient dependable cyber-physical systems: a middleware perspective (2012) (44)
Optimal register assignment to loops for embedded code generation (1996) (43)
Quality-Based Backlight Optimization for Video Playback on Handheld Devices (2007) (43)
E < MC2: less energy through multi-copy cache (2010) (43)
Access pattern based local memory customization for low power embedded systems (2001) (43)
Comprehensive Lower Bound Estimation From Behavioral Descriptions (1994) (42)
Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation (2009) (41)
A Real-time PPG Quality Assessment Approach for Healthcare Internet-of-Things (2019) (41)
Exploiting off-chip memory access modes in high-level synthesis (1997) (39)
Automatic Identification of Application-Specific Functional Units with Architecturally Visible Storage (2006) (39)
EXPRESSION: An ADL for system level design exploration (1998) (38)
CyberPhysical-System-On-Chip (CPSoC): A self-aware MPSoC paradigm with cross-layer virtual sensing and actuation (2015) (38)
Speculation techniques for high level synthesis of control intensive designs (2001) (37)
Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies (2006) (37)
Self-Awareness in Systems on Chip— A Survey (2017) (37)
Specification-driven directed test generation for validation of pipelined processors (2008) (36)
A GPU-accelerated cortical neural network model for visually guided robot navigation (2015) (36)
ARGO: Aging-aware GPGPU register file allocation (2013) (36)
System-level power-performance trade-offs in bus matrix communication architecture synthesis (2006) (36)
Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications (2009) (36)
Synthesis-driven exploration of pipelined embedded processors (2004) (36)
Power / capacity scaling: Energy savings with simple fault-tolerant caches (2014) (36)
A Multi-Granularity Power Modeling Methodology for Embedded Processors (2011) (36)
Low power address encoding using self-organizing lists (2001) (36)
FFT-Cache: A Flexible Fault-Tolerant Cache architecture for ultra low voltage operation (2011) (35)
ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors (2006) (35)
APEX: access pattern based memory architecture exploration (2001) (35)
Biologically plausible models of homeostasis and STDP: Stability and learning in spiking neural networks (2013) (34)
BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoC (2007) (34)
Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs (2004) (34)
GENUS : a generic component library for high level synthesis (1988) (34)
SmartBalance: A sensing-driven linux load balancer for energy efficiency of heterogeneous MPSoCs (2015) (34)
Rapid exploration of pipelined processors through automatic generation of synthesizable RTL models (2003) (34)
PyCARL: A PyNN Interface for Hardware-Software Co-Simulation of Spiking Neural Network (2020) (34)
Library mapping for memories (1997) (34)
Automatic verification of in-order execution in microprocessors with fragmented pipelines and multicycle functional units (2002) (34)
Introduction of Architecturally Visible Storage in Instruction Set Extensions (2007) (33)
Analysis of the Performance of Coarse-Grain Reconfigurable Architectures with Different Processing Element Configurations (2003) (33)
Data cache sizing for embedded processor applications (1998) (33)
3D-FlashMap: A physical-location-aware block mapping strategy for 3D NAND flash memory (2012) (33)
VaMV: Variability-aware Memory Virtualization (2012) (33)
Configurable Processors for Embedded Computing (2003) (32)
Meta-Cure: A reliability enhancement strategy for metadata in NAND flash memory storage systems (2012) (32)
An intermediate representation for behavioral synthesis (1990) (32)
Bridging high-level slqvihesis to RTL technology libraries (1991) (32)
Objective stress monitoring based on wearable sensors in everyday settings (2020) (32)
Energy-aware cosynthesis of real-time multimedia applications on MPSoCs using heterogeneous scheduling policies (2008) (31)
A Reliability Enhanced Address Mapping Strategy for Three-Dimensional (3-D) NAND Flash Memory (2014) (31)
Leakage Power Estimation in SRAMs (2003) (31)
Automatic functional test program generation for pipelined processors using model checking (2002) (31)
Processor-memory co-exploration driven by a Memory-Aware Architecture Description Language (2001) (31)
Energy efficient watermarking on mobile devices using proxy-based partitioning (2006) (31)
A retargetable framework for instruction-set architecture simulation (2006) (30)
Performance and energy benefits of instruction set extensions in an FPGA soft core (2006) (30)
HaVOC: A hybrid memory-aware virtualization layer for on-chip distributed ScratchPad and Non-Volatile Memories (2012) (30)
A customizable compiler framework for embedded systems (2001) (30)
Performance estimation of distributed real-time embedded systems by discrete event simulations (2007) (30)
Memory optimal single appearance schedule with dynamic loop count for synchronous dataflow graphs (2006) (29)
Self-aware Cyber-Physical Systems-on-Chip (2015) (29)
SPMVisor: Dynamic scratchpad memory virtualization for secure, low power, and high performance distributed on-chip memories (2011) (29)
MIST: an algorithm for memory miss traffic management (2000) (28)
Neural and Synaptic Array Transceiver: A Brain-Inspired Computing Framework for Embedded Learning (2017) (28)
Thermal-Aware Task Mapping on Dynamically Reconfigurable Network-on-Chip Based Multiprocessor System-on-Chip (2018) (28)
Robust ECG R-peak detection using LSTM (2020) (28)
A Framework for Cosynthesis of Memory and Communication Architectures for MPSoC (2007) (27)
Modeling and validation of pipeline specifications (2004) (27)
E-RoC: Embedded RAIDs-on-Chip for low power distributed dynamically managed reliable memories (2011) (27)
ViPZonE: OS-level memory variability-driven physical address zoning for energy savings (2012) (27)
LEAF: A System Level Leakage-Aware Floorplanner for SoCs (2007) (27)
Automatic modeling and validation of pipeline specifications driven by an architecture description language [SoC] (2002) (26)
Rapid estimation for parameterized components in high-level synthesis (1993) (26)
A Framework to Explore Workload-Specific Performance and Lifetime Trade-offs in Neuromorphic Computing (2019) (26)
Mechanisms underlying the basal forebrain enhancement of top‐down and bottom‐up attention (2014) (26)
Memory Architecture Exploration for Programmable Embedded Systems (2002) (26)
Fast exploration of bus-based communication architectures at the CCATB abstraction (2008) (26)
A unified lower bound estimation technique for high-level synthesis (1997) (26)
Elimination of redundant memory traffic in high-level synthesis (1996) (25)
3D Visual Response Properties of MSTd Emerge from an Efficient, Sparse Population Code (2016) (25)
Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays (2012) (25)
Run-DMC: Runtime dynamic heterogeneous multicore performance and power estimation for energy efficiency (2015) (25)
On-chip self-awareness using Cyberphysical-Systems-on-Chip (CPSoC) (2014) (25)
How to solve the current memory access and data transfer bottlenecks: at the processor architecture or at the compiler level (2000) (25)
Error-Exploiting Video Encoder to Extend Energy/QoS Tradeoffs for Mobile Embedded Systems (2008) (24)
xTune: A formal methodology for cross-layer tuning of mobile embedded systems (2012) (24)
Operation tables for scheduling in the presence of incomplete bypassing (2004) (24)
On-Chip Interconnect with aelite: Composable and Predictable Systems (2010) (24)
Generic pipelined processor modeling and high performance cycle-accurate simulator generation (2005) (24)
Mitigating the impact of hardware defects on multimedia applications: a cross-layer approach (2008) (24)
A comprehensive estimation technique for high-level synthesis (1995) (24)
HiCH (2017) (24)
Incorporating DRAM access modes into high-level synthesis (1998) (24)
Design Methodology for High-Level Synthesis (1992) (23)
Quality-aware mobile graphics workload characterization for energy-efficient DVFS design (2014) (23)
Dynamically increasing the scope of code motions during the high-level synthesis of digital circuits (2003) (23)
Compiler driven data layout optimization for regular/irregular array access patterns (2008) (23)
PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures (2006) (23)
Conditional speculation and its effects on performance and area for high-level synthesis (2001) (23)
Models, abstractions, and architectures: The missing links in cyber-physical systems (2015) (23)
A Unified code generation approach using mutation scheduling (1994) (23)
Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications (2005) (23)
Improving cache Performance Through Tiling and Data Alignment (1997) (22)
Large-Scale Spiking Neural Networks using Neuromorphic Hardware Compatible Models (2015) (22)
Personalized Maternal Sleep Quality Assessment: An Objective IoT-based Longitudinal Study (2019) (22)
Synthesis of On-Chip Communication Architectures (2008) (22)
Exploiting Application Data-Parallelism on Dynamically Reconfigurable Architectures: Placement and Architectural Considerations (2009) (22)
Energy-efficient instruction set synthesis for application-specific processors (2003) (22)
Efficient Spiking Neural Network Model of Pattern Motion Selectivity in Visual Cortex (2014) (21)
Approximation knob: Power Capping meets energy efficiency (2016) (21)
Multi-layer memory resiliency (2014) (21)
A Probabilistic Formal Analysis Approach to Cross Layer Optimization in Distributed Embedded Systems (2007) (21)
Formal performance evaluation of AMBA-based system-on-chip designs (2006) (21)
Low power mapping of behavioral arrays to multiple memories (1996) (21)
Modeling and Verification of Pipelined Embedded Processors in the Presence of Hazards and Exceptions (2002) (21)
Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming Applications (2008) (21)
Enabling Resource-Aware Mapping of Spiking Neural Networks via Spatial Decomposition (2020) (21)
Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications (2006) (21)
Exploiting Heterogeneity for Aging-Aware Load Balancing in Mobile Platforms (2017) (21)
FORAY-GEN: automatic generation of affine functions for memory optimizations (2005) (21)
Dynamic common sub-expression elimination during scheduling in high-level synthesis (2002) (21)
Mapping Loops on Coarse-Grain Reconfigurable Architectures Using Memory Operation Sharing (2002) (21)
A Reliability-Aware Address Mapping Strategy for NAND Flash Memory Storage Systems (2014) (21)
Energy-aware system design for wireless multimedia (2004) (21)
Memory Systems and Compiler Support for MPSoC Architectures (2005) (21)
Endurance-Aware Mapping of Spiking Neural Networks to Neuromorphic Hardware (2021) (20)
FORGE: a framework for optimization of distributed embedded systems software (2003) (20)
A data alignment technique for improving cache performance (1997) (20)
Reducing Address Bus Transitions for Low Power Memory Mapping (1996) (20)
Integrating Program Transformations In The Memory-based Synthesis Of Image And Video Algorithms (1994) (20)
Very fast Simulated Annealing for HW-SW partitioning (2004) (20)
Interface synthesis using memory mapping for an FPGA platform (2003) (20)
QuARK: Quality-configurable approximate STT-MRAM cache by fine-grained tuning of reliability-energy knobs (2017) (19)
Functional verification of programmable embedded architectures - a top-down approach (2005) (19)
GSR Analysis for Stress: Development and Validation of an Open Source Tool for Noisy Naturalistic GSR Data (2020) (19)
Processor-memory coexploration using an architecture description language (2004) (19)
Platform-Centric Self-Awareness as a Key Enabler for Controlling Changes in CPS (2018) (19)
A large-scale neural network model of the influence of neuromodulatory levels on working memory and behavior (2013) (19)
REMEDIATE: A scalable fault-tolerant architecture for low-power NUCA cache in tiled CMPs (2013) (18)
Designer Controlled Behavioral Synthesis (1989) (18)
Co-Cap: energy-efficient cooperative CPU-GPU frequency capping for mobile games (2016) (18)
Memory-aware cooperative CPU-GPU DVFS governor for mobile games (2015) (18)
Pain Assessment Tool With Electrodermal Activity for Postoperative Patients: Method Validation Study (2021) (18)
PBExplore: a framework for compiler-in-the-loop exploration of partial bypassing in embedded processors (2005) (18)
High-level library mapping for memories (2000) (18)
Approximation-Aware Coordinated Power/Performance Management for Heterogeneous Multi-cores (2018) (18)
Continuous Non-Invasive Blood Pressure Monitoring: A Methodological Review on Measurement Techniques (2020) (18)
Domain-specific Accelerators for Ideal Lattice-based Public Key Protocols (2018) (18)
Behavioral array mapping into multiport memories targeting low power (1997) (18)
Automated throughput-driven synthesis of bus-based communication architectures (2005) (18)
A Parallelizing Approach to the High-Level Synthesis of Digital Circuits (2004) (17)
VAWOM: Temperature and process variation aware WearOut Management in 3D multicore architecture (2013) (17)
Adaptive low-power address encoding techniques using self-organizing lists (2003) (17)
SOSA: Self-Optimizing Learning with Self-Adaptive Control for Hierarchical System-on-Chip Management (2019) (17)
Compilation framework for code size reduction using reduced bit-width ISAs (rISAs) (2006) (17)
Evaluating Carbon Nanotube Global Interconnects for Chip Multiprocessor Applications (2010) (17)
A User Interface for VHDL Behavioral Modeling (1991) (17)
Edge-Assisted Sensor Control in Healthcare IoT (2018) (17)
Towards reverse engineering the brain: Modeling abstractions and simulation frameworks (2010) (17)
IDAP: a tool for high-level power estimation of custom array structures (2003) (17)
ML-Gov: a machine learning enhanced integrated CPU-GPU DVFS governor for mobile gaming (2017) (16)
Investigation of Machine Learning Approaches for Traumatic Brain Injury Classification via EEG Assessment in Mice (2020) (16)
PBPAIR: an energy-efficient error-resilient encoding using probability based power aware intra refresh (2006) (16)
An Edge-Assisted and Smart System for Real-Time Pain Monitoring (2019) (16)
Minimal sparse observability of complex networks: Application to MPSoC sensor placement and run-time thermal estimation & tracking (2014) (16)
Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability (2008) (16)
CryptoPIM: In-memory Acceleration for Lattice-based Cryptographic Hardware (2020) (16)
Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture (2010) (16)
Cross-layer virtual observers for embedded multiprocessor system-on-chip (MPSoC) (2012) (15)
Single appearance schedule with dynamic loop count for minimum data buffer from synchronous dataflow graphs (2005) (15)
Memory system connectivity exploration (2002) (15)
Evaluating memory architectures for media applications on coarse-grained reconfigurable architectures (2003) (15)
System level power estimation methodology with H.264 decoder prediction IP case study (2007) (15)
Interconnect-Aware Mapping of Applications to Coarse-Grain Reconfigurable Architectures (2004) (15)
Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis (2007) (15)
Gain scheduled control for nonlinear power management in CMPs (2018) (15)
Partially Protected Caches to Reduce Failures Due to Soft Errors in Multimedia Applications (2009) (15)
Computing spike-based convolutions on GPUs (2009) (15)
Coordinated transformations for high-level synthesis of high performance microprocessor blocks (2002) (15)
Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications (2009) (15)
Dynamic Computation Migration at the Edge: Is There an Optimal Choice? (2019) (15)
Register File Power Reduction Using Bypass Sensitive Compiler (2008) (15)
High-Level synthesis with Synchronous and RAMBUS DRAMs (1998) (15)
HDRL: Homogeneous Dual-Rail Logic for DPA Attack Resistive Secure Circuit Design (2012) (15)
Software controlled memory layout reorganization for irregular array access patterns (2007) (15)
Quality Adapted Backlight Scaling (QABS) for Video Streaming to Mobile Handheld Devices (2005) (15)
Aggregating processor free time for energy reduction (2005) (15)
PTL: PCM Translation Layer (2012) (15)
NeuroXplorer 1.0: An Extensible Framework for Architectural Exploration with Spiking Neural Networks (2021) (15)
FPGA emulation and prototyping of a cyberphysical-system-on-chip (CPSoC) (2014) (14)
A top-down methodology for microprocessor validation (2004) (14)
Dynamic Reliability Management in Neuromorphic Computing (2021) (14)
Design synthesis and silicon compilation (1990) (14)
Minimization of Memory Traffic in High-Level Synthesis (1994) (14)
Spiking neuron model of basal forebrain enhancement of visual attention (2012) (14)
RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor (2010) (14)
Pain Recognition With Electrocardiographic Features in Postoperative Patients: Method Validation Study (2021) (14)
Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications (2009) (14)
Context-Aware Sensing via Dynamic Programming for Edge-Assisted Wearable Systems (2020) (14)
Exploring Energy Efficient Quantum-resistant Signal Processing Using Array Processors (2020) (14)
COVID Symptoms, Symptom Clusters, and Predictors for Becoming a Long-Hauler Looking for Clarity in the Haze of the Pandemic (2022) (14)
CAPPS: A Framework for Power–Performance Tradeoffs in Bus-Matrix-Based On-Chip Communication Architecture Synthesis (2010) (14)
HDGM: Hierarchical Dynamic Goal Management for Many-Core Resource Allocation (2018) (14)
Design considerations for limited connectivity vliw architectures (1992) (14)
Exploring efficient operating points for voltage scaled embedded processor cores (2003) (14)
NSF expedition on variability-aware software: Recent results and contributions (2015) (14)
STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs (2007) (14)
Model-based analysis of event-driven distributed real-time embedded systems (2009) (14)
Combining Formal Verification with Observed System Execution Behavior to Tune System Parameters (2007) (13)
On-chip stack based memory organization for low power embedded architectures (2003) (13)
Optimal Application Mapping and Scheduling for Network-on-Chips with Computation in STT-RAM Based Router (2019) (13)
Energy-efficient and Reliable Wearable Internet-of-Things through Fog-Assisted Dynamic Goal Management (2019) (13)
An Efficient and Robust Deep Learning Method with 1-D Octave Convolution to Extract Fetal Electrocardiogram (2020) (13)
Goal-Driven Autonomy for Efficient On-chip Resource Management: Transforming Objectives to Goals (2019) (13)
Youn-Long Steve Lin (1992) (13)
Processor description languages : applications and methodologies (2008) (13)
Access pattern-based memory and connectivity architecture exploration (2003) (12)
Dynamic conditional branch balancing during the high-level synthesis of control-intensive designs (2003) (12)
Satisfying timing constraints of preemptive real-time tasks through task layout technique (2001) (12)
R-TOD: Real-Time Object Detector with Minimized End-to-End Delay for Autonomous Driving (2020) (12)
Synergistic CPU-GPU Frequency Capping for Energy-Efficient Mobile Games (2017) (12)
Exel: A language for interactive behavioral synthesis (1988) (12)
Dependability evaluation of SISO control-theoretic power managers for processor architectures (2017) (12)
Trends, challenges and needs for lattice-based cryptography implementations: special session (2017) (12)
Incorporating compiler feedback into the design of ASIPs (1995) (12)
Long-Term IoT-Based Maternal Monitoring: System Design and Evaluation (2021) (12)
Design methodologies for enabling self-awareness in autonomous systems (2018) (12)
Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions (2003) (12)
pyEDA: An Open-Source Python Toolkit for Pre-processing and Feature Extraction of Electrodermal Activity (2021) (12)
A novel NoC-based design for fault-tolerance of last-level caches in CMPs (2012) (12)
Memory Organization and Exploration for Embedded Systems-on-Silicon (1997) (12)
Methodology for multi-granularity embedded processor power model generation for an ESL design flow (2008) (11)
High-level library mapping for arithmetic components (1996) (11)
Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA) (2004) (11)
Variability-aware memory management for nanoscale computing (2013) (11)
Memory optimizations and exploration for embedded systems (1998) (11)
Architecture description language driven design space exploration in the presence of coprocessors (2001) (11)
Design reuse through high-level library mapping (1995) (11)
Considering run-time reconfiguration overhead in task graph transformations for dynamically reconfigurable architectures (2005) (11)
Constraint Refinement for Online Verifiable Cross-Layer System Adaptation (2008) (11)
Self-Awareness in Cyber-Physical Systems (2016) (11)
A Conservative Approximation Method for the Verification of Preemptive Scheduling Using Timed Automata (2009) (11)
HiCAP: Hierarchical FSM-based Dynamic Integrated CPU-GPU Frequency Capping Governor for Energy-Efficient Mobile Gaming (2016) (11)
DPCS: Dynamic Power/Capacity Scaling for SRAM Caches in the Nanoscale Era (2015) (11)
Flexible NTT Accelerators for RLWE Lattice-Based Cryptography (2019) (11)
Special session: trends, challenges and needs for lattice-based cryptography implementations (2017) (11)
A design space exploration framework for reduced bit-width Instruction Set architecture (rISA) design (2002) (11)
Conquering MPSoC complexity with principles of a self-aware information processing factory (2016) (11)
A Recurrent Neural Network Based Model of Predictive Smooth Pursuit Eye Movement in Primates (2018) (11)
A backlight optimization scheme for video playback on mobile devices (2006) (11)
AVid: Annotation driven video decoding for hybrid memories (2012) (11)
Slack-aware scheduling on Coarse Grained Reconfigurable Arrays (2011) (10)
Cross-layer co-exploration of exploiting error resilience for video over wireless applications (2008) (10)
Sparse coding and dimensionality reduction in cortex (2017) (10)
Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures (2007) (10)
Software Annotations for Power Optimization on Mobile Devices (2006) (10)
Inter-kernel data reuse and pipelining on chip-multiprocessors for multimedia applications (2009) (10)
PoliMakE: a policy making engine for secure embedded software execution on chip-multiprocessors (2010) (10)
Automatic validation of pipeline specifications (2001) (10)
Memory Architectures for Embedded Systems-On-Chip (2002) (10)
Prospective Study Evaluating a Pain Assessment Tool in a Postoperative Environment: Protocol for Algorithm Testing and Enhancement (2020) (10)
Towards Automatic Validation of Dynamic Behavior in Pipelined Processor Specifications (2003) (10)
Exploring computation offloading in IoT systems (2021) (10)
Annotation Based Multimedia Streaming Over Wireless Networks (2006) (10)
Policy Construction and Validation for Energy Minimization in Cross Layered Systems : A Formal Method Approach (2006) (10)
Software and Hardware Implementation of Lattice-Cased Cryptography Schemes (2017) (10)
SPMPool: Runtime SPM Management for Memory-Intensive Applications in Embedded Many-Cores (2016) (10)
Personalized Stress Monitoring using Wearable Sensors in Everyday Settings (2021) (10)
Small Memory Footprint Neural Network Accelerators (2019) (10)
System and architecture-level power reduction of microprocessor-based communication and multi-media applications (2000) (9)
Automatic management of Software Programmable Memories in Many-core Architectures (2016) (9)
Retargetable pipeline hazard detection for partially bypassed processors (2006) (9)
Trustworthy AI Inference Systems: An Industry Research View (2020) (9)
Hierarchical dynamic goal management for IoT systems (2018) (9)
Specification-driven validation of programmable embedded systems (2004) (9)
SURF: Self-aware Unified Runtime Framework for Parallel Programs on Heterogeneous Mobile Architectures (2019) (9)
Sense-making from distributed and mobile sensing data: A middleware perspective (2014) (9)
Accuracy-Aware Power Management for Many-Core Systems Running Error-Resilient Applications (2017) (9)
SEAMS (2021) (9)
Memory-aware NoC Exploration and Design (2008) (9)
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures (2008) (9)
Design Methodology for Responsive and Rrobust MIMO Control of Heterogeneous Multicores (2018) (9)
Automatic Design Space Exploration of Register Bypasses in Embedded Processors (2007) (9)
Detection of COVID-19 Using Heart Rate and Blood Pressure: Lessons Learned from Patients with ARDS (2020) (9)
Hierarchical adaptive Multi-objective resource management for many-core systems (2019) (9)
ExCCel: Exploration of complementary cells for efficient DPA attack resistivity (2010) (8)
CHIPS-AHOy: a predictable holistic cyber-physical hypervisor for MPSoCs (2018) (8)
Shift buffering technique for automatic code synthesis from synchronous dataflow graphs (2005) (8)
Efficient power reduction techniques for time multiplexed address buses (2002) (8)
TRAM: A tool for Temperature and Reliability Aware Memory Design (2009) (8)
Cross-Abstraction Functional Verification and Performance Analysis of Chip Multiprocessor Designs (2009) (8)
A Semantic Framework for Reconfiguration of Instrumented Cyber Physical Spaces (2007) (8)
Software Controlled Memories for Scalable Many-Core Architectures (2012) (8)
Modeling and analysis of fault-tolerant distributed memories for Networks-on-Chip (2013) (8)
GPGPU accelerated simulation and parameter tuning for neuromorphic applications (2014) (8)
Verification of in-order execution in pipelined processors (2000) (8)
Neuromorphic modeling abstractions and simulation of large-scale cortical networks (2011) (8)
An algorithm for the allocation of functional units from realistic RT component libraries (1994) (8)
Towards practical high-level synthesis from large behavioral descriptions (2010) (8)
Reducing compilation time overhead in compiled simulators (2003) (8)
Cross-Layer Exploration of Heterogeneous Multicore Processor Configurations (2015) (8)
A first look at the interplay of code reordering and configurable caches (2005) (7)
A framework for memory-aware multimedia application mapping on chip-multiprocessors (2008) (7)
Architecture Description Languages (2007) (7)
Accelerating Brain Circuit Simulations of Object Recognition with a Sony PlayStation 3 (2007) (7)
Quality-configurable memory hierarchy through approximation: special session (2017) (7)
On detecting and using memory phases in multimedia systems (2016) (7)
Relaxing Manufacturing Guard-bands in Memories for Energy Saving (2014) (7)
Tuning Caches to Applications for Low-Energy Embedded Systems (2004) (7)
System level performance analysis of carbon nanotube global interconnects for emerging chip multiprocessors (2008) (7)
Equivalent design representations and transformations for interactive scheduling (1992) (7)
Automatic generation of operation tables for fast exploration of bypasses in embedded processors (2006) (7)
Managing Cross-Layer Constraints for Interactive Mobile Multimedia∗ (2003) (7)
The GENUS User Manual and C Programming Library (1993) (7)
On the feasibility of SISO control-theoretic DVFS for power capping in CMPs (2018) (7)
Self-Adaptive Memory Approximation: A Formal Control Theory Approach (2020) (7)
Personal mental health navigator: Harnessing the power of data, personal models, and health cybernetics to promote psychological well-being (2020) (7)
The Information Processing Factory: A Paradigm for Life Cycle Management of Dependable Systems (2019) (7)
Synthesis of Flexible Accelerators for Early Adoption of Ring-LWE Post-quantum Cryptography (2020) (7)
DynaPoMP: dynamic policy-driven memory protection for SPM-based embedded systems (2011) (7)
A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures (2008) (7)
Floorplan driven leakage power aware IP-based SoC design space exploration (2006) (7)
SPMCloud: Towards the Single-Chip Embedded ScratchPad Memory-Based Storage Cloud (2014) (7)
ViPZonE: Hardware Power Variability-Aware Virtual Memory Management for Energy Savings (2015) (7)
Edge-Assisted Control for Healthcare Internet of Things (2020) (6)
Harmonic scheduling of linear recurrences for digital filter design (1992) (6)
New directions in compiler technology for embedded systems (embedded tutorial) (2001) (6)
Architecture Description Language driven Functional Test Program Generation for Microprocessors using SMV (2003) (6)
Code size reduction in heterogeneous-connectivity-based DSPs using instruction set extensions (2005) (6)
ARGA: Approximate Reuse for GPGPU Acceleration (2019) (6)
Partitioning techniques for partially protected caches in resource-constrained embedded systems (2010) (6)
Energy analysis of multimedia watermarking on mobile handheld devices (2005) (6)
HCI and mHealth Wearable Tech: A Multidisciplinary Research Challenge (2020) (6)
Encoding Techniques for On-Chip Communication Architectures (2008) (6)
Using a Flexible Fault-Tolerant Cache to Improve Reliability for Ultra Low Voltage Operation (2015) (6)
BIF : a behavioral intermediate format for high level synthesis (1989) (6)
An Experimental Study on Energy Consumption of Video Encryption for Mobile Handheld Devices (2005) (6)
Cooperative On-Chip Temperature EstimationUsing Multiple Virtual Sensors (2015) (6)
A method for register allocation to loops in multiple register file architectures (1996) (6)
An empirical study on the effects of physical design in high-level synthesis (1994) (6)
High-Level Synthesis with SDRAMs and RAMBUS DRAMs (Special Section on VLSI Design and CAD Algorithms) (1999) (6)
Classification of Electroencephalogram in a Mouse Model of Traumatic Brain Injury Using Machine Learning Approaches* (2020) (6)
Generic Processor Modeling for Automatically Generating Very Fast Cycle-Accurate Simulators (2006) (6)
Novel Blood Pressure Waveform Reconstruction from Photoplethysmography using Cycle Generative Adversarial Networks (2022) (6)
Memory Subsystem Description in EXPRESSION (2000) (6)
HESSLE-FREE (2019) (5)
Thermal sensor allocation for SoCs based on temperature gradients (2015) (5)
Protecting caches against multi-bit errors using embedded erasure coding (2015) (5)
CAST: Content-Aware STT-MRAM Cache Write Management for Different Levels of Approximation (2020) (5)
PoliCym: Rapid Prototyping of Resource Management Policies for HMPs (2017) (5)
Goal Formulation: Abstracting Dynamic Objectives for Efficient On-chip Resource Allocation (2018) (5)
Proxy-based task partitioning of watermarking algorithms for reducing energy consumption in mobile devices (2004) (5)
A Study of Out-of-Order Completion for the MIPS R10K Superscalar Processor (2001) (5)
Adaptive-reflective middleware for power and energy management in many-core heterogeneous systems (2019) (5)
LEGEND: a language for generic component library description (1990) (5)
Automatic Instruction Set Design Through Efficient Instruction Encoding for Application-Specific Processors (2003) (5)
Coprocessor Codesign for Programmable Architectures (2001) (5)
Multicopy Cache: A Highly Energy-Efficient Cache Architecture (2014) (5)
MEMCOP: memory-aware co-operative power management governor for mobile games (2018) (5)
Customizing Software Toolkits for Embedded Systems-On-Chip (2000) (5)
A Methodology for Power-aware Pipelining via High-Level Performance Model Evaluations (2009) (5)
Brain Derived Vision Algorithm on High Performance Architectures (2009) (5)
A Property Checking Approach to Microprocessor Verification using Symbolic Simulation (2002) (5)
A Fast Area-Delay Estimation Technique ,,,.-for RTL Component Generator~ (1992) (5)
Fast Automated Generation of High-Quality Instruction Set Extensions for Processor Customization (2004) (5)
Content-aware Power Optimizations for Multimedia Streaming Over Wireless Networks (2006) (5)
A hypergraph-based model for port allocation on multiple-register-file VLIW architectures (1995) (5)
Reclocking for high-level synthesis (1995) (5)
Data Reuse Driven Memory and Network-On-Chip Co-Synthesis (2007) (5)
P2E-WGAN: ECG waveform synthesis from PPG with conditional wasserstein generative adversarial networks (2021) (5)
The Causality Inference of Public Interest in Restaurants and Bars on Daily COVID-19 Cases in the United States: Google Trends Analysis (2021) (5)
Enabling heterogeneous cycle-based and event-driven simulation in a design flow integrated using the SPIRIT consortium specifications (2007) (5)
A Representation for the Binding of RT-Component Functionality to HDL Behavior (1993) (5)
LRCG: latch-based random clock-gating for preventing power analysis side-channel attacks (2012) (5)
Using Multimodal Assessments to Capture Personalized Contexts of College Student Well-being in 2020: Case Study (2020) (5)
The Case for Exploiting Underutilized Resources in Heterogeneous Mobile Architectures (2019) (5)
Compilation Approach for Coarse-Grained Reconfigurable (2003) (5)
A methodology for accurate modeling of energy dissipation in array structures (2003) (5)
Novel Brain-Derived Algorithms Scale Linearly with Number of Processing Elements (2007) (5)
SEAMS: Self-Optimizing Runtime Manager for Approximate Memory Hierarchies (2021) (4)
High-Level Synthesis of Scalable Architectures for IIR Filters Using Multichip Modules (1993) (4)
Dynamic iFogSim: A Framework for Full-Stack Simulation of Dynamic Resource Management in IoT Systems (2020) (4)
System-level PVT variation-aware power exploration of on-chip communication architectures (2009) (4)
Fast Exploration of Bus-Based On-Chip Communication Architectures (2004) (4)
Electronic system-level design and high-level synthesis (2009) (4)
Energy-Efficient Adaptive System Reconfiguration for Dynamic Deadlines in Autonomous Driving (2021) (4)
Self-Awareness for Autonomous Systems (2020) (4)
Online Learning for Orchestration of Inference in Multi-user End-edge-cloud Networks (2022) (4)
Greedy and Heuristic-based Algorithms for Synthesis of Complex Instructions in Heterogeneous-Connectivity-based DSPs (2003) (4)
SAM: Software-Assisted Memory Hierarchy for Scalable Manycore Embedded Systems (2017) (4)
Optimizing Energy Efficiency of Wearable Sensors Using Fog-assisted Control (2019) (4)
Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends (2007) (4)
A distinct symptom pattern emerges for COVID-19 long-haul: a nationwide study (2022) (4)
Video Stream Annotations for Energy Trade-offs in Multimedia Applications (2006) (4)
Embodied Self-Aware Computing Systems (2020) (4)
NoC-based fault-tolerant cache design in chip multiprocessors (2014) (4)
ShaVe-ICE (2018) (4)
Assessing the Mental Health of Emerging Adults Through a Mental Health App: Protocol for a Prospective Pilot Study (2021) (4)
Translating BIF into VHDL : algorithms and examples (1990) (4)
Partially-Forgetful Memories : Relaxing Memory Guard-bands for Approximate Computing (2015) (4)
Design space exploration and parameter tuning for neuromorphic applications (2013) (4)
Specification of Hazards, Stalls, Interrupts, and Exceptions in EXPRESSION (2001) (4)
Minimization of Memory Tra c in High-Level Synthesis (1995) (4)
Error-Aware Algorithm/Architecture Coexploration for Video Over Wireless Applications (2012) (4)
A Framework for Memory and Communication Architecture Co-synthesis in MPSoCs (2006) (4)
Assessing Mental Health in Emerging Adulthood through a Mental Health Navigator: A Study Protocol. (2021) (4)
Towards Embedded RAIDs-on-Chip (2011) (3)
Efficient Search Space Exploration for HW-SW Partitioning (2004) (3)
RT Component Sets for High-Level Design Applications (1997) (3)
Energy-Aware Adaptations for End-to-End Videostreaming to Mobile Handheld Devices (2004) (3)
Trends in On-chip Dynamic Resource Management (2018) (3)
ServiceFORGE : A Software Architecture for Power and Quality Aware Services (2003) (3)
A novel wireless ECG system for prolonged monitoring of multiple zebrafish for heart disease and drug screening studies. (2021) (3)
Embedded RAIDs-on-chip for bus-based chip-multiprocessors (2014) (3)
Exploring scalable schedules for IIR filters with resource constraints (1999) (3)
Orchestrated application quality and energy storage management in solar-powered embedded systems (2015) (3)
Reclocking Controllers for Minimum Execution Time (1995) (3)
Exploring Hybrid Memory Caches in Chip Multiprocessors (2018) (3)
Functional validation of programmable architectures (2004) (3)
Data Partitioning Techniques for Partially Protected Caches to Reduce Soft Error Induced Failures (2008) (3)
Partitioning of Variables for Multiple-Register-File Architectures via Hypergraph Coloring (1994) (3)
On-Chip Dynamic Resource Management (2019) (3)
Nine Months in the Life of a College Student During 2020: A Case Study Using Multi-Modal Assessments to Capture Personalized Contexts of Well-being (2020) (3)
FIFO power optimization for on-chip networks (2004) (3)
Networks-On-Chip (2008) (3)
On chip Communication-Architecture Based Thermal Management for SoCs (2009) (3)
Partitioning of Variables for Multiple-Register-File VLIW Architectures (1994) (3)
Self-aware Memory Management for Emerging Energy-efficient Architectures (2020) (3)
Cooperative CPU-GPU Frequency Capping ( Co-Cap ) for Energy Efficient Mobile Gaming (2015) (3)
Combining code reordering and cache configuration (2012) (3)
The Information Processing Factory: Organization, Terminology, and Definitions (2019) (3)
Basic Concepts of Bus-Based Communication Architectures (2008) (3)
Functional and Timing Validation of Partially Bypassed Processor Pipelines (2007) (3)
High Level Design Space Exploration of Shared Bus Communication Architectures (2004) (3)
Domain-Specific Modeling of Power Aware Distributed Real-Time Embedded Systems (2006) (3)
Compiler-in-the-loop exploration of programmable embedded systems (2006) (3)
Towards Embedded RAIDs-on-Chip (2011) (3)
ESL hand-off: Fact or EDA fiction? (2008) (3)
EAVE: Error-Aware Video Encoding Supporting Extended Energy/QoS Trade-offs for Mobile Embedded Systems (2012) (3)
A Framework for Memory Subsystem Exploration (2002) (3)
VISA synthesis: Variation-aware Instruction Set Architecture synthesis (2013) (3)
Architecture Description Language driven Validation of Processor , Memory , and Co-Processor Pipelines (3)
An advanced course design for mobile embedded software through Android programming (2012) (3)
Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips (2008) (3)
The effects of variations in component styles and shapes on high-level synthesis (1992) (3)
Using Annotations to Facilitate Power vs Quality Trade-offs in Streaming Applications ∗ (2005) (3)
HDLGen : Architecture Description Language driven HDL Generation for Pipelined Processors (2003) (3)
A Standard Cell-Based DPA Attack Countermeasure using Homogeneous Dual-Rail Logic ( HDRL ) (2012) (2)
Workload Characterization for Memory Management in Emerging Embedded Platforms (2019) (2)
The Self-Aware Information Processing Factory Paradigm for Mixed-Critical Multiprocessing (2022) (2)
ISEGEN: Adapting Kerninghan-Lin Min-Cut Heuristic for Generation of Instruction Set Extensions (2004) (2)
Data Reuse for Accelerated Approximate Warps (2020) (2)
A generalized technique for energy-efficient operating voltage set-up in dynamic voltage scaled processors (2005) (2)
Towards More Realistic Physical Design Models for High-Level Synthesis (1993) (2)
MARS: Middleware for Adaptive Reflective Computer Systems (2021) (2)
The Causality Inference of Public Interest in Restaurants and Bars on COVID-19 Daily Cases in the US: A Google Trends Analysis (2020) (2)
Architecture Description Language driven Validation of Dynamic Behavior in Pipelined Processor Specifications (2003) (2)
Philosoftware: a low power, high performance, reliable, and secure virtualization layer for on-chip software-controlled memories (2012) (2)
Intelligent Management of Mobile Systems through Computational Self-Awareness (2020) (2)
Virtualizing on-chip distributed ScratchPad memories for low power and trusted application execution (2013) (2)
Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units (2010) (2)
MultiMaKe: Chip-multiprocessor driven memory-aware kernel pipelining (2013) (2)
How to solve the current memory access and data transfer bottlenecks: at the processor architecture or at the compiler level? (2000) (2)
Chauffeur: Benchmark Suite for Design and End-to-End Analysis of Self-Driving Vehicles on Embedded Systems (2021) (2)
Compiler-Architecture Exploration using Reservation Tables Generation (1999) (2)
Aggressive Memory-Aware Compilation (2000) (2)
Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures (2009) (2)
CAPPS : A Framework for Power-Performance Trade-Offs in On-Chip Communication Architecture Synthesis ∗ (2006) (2)
SPMPool (2016) (2)
DPCS (2015) (2)
TrustGeM: Dynamic trusted environment generation for chip-multiprocessors (2011) (2)
Vision-inspired global routing for enhanced performance and reliability (2013) (2)
Towards Smart and Efficient Health Monitoring Using Edge-enabled Situational-awareness (2021) (2)
Automated Synthesis of Bus Architectures for Systems with Throughput Constraints (2004) (2)
Special session: quality-configurable memory hierarchy through approximation (2017) (2)
Cross-layer virtual/physical sensing and actuation for resilient heterogeneous many-core SoCs (2016) (2)
Specification of Timing Constraints in VHDL for High-Level Synthesis (1994) (2)
AMSER: Adaptive Multimodal Sensing for Energy Efficient and Resilient eHealth Systems (2021) (2)
193 Sleep Variability and Affect Dynamics Among College Students during COVID-19 Pandemic (2021) (2)
Analyzing and Exploring Fault-tolerant Distributed Memories for NoCs (2013) (2)
Center for Embedded Computer Systems University of California , Irvine Cross-Layer Interactions of Error Control Schemes in Mobile Multimedia Systems (2008) (2)
Proceedings of the 4th Design Automation Conference (2011) (2)
On-Chip Communication Architecture Standards (2008) (2)
Investigation of Machine Learning and Deep Learning Approaches for Detection of Mild Traumatic Brain Injury from Human Sleep Electroencephalogram (2021) (2)
A Micro-Level Analysis of Physiological Responses to COVID-19: Continuous Monitoring of Pregnant Women in California (2022) (2)
A Reliable, Safe, and Secure Run-Time Platform for Cyber Physical Systems (2013) (2)
CARLsim 6: An Open Source Library for Large-Scale, Biologically Detailed Spiking Neural Network Simulation (2022) (2)
Probability based power aware error resilient coding (2005) (2)
Accelerating Brain Circuit Simulations of Object Recognition with CELL Processors (2007) (2)
Hybrid Learning for Orchestrating Deep Learning Inference in Multi-user Edge-cloud Networks (2022) (2)
Title An efficient automated parameter tuning framework for spiking neural networks (2014) (1)
PBPAIR : Probability Based Power Aware Intra Refresh A New Energy-efficient Error-resilient Encoding Scheme * (2005) (1)
A methodology for validation of microprocessors using equivalence checking (2003) (1)
Architectural Models in Synthesis (1992) (1)
Modeling of Software-Hardware Complexes (2007) (1)
Work-in-progress: exploring fast and slow memories in HMP core types (2017) (1)
A Case for an Adaptive and Opportunistic Variability- Aware Memory Virtualization Layer (2011) (1)
On-Chip vs. Off-Chip Memory: Utilizing Scratch-Pad Memory (1999) (1)
Behavioral modeling of DRACO : a peripheral interface ASIC (1990) (1)
Power estimation of low-power high-performance memory structures (2004) (1)
Acceleration beyond memory barriers in is-extensible processors (2006) (1)
Keynote speach (2012) (1)
Digital Health–Enabled Community-Centered Care: Scalable Model to Empower Future Community Health Workers Using Human-in-the-Loop Artificial Intelligence (2021) (1)
Flexible and Personalized Learning for Wearable Health Applications using HyperDimensional Computing (2022) (1)
Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs (2004) (1)
NeuSB: A Scalable Interconnect Architecture for Spiking Neuromorphic Hardware (2023) (1)
Live demonstration: Computing spike-based convolutions on GPUs (2009) (1)
DNN-Assisted Sensor for Energy-Efficient ECG Monitoring (2019) (1)
Using HSFMs to Model Mobile Gaming Behavior for Energy Efficient DVFS Governors (2016) (1)
A Technology-Based Pregnancy Health and Wellness Intervention (Two Happy Hearts): Case Study (2021) (1)
SOSA (2019) (1)
A Compound Information Model for High-Level Synthesis (1995) (1)
WEARABLE INTERNET-OF-THINGS TECHNOLOGY: AN IMMIGRANT DEMENTIA CAREGIVERS PILOT INTERVENTION (2019) (1)
Exploring fast and slow memories in HMP core types: work-in-progress (2017) (1)
STINT: selective transmission for low-energy physiological monitoring (2020) (1)
Design Reuse: Fact or Fiction? (Panel) (1994) (1)
Power-Aware Multimedia Streaming in Heterogeneous Multi-User Environments ∗ (2003) (1)
Minimizing peak power for application chains on architectures with partial dynamic reconfiguration (2006) (1)
Introduction to Architecture Description Languages (2008) (1)
Guest Editorial: Special Issue on Self-Aware Systems on Chip (2017) (1)
Behavioral modeling of the Intel 8255A/8255A-5 programmable peripheral interface (1991) (1)
SPM-vSharE : Memory Management in SPM-based Many-core Embedded Systems (2016) (1)
On linking RT-component functionality to abstract HDL behavior (1993) (1)
Selecting granularity of parallelism for tasks executing on dynamically reconfigurable architectures (2006) (1)
Exercise and Stress in At-Risk Women during Pregnancy and Postpartum. (2021) (1)
Exploring Energy Efficient Architectures for RLWE Lattice-Based Cryptography (2021) (1)
Trends in Emerging On-Chip Interconnect Technologies (IPSJ Transactions on System LSI Design Methodology Vol.1) (2008) (1)
Bus Matrix Communication Architecture Synthesis (2005) (1)
EXTEND-L : an input language for extensible register transfer compilation (1988) (1)
Empowering autonomy through self-awareness in MPSoCs (2017) (1)
Memory Data Organization for Low-Energy Address Buses (2004) (1)
Combining Transaction-level Simulations and Model Checking for MPSoC Verification and Performance Evaluation (2009) (1)
EXPRESSION User Manual version 1.0 (2003) (1)
Adaptive reduced bit-width Instruction Set Architecture (adapt-rISA) (2009) (1)
Low Overhead DPA Countermeasure using ExCCel (Exploration of Complementary Cells) (2010) (1)
Co-optimization of Streaming Multimedia QOS and Backlight Power Consumption for Mobile Handheld Devices (2003) (1)
The Two Happy Hearts Technology-based Pregnancy Health and Wellness Intervention in California: Case Study (Preprint) (2021) (1)
A methodology for validation of microprocessors using symbolic simulation (2005) (1)
Design reuse (panel): fact or fiction (1994) (1)
Harmonic Scheduling: A Technique for Scheduling beyond Loop-Carried Dependencies (1993) (1)
Redundancy-aware Design Space Exploration for Memory Reliability in Many-cores (2017) (1)
Design Representation and Transformations (1992) (1)
Synthesis of Instruction Sets for High-Performance and Energy-Efficient ASIP (2007) (1)
HAMEX: heterogeneous architecture and memory exploration framework (2016) (1)
Emergent Control of MPSoC Operation by a Hierarchical Supervisor / Reinforcement Learning Approach (2020) (1)
Chapter 14 ENERGY-AWARE ADAPTATIONS FOR END-TO-END VIDEO STREAMING TO MOBILE HANDHELD DEVICES (2004) (1)
ILP-Based Program Path Analysis for Bounding Worst-Case Inter-Task Cache Conflicts (2004) (1)
Compiler-inthe-Loop ADL-driven Early Architectural Exploration ∗ (2005) (1)
Emerging On-Chip Interconnect Technologies (2008) (1)
A Formal Methodology for Compositional Cross-Layer Optimization (2011) (1)
A Model-Based Approach to System Specification for Distributed Real-time and Embedded Systems * (2004) (1)
Functional verification of pipelined processors: a case study (2004) (1)
Performance Enhancement of Desktop Multimedia with Multithreaded Extensions to A General Purpose Superscalar Microprocessor (1998) (1)
Reflecting on Self-Aware Systems-on-Chip (2020) (1)
Allocation of Functional Units from Realistic Component Libraries (1993) (1)
Floorplan-aware Bus Architecture Synthesis (2004) (1)
Proceedings of the 7th ACM International Workshop on Mobile Video (2015) (1)
Virtualizing on-chip distributed ScratchPad memories for low power and trusted application execution (2013) (1)
Architecture and Cross-Layer Design Space Exploration (2017) (0)
Editorial (2008) (0)
Compiler Aided Design of Embedded Computers (2007) (0)
Introduction to Special Issue on Cross-layer Dependable Embedded Systems (2014) (0)
Programme Topic Chairs (1998) (0)
A 1 SPM 0 Core 0 A 1 SPM 3 Core 3 Page SPM 2 Core 2 Page App SPM 1 Core 1 (2014) (0)
Exploring Heterogeneous Task-Level Parallelism in a BMA Video Coding Application using System-Level Simulation (2018) (0)
Inter and intra kernel reuse analysis driven pipelining on Chip-Multiprocessors (2010) (0)
CODES+ISSS 2007 guest editors’ introduction (2009) (0)
Cross-Layer Co-Exploration of Exploiting E Over Wireless Applicati (2009) (0)
Organizing and Program Committee (1996) (0)
Copy Elimination for Parallelizing Compilers (1998) (0)
Introduction to the Speical Issue on Self-Awareness in Resource Constrained CPS (0)
1 A Framework for GUI-driven Design Space Exploration of a MIPS 4 K-like processor † (2003) (0)
Reclocking for high level synthesis (1995) (0)
Xtune: a formal methodology for cross-layer tuning of mobile real-time embedded systems (2008) (0)
Demand Layering for Real-Time DNN Inference with Minimized Memory Usage (2022) (0)
2009 List of Reviewers (2009) (0)
Visual response properties of MSTd emerge from a sparse population code (2017) (0)
Benchmarking and the Art of Syntesis Tool Comparison (1992) (0)
ProSwap: Period-aware Proactive Swapping to Maximize Embedded Application Performance (2022) (0)
MEMCOP: memory-aware co-operative power management governor for mobile games (2018) (0)
Session details: Embedded processor and MPSoC design (2007) (0)
Ultra fine-grain template-driven synthesis (1994) (0)
Data Organization: The Processor Core/Cache Interface (1999) (0)
Session details: High-level synthesis and IP protection (2008) (0)
Predicting Failures in Embedded Systems Using Long Short-Term Inference (2021) (0)
Robust Face Recognition Against Soft-errors Using a Cross-layer Approach (2016) (0)
A Unified Power Management Framework for Distributed Video Streaming to Mobile Devices (2004) (0)
Composing Graphical Models with Generative Adversarial Networks for EEG Signal Modeling (2022) (0)
Tutorial T6: Variability-resistant Software and Hardware for Nano-Scale Computing (2012) (0)
Mitigating the Impact of Hardware Failures on Multimedia Applications – A Cross-Layer Approach (2008) (0)
Embedded memories in system design - from technology to systems architecture (1998) (0)
Cooperative cross-layer protection for resource constrained mobile multimedia systems (2008) (0)
Verification and Security Issues in On-Chip Communication Architecture Design (2008) (0)
FABSYN: Floorplan-aware bus architecture synthesis - eScholarship (2006) (0)
Introduction of Local Memory Elements in Synthesis of Instruction Set Extensions (2003) (0)
cpsoc-codes+isss2014-splsession (2015) (0)
An Introduction to the Plasma Language (2005) (0)
On-Chip Optical Ring Bus Communication Architecture for Heterogeneous MPSoC (2013) (0)
COPPER: COMPILER-CONTROLLED ON-DEMAND APPROACH TO POWER-EFFICIENT COMPUTING (2003) (0)
Resilient dependable cyber-physical systems: a middleware perspective (2012) (0)
Editorial (2007) (0)
Session details: Issues in partitioning & design space eploration for codesign (2003) (0)
Memory Resiliency Invited Paper in Special Session Resiliency: Approaches for the Next Decade" (2014) (0)
ARGA (2019) (0)
2009 EDAA PhD Forum at DATE (2009) (0)
Temperature aware vlsi design for reduced power and reliability enhancement (2009) (0)
Design transformations for system level models (2006) (0)
Distributed Multimedia Streaming in a Heterogeneous Environment ∗ (2003) (0)
Case Study: MPEG Decoder (1999) (0)
Introduction to the Special Issue on Self-Aware Cyber-physical Systems (2020) (0)
Editorial (2008) (0)
Introduction to special section SCPS'09 (2012) (0)
W Operating System DVS Scheduler Network Management Transcoding Admission Control Applications Video Player Other Tasks Middleware (2003) (0)
Editorial (2006) (0)
Application mapping for platform fpgas with partial dynamic reconfiguration (2007) (0)
High-Level Synthesis of Scalable Architectures for IIR Filters Using Parameterized MCM ' s y Haigeng (1992) (0)
Quality-Configurable Memory Hierarchy Through Approximation Conference (2017) (0)
Operation Tables for Scheduling in the Presence of Incomplete Bypassing (2004) (0)
Editorial (2005) (0)
Annotation Integration and Trade-off Analysis for Multimedia Applications (2007) (0)
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007 (2007) (0)
QoS-aware dynamic power management for coarse-grained reconfigurable architecture (2009) (0)
Off-Chip Memory Access Optimizations (1999) (0)
Guest editorial 11th international symposium on system-level synthesis and design (ISSS'98) (2000) (0)
On-Chip Dynamic Resource Managemen (2019) (0)
PBExplore : A Compiler-inthe-Loop Framework for Design Space Exploration of Partially Bypassed Processor Pipelines User Manual Version 1 . 0 01 / 15 / 2008 (2008) (0)
Context-Aware Stress Monitoring using Wearable and Mobile Technologies in Everyday Settings (2023) (0)
Quo vadis, BTSoC (Billion Transistor SoC)? (2008) (0)
Scheduling for design reuse of datapath components (1994) (0)
Using FORAY Models to Enable MPSoC Memory Optimizations (2008) (0)
Objective Prediction of Tomorrow’s Affect Using Multi-Modal Physiological and Behavioral Data: A 12-month Study on College Students (Preprint) (2022) (0)
An Interpretable Machine Learning Model Enhanced Integrated CPU-GPU DVFS Governor (2021) (0)
Latency System Throughput Resource Utilization Power and Energy Life-time Reliability Thermal Stability Performance Driven Throughput Driven Lifetime Reliability Driven Varying Workload and User Demands Time Goal System Aberrations and Constraints Hierarchical Dynamic Goal (2017) (0)
AXES: Approximation Manager for Emerging Memory Architectures (2020) (0)
Multi-Layer Memory Resiliency Invited Paper in Special Session "Embedded Resiliency: Approaches for the Next Decade" (2014) (0)
Design Considerations for Limited Connectivity (2015) (0)
Sleep Patterns and Affect Dynamics Among College Students during COVID-19 Pandemic (Preprint) (2021) (0)
STINT (2020) (0)
On-Chip Communication Architecture Refinement and Interface Synthesis (2008) (0)
Editorial (2008) (0)
PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors (2008) (0)
Parade: power analysis resistive architecture design (2012) (0)
FOR EMBEDDED & CYBER-PHYSICAL SYSTEMS Software and Hardware Implementation of Lattice-based Cryptography Schemes (2018) (0)
On the rapid prototyping and design of a wireless communication system on a chip (abstract only) (1999) (0)
Locate: Low-Power Viterbi Decoder Exploration using Approximate Adders (2023) (0)
Custom Bus-Based On-Chip Communication Architecture Design (2008) (0)
Session details: Software-driven techniques for energy efficiency in embedded and multi-core systems (2012) (0)
Heat-aware transmission strategies (2015) (0)
IDAP: a tool for high level power estimation of custom array structures (2003) (0)
Session details: Application specific architecture design tools (2005) (0)
Effect of Soft Errors in Iterative Learning Control and Compensation using Cross-layer Approach (2019) (0)
JJarmonic Scheduling of Linear Recurrences in Digital Filter Design ___ (2015) (0)
Characterization of GPGPU Workloads via Correlation-Driven Kernel Similarity Analysis (2013) (0)
MultiMaKe : Chip-Multiprocessor Driven Memory-aware Kernel (2011) (0)
Regular schedules for scalable design of IIR filters (1993) (0)
Driving agenda for systems research (2003) (0)
Prospective Study Evaluating a Pain Assessment Tool in a Postoperative Environment: Protocol for Algorithm Testing and Enhancement (Preprint) (2020) (0)
Annotation Integration andTrade-off Analysis forMultimedia Applications (2007) (0)
Exploiting Heterogeneous Mobile Architectures Through a Unified Runtime Framework (2019) (0)
EASYR: Energy-Efficient Adaptive System Reconfiguration for Dynamic Deadlines in Autonomous Driving on Multicore Processors (2022) (0)
The power impact of hardware and software actuators on self-adaptable many-core systems (2019) (0)
1 P Ports P Ports 2 P Portsk Mem 1 Mem 2 Mem k Functional Unit MUnit 1 Functional (0)
Edge-centric Optimization of Multi-modal ML-driven eHealth Applications (2022) (0)
Processor Modeling and Design Tools (2016) (0)
Processor Stew (2009) (0)
Pregnant in a Pandemic: Connecting Perceptions of Uplifts and Hassles to Mental Health. (2022) (0)
Analytical Models for Leakage Power Estimation of Memory Array Structures (2004) (0)
Architecture exploration of parameterizable EPIC SOS architectures (poster paper) (2000) (0)
Microarchitecture-Level SoC Design (2017) (0)
Warp Lockstep Warp Bottleneck L Multi Lookup Table In Parallel Dynamic Table with LRU Warp Passthrough ARGA SolutionsExisting Limitations Speedup Wrap Balance High Hitrate (2019) (0)
Outlook for many-core systems: Cloudy with a chance of virtualization (2013) (0)
Using a Flexible Fault-Tolerant Cache ( FFT-Cache ) to Improve Reliability in Ultra Low Voltage Operation (2011) (0)
An Embedded Hybrid-Memory-Aware Virtualization Layer for Chip-Multiprocessors (2012) (0)
Real-time analysis of resource-constrained distributed systems by simulation-guided model checking (2008) (0)
Memory Architecture Exploration (1999) (0)
Efficient Spiking Neural Network Model of Pattern Motion Selectivity in Visual Cortex (2014) (0)
EE382V: System-on-a-Chip (SoC) Design (2014) (0)
Hyperdimensional Hybrid Learning on End-Edge-Cloud Networks (2022) (0)
Optimizing Program Performance via Similarity, Using Feature-aware and Feature-agnostic Characterization Approaches (2013) (0)
MultiMaKe (2013) (0)
DEPUTYEDITOR-IN-CHIEF (2014) (0)
Session details: Memory management and address optimization in embedded systems (2002) (0)
UC Irvine UC Irvine Previously Published Works Title An efficient automated parameter tuning framework for spiking neural networks (2014) (0)
Self-Awareness for Heterogeneous MPSoCs: A Case Study using Adaptive, Reflective Middleware (2018) (0)
Techical Program Co-Chairs' Message (2004) (0)
Enabling Resource-Aware Compilation of Spiking Neural Networks to Neuromorphic Hardware (2020) (0)
Design Description Languages (1992) (0)
A language for designer controlled behavioral synthesis (1993) (0)
Session details: Session 9B: Power issues in high level synthesis (2001) (0)
Best ways to use billions of devices on a chip: panel (2008) (0)
Data Organization Exploration for Low-Energy Address Buses (2003) (0)
Pain Assessment Tool With Electrodermal Activity for Postoperative Patients: Method Validation Study (Preprint) (2020) (0)
Guest Editorial Special Section on Memory Architectures and Organization (2012) (0)
Towards Better Accounting of Physical Design Effects in High-Level Synthesis (1995) (0)
Multiprocessor system-on-chip data memory customization for embedded array-intensive applications (2007) (0)
Center for Embedded Computer Systems University of California , Irvine Partially Protected Caches to Reduce Failures due to Soft Errors in Mission-Critical Multimedia Systems (2008) (0)
Speculative Execution by Compiler Supported Branch Prediction Hardware (1996) (0)
Benchmarking for high-level synthesis (1992) (0)
Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures (2010) (0)
5th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2007) : Salzburg, Austria, 30 September - 3 October 2007 (2007) (0)
Rapid technology projection for high-level synthesis (1994) (0)
Active Reinforcement Learning for Personalized Stress Monitoring in Everyday Settings (2023) (0)
A Technology-based Pregnancy Health and Wellness Intervention: The Two Happy Hearts Case Study during the COVID-19 Pandemic (Preprint) (2021) (0)
Assessing the Mental Health of Emerging Adults Through a Mental Health App: Protocol for a Prospective Pilot Study (Preprint) (2020) (0)
Data Collection and Labeling of Real-Time IoT-Enabled Bio-Signals in Everyday Settings for Mental Health Improvement (2021) (0)
Label Alignment Improves EEG-based Machine Learning-based Classification of Traumatic Brain Injury (2022) (0)
Objective Prediction of Tomorrow's Affect Using Multi-Modal Physiological Data and Personal Chronicles: A Study of Monitoring College Student Well-being in 2020 (2022) (0)
A Novel Art of Electrocardiogram Assessment in Zebrafish for Cardiovascular Disease Studies and Drug Screening (2021) (0)
Sleep Patterns and Affect Dynamics Among College Students During the COVID-19 Pandemic: Intensive Longitudinal Study (2022) (0)
Digital Health-Enabled Community-Centered Care: A Scalable Model to Empower Future Community Health Workers utilizing Human-in-the-Loop Artificial Intelligence (Preprint) (2021) (0)
SIC-EDGE: Semantic Iterative ECG Compression for Edge-Assisted Wearable Systems (2022) (0)
Stress Monitoring based on Wearable Sensors in Everyday Settings THESIS (2019) (0)
Digital Health-Enabled Community-Centered Care (D-CCC): A Scalable Model to Empower Future Community Health Workers utilizing Human-in-the-Loop AI (2021) (0)
Objective Prediction of Next-Day’s Affect Using Multimodal Physiological and Behavioral Data: Algorithm Development and Validation Study (2023) (0)
Pain Recognition With Electrocardiographic Features in Postoperative Patients: Method Validation Study (Preprint) (2020) (0)
EXPRESSION: An ADL for Software Toolkit Generation, Exploration, and Validation of Programmable SOC Architectures (2008) (0)
Efficient Personalized Learning for Wearable Health Applications using HyperDimensional Computing (2022) (0)
ECG Biosignal Deidentification Using Conditional Generative Adversarial Networks (2022) (0)
Error Resilience Evaluation of Approximate Storage in the Motion Compensation of VVC Decoders (2023) (0)
Sleep Tracking of a Commercially Available Smart Ring and Smartwatch Against Medical-Grade Actigraphy in Everyday Settings: Instrument Validation Study (Preprint) (2020) (0)
Models for Power and Thermal Estimation (2008) (0)
Exploiting Memory Resilience for Emerging Technologies: An Energy-Aware Resilience Exemplar for STT-RAM Memories (2020) (0)
Chapter 4 – Models for Performance Exploration (2008) (0)
Phase 3 . 2 Deliverable : Final report on mobile GPU characterization and opportunities for power and performance improvement (2016) (0)

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