Ping Keung Ko

Ping Keung Ko's AcademicInfluence.com Rankings

Ping Keung Ko

Engineering

#6123

World Rank

#7428

Historical Rank

Electrical Engineering

#1782

World Rank

#1881

Historical Rank

Applied Physics

#1911

World Rank

#1945

Historical Rank

engineering Degrees

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Engineering

Ping Keung Ko's Degrees

PhD Electrical Engineering University of California, Berkeley
Masters Electrical Engineering University of California, Berkeley
Bachelors Electrical Engineering University of California, Berkeley

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Ping Keung Ko's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors (1990) (808)
BSIM: Berkeley short-channel IGFET model for MOS transistors (1987) (564)
Threshold voltage model for deep-submicrometer MOSFETs (1993) (456)
Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI (1997) (414)
The impact of gate-induced drain leakage current on MOSFET scaling (1987) (314)
Random telegraph noise of deep-submicrometer MOSFETs (1990) (299)
Lucky-electron model of channel hot-electron injection in MOSFET'S (1984) (279)
Subbreakdown drain leakage current in MOSFET (1987) (260)
A physics-based MOSFET noise model for circuit simulators (1990) (253)
A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation (1994) (233)
Berkeley reliability tools-BERT (1993) (198)
A physical and scalable I-V model in BSIM3v3 for analog/digital circuit simulation (1997) (187)
A simple method to characterize substrate current in MOSFET's (1984) (185)
An engineering model for short-channel MOS devices (1988) (162)
Principles and characteristics of a new generation plasma immersion ion implanter (1997) (132)
Dependence of channel electric field on device scaling (1985) (131)
A dynamic threshold voltage MOSFET (DTMOS) for very low voltage operation (1994) (122)
Inversion-layer capacitance and mobility of very thin gate-Oxide MOSFET's (1986) (118)
A robust and physical BSIM3 non-quasi-static transient and AC small-signal model for circuit simulation (1998) (116)
Impact ionization in GaAs MESFETs (1990) (113)
Design for suppression of gate-induced drain leakage in LDD MOSFETs using a quasi-two-dimensional analytical model (1992) (113)
High-gain lateral bipolar action in a MOSFET structure (1991) (109)
MOSFET carrier mobility model based on gate oxide thickness, threshold and gate voltages (1996) (108)
A model for hot-electron-induced MOSFET linear-current degradation based on mobility reduction due to interface-state generation (1991) (108)
Super thin-film transistor with SOI CMOS performance formed by a novel grain enhancement method (2000) (106)
Low-voltage hot-electron currents and degradation in deep-submicrometer MOSFETs (1989) (104)
A unified model for hot-electron currents in MOSFET's (1981) (101)
Threshold voltage model for deep-submicrometer fully depleted SOI MOSFET's (1995) (101)
Source-and-drain series resistance of LDD MOSFET's (1984) (95)
Simulation of MOSFET lifetime under AC hot-electron stress (1988) (92)
Hot-carrier current modeling and device degradation in surface-channel p-MOSFETs (1990) (92)
Suppression of boron penetration in p/sup +/ polysilicon gate P-MOSFETs using low-temperature gate-oxide N/sub 2/O anneal (1994) (92)
Numerical modeling of linear doping profiles for high-voltage thin-film SOI devices (1999) (88)
Deep-submicrometer MOS device fabrication using a photoresist-ashing technique (1988) (86)
A charge sheet capacitance model of short channel MOSFETs for SPICE (1991) (81)
The enhancement of gate-induced-drain-leakage (GIDL) current in short-channel SOI MOSFET and its application in measuring lateral bipolar current gain beta (1992) (80)
Chapter 1 - Approaches to Scaling (1989) (79)
A physical model for MOSFET output resistance (1992) (78)
The impact of device scaling and power supply change on CMOS gate performance (1996) (73)
Hot-electron currents in very short channel MOSFET's (1983) (72)
Bipolar-FET hybrid-mode operation of quarter-micrometer SOI MOSFETs (MESFETs read MOSFETs) (1993) (72)
A MOSFET electron mobility model of wide temperature range (77 - 400 K) for IC simulation (1997) (72)
Hot-carrier-induced MOSFET degradation under AC stress (1987) (70)
A capacitance method to determine channel lengths for conventional and LDD MOSFET's (1984) (70)
A CV technique for measuring thin SOI film thickness (1991) (67)
An AC conductance technique for measuring self-heating in SOI MOSFET's (1995) (63)
Performance and reliability design issues for deep-submicrometer MOSFETs (1991) (62)
Effects of N/sub 2/O anneal and reoxidation on thermal oxide characteristics (1992) (62)
An analytical model for the channel electric field in MOSFET's with graded-drain structures (1984) (61)
A simple method to determine channel widths for conventional and LDD MOSFET's (1984) (59)
A wide tuning range gated varactor (2000) (58)
Kink-free polycrystalline silicon double-gate elevated-channel thin-film transistors (1998) (58)
Shot-noise-induced excess low-frequency noise in floating-body partially depleted SOI MOSFET's (1999) (55)
Recessed-channel structure for fabricating ultrathin SOI MOSFET with low series resistance (1994) (55)
Threshold voltage and C-V characteristics of SOI MOSFET's related to Si film thickness variation on SIMOX wafers (1992) (54)
A novel high-speed, 5-volt programming EPROM structure with source-side injection (1986) (53)
VIA-4 avalanche-induced breakdown mechanisms in short-channel MOSFETs (1982) (51)
Instrumental and process considerations for the fabrication of silicon-on-insulators (SOI) structures by plasma immersion ion implantation (1998) (51)
Hot-electron-induced traps studied through the random telegraph noise (1991) (50)
A bidirectional NMOSFET current reduction model for simulation of hot-carrier-induced circuit degradation (1993) (48)
Asymmetrical characteristics in LDD and minimum-overlap MOSFET's (1986) (47)
Hot-carrier-induced degradation of metal-oxide-semiconductor field-effect transistors: Oxide charge versus interface traps (1989) (44)
50-Å gate-Oxide MOSFET's at 77 K (1987) (42)
An accurate semi-empirical saturation drain current model for LDD n-MOSFET (1996) (40)
Single grain thin-film-transistor (TFT) with SOI CMOS performance formed by metal-induced-lateral-crystallization (1999) (39)
Special modulator for high frequency, low-voltage plasma immersion ion implantation (1999) (39)
EEPROM as an analog storage device, with particular applications in neutral networks (1992) (39)
Comparison of ESD protection capability of SOI and bulk CMOS output buffers (1994) (39)
Performance of a CMOS compatible lateral bipolar photodetector on SOI substrate (1998) (38)
Submicron super TFTs for 3-D VLSI applications (2000) (38)
Spatially resolved observation of visible-light emission from Si MOSFET's (1983) (38)
Hot-carrier reliability design guidelines for CMOS logic circuits (1993) (37)
Effect of oxide field on hot‐carrier‐induced degradation of metal‐oxide‐semiconductor field‐effect transistors (1987) (37)
Hot-carrier-reliability design rules for translating device degradation to CMOS digital circuit degradation (1994) (37)
The effects of hot-electron degradation on analog MOSFET performance (1990) (37)
Simulations of CMOS circuit degradation due to hot-carrier effects (1992) (36)
New insight into high-field mobility enhancement of nitrided-oxide N-MOSFET's based on noise measurement (1994) (35)
Improvement of charge trapping characteristics of N/sub 2/O-annealed and reoxidized N/sub 2/O-annealed thin oxides (1992) (34)
An MOS transistor charge model for VLSI design (1988) (34)
A versatile, SOI BiCMOS technology with complementary lateral BJT's (1992) (34)
Gate-induced band-to-band tunneling leakage current in LDD MOSFETs (1992) (34)
The effects of low-angle off-axis substrate orientation on MOSFET performance and reliability (1991) (33)
A high-performance lateral bipolar transistor fabricated on SIMOX (1993) (33)
Polished TFT's: surface roughness reduction and its correlation to device performance improvement (1997) (32)
Circuit reliability simulator-oxide breakdown module (1989) (32)
Flicker noise characteristics of advanced MOS technologies (1988) (32)
A nonquasi-static MOSFET model for SPICE-transient analysis (1989) (32)
Comparative study of fully depleted and body-grounded non fully depleted SOI MOSFETs for high performance analog and mixed signal circuits (1995) (32)
A charge conserving non-quasi-state (NQS) MOSFET model for SPICE transient analysis (1991) (32)
Temperature dependence of MOSFET substrate current (1993) (31)
High-field transport of inversion-layer electrons and holes including velocity overshoot (1997) (31)
Measurement and modeling of short-channel MOS transistor gate capacitances (1987) (31)
Hot-electron induced excess carriers in MOSFET's (1982) (31)
Performance of the floating gate/body tied NMOSFET photodetector on SOI substrate (2000) (31)
Gate current in OFF-state MOSFET (1989) (30)
Relating CMOS inverter lifetime to DC hot-carrier lifetime of NMOSFETs (1990) (30)
Modeling the floating-body effects of fully depleted, partially depleted, and body-grounded SOI MOSFETs (2004) (30)
Recovery of threshold voltage after hot-carrier stressing (1988) (29)
Hot-electron currents in deep-submicrometer MOSFETs (1988) (28)
Field and temperature acceleration of time-dependent dielectric breakdown for reoxidized-nitrided and fluorinated oxides (1992) (28)
Noise overshoot at drain current kink in SOI MOSFET (1990) (26)
The effects of weak gate-to-drain(source) overlap on MOSFET characteristics (1986) (26)
Effects of the gate-to-drain/source overlap on MOSFET characteristics (1987) (25)
A non-quasi-static MOSFET model for SPICE-AC analysis (1992) (25)
Modeling of substrate current in p-MOSFET's (1987) (25)
P-MOSFET gate current and device degradation (1989) (25)
A deep-submicrometer MOSFET model for analog/digital circuit simulations (1988) (24)
Hot-carrier effects in thin-film fully depleted SOI MOSFET's (1994) (24)
An automated system for measurement of random telegraph noise in metal-oxide-semiconductor field-effect transistors (1989) (23)
An accurate model of thin film SOI-MOSFET breakdown voltage (1991) (23)
A three-terminal SOI gated varactor for RF applications (2001) (23)
A framework to evaluate technology and device design enhancements for MOS integrated circuits (1989) (23)
Circuit-level simulation of TDDB failure in digital CMOS circuits (1995) (22)
Optimization of gate oxide N/sub 2/O anneal for CMOSFET's at room and cryogenic temperatures (1994) (22)
Transient behavior of subthreshold characteristics of fully depleted SOI MOSFETs (1991) (22)
The EEPROM as an analog memory drive (1989) (21)
Projecting CMOS circuit hot-carrier reliability from DC device lifetime (1993) (21)
The behavior of narrow-width SOI MOSFETs with MESA isolation (2000) (20)
Enhancement of hot-electron currents in graded-gate-oxide (GGO)-MOSFETs (1984) (20)
A capacitance method to determine the gate-to-drain/Source overlap length of MOSFET's (1987) (20)
Simulating the competing effects of P- and N-MOSFET hot-carrier aging in CMOS circuits (1994) (20)
Hot-Carrier-Induced MOSFET Degradation: AC Versus DC Stressing (1987) (20)
A new bi-directional PMOSFET hot-carrier degradation model for circuit reliability simulation (1992) (19)
Determining the onset frequency of nonquasistatic effects of the MOSFET in AC simulation (2002) (18)
A robust physical and predictive model for deep-submicrometer MOS circuit simulation (1993) (17)
Body self bias in fully depleted and non-fully depleted SOI devices (1994) (17)
Implemention of linear doping profiles for high voltage thin-film SOI devices (1995) (17)
Characterization of very thin gate-oxide MOS devices (1984) (17)
Recess channel structure for reducing source/drain series resistance in ultra-thin SOI MOSFETs (1993) (16)
A complete radiation reliability software simulator (1994) (16)
Realistic worst-case SPICE file extraction using BSIM3 (1995) (16)
Quasi-static simulation of hot-electron-induced MOSFET degradation under AC (pulse) stress (1987) (16)
Effects of plasma charging damage on the noise performance of thin-oxide MOSFET's (1994) (16)
Intrinsic transconductance extraction for deep-submicrometer MOSFETs (1989) (16)
A new LDD structure: total overlap with polysilicon spacer (TOPS) (1990) (15)
A Physical and Scalable – Model in BSIM 3 v 3 for Analog / Digital Circuit Simulation (1998) (15)
Study of luminescent porous polycrystalline silicon thin films (1996) (15)
A physically based compact device model for fully depleted and nearly fully depleted SOI MOSFET (1996) (15)
Hot-carrier-induced degradation in p-MOSFETs under AC stress (1988) (15)
A source-side injection erasable programmable read-only-memory (SI-EPROM) device (1986) (15)
High-isolation bonding pad design for silicon RFIC up to 20 GHz (2003) (15)
A measurement-based charge sheet capacitance model of short-channel MOSFET's for SPICE (1986) (15)
Optimizing polysilicon thin-film transistor performance with chemical-mechanical polishing and hydrogenation (1996) (14)
A relaxation time approach to model the non-quasi-static transient effects in MOSFETs (1994) (14)
Saturation velocity and velocity overshoot of inversion layer electrons and holes (1994) (14)
The influence of substrate compensation on inter-electrode leakage and back-gating in GaAs MESFETs (1991) (14)
Prediction of hot-carrier degradation in digital CMOS VLSI by timing simulation (1992) (14)
A novel Silicon-On-Insulator (SOI) MOSFET for ultra low voltage operation (1994) (13)
A New Insight Into Correlation Between DC And AC Hot-carrier Degradation Of MOS Devices (1993) (13)
Characterization of Intrinsic Capacitances of Small-Geometry MOSFET's (1984) (13)
A new approach for simulation of circuit degradation due to hot-electron damage in NMOSFETs (1991) (13)
The effects of source/drain resistance on deep submicrometer device performance (1990) (13)
Polysilicon gate depletion effect on IC performance (1995) (12)
Design guidelines for deep-submicrometer MOSFETs (1988) (12)
A high density conduction based micro-DNA-identification array fabricated in a CMOS compatible process (2003) (12)
The Enhancement of Gate-Induced-Drain-Leakage (gidl) Current in Soi Mosfet and its Impact on Soi Device Scaling (1992) (12)
High gain lateral bipolar transistor (1988) (11)
SOI/bulk hybrid technology on SIMOX wafers for high performance circuits with good ESD immunity (1995) (10)
A charge-conserving non-quasistatic MOSFET model for SPICE transient analysis (1988) (10)
A high speed SOI technology with 12 ps/18 ps gate delay operating at 5 V/1.5 V (1992) (10)
Hot electron gate current and degradation in P-channel SOI MOSFETs (1991) (10)
Performance and hot-electron reliability of deep-submicron MOSFET's (1987) (10)
A non-quasistatic MOSFET model for SPICE (1987) (10)
A physical poly-silicon thin film transistor model for circuit simulations (1993) (10)
Inverse-narrow-width effect of deep sub-micrometer MOSFETs with LOCOS isolation (1997) (10)
High-Q SOI gate varactor for use in RF ICs (1998) (9)
A unified understanding on fully-depleted SOI NMOSFET hot-carrier degradation (1998) (9)
A physically-based low-frequency noise model for NFD SOI MOSFET's (1998) (9)
RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology (2003) (9)
Improvement of Charge Trapping Char act er is tics of N, 0- Annealed and Reoxidized N,O-Annealed Thin Oxides (1992) (9)
Hot-Electron Effects in Mosfets. (1982) (9)
MOS Device modeling for circuit simulation (1985) (8)
MOSFET inversion layer capacitance model based on Fermi-Dirac statistics for wide temperature range (1997) (8)
Development of a viable 3D integrated circuit technology (2001) (8)
Characterization of hot-carrier effects in thin-film fully-depleted SOI MOSFETs (1994) (8)
MOSFET saturation voltage (1994) (8)
Gate-Induced Drain Leakage in Ldd and Fully-Overlapped Ldd Mosfets (1991) (8)
An analytical model for intrinsic capacitances of short-channel MOSFETs (1984) (8)
SOI MOSFET design for all-dimensional scaling with short channel, narrow width and ultra-thin films (1995) (8)
Simulation of P- and N-MOSFET hot-carrier degradation in CMOS circuits (1991) (8)
Quasi-2D Compact Modeling for Double-Gate MOSFET (2004) (7)
Degradation of N/sub 2/O-annealed MOSFET characteristics in response to dynamic oxide stressing (1993) (7)
High gain gate/body tied NMOSFET photo-detector on SOI substrate for low power applications (2000) (7)
High-speed mixed signal and RF circuit design with compact waffle MOSFET (2002) (7)
Oxides grown on textured single‐crystal silicon for enhanced conduction (1988) (7)
A high performance lateral bipolar transistor from a SOI CMOS process (1995) (7)
The effects of furnace N/sub 2/O annealing on MOSFETs (1992) (7)
An enhanced compact waffle MOSFET with low drain capacitance from a standard submicron CMOS technology (2003) (7)
SOI MOSFET modeling using an AC conductance technique to determine heating (1994) (7)
Fully depleted CMOS/SOI device design guidelines for low power applications (1997) (7)
A novel MOS device structure with S/D contacts over oxide (COO) (1985) (7)
Off‐state leakage currents in n‐channel metal‐oxide‐semiconductor field‐effect transistors with 10‐nm thermally nitrided and reoxidized nitrided oxides as the gate dielectric (1991) (6)
ULSI-quality gate oxide on thin-film-silicon-on-insulator (1993) (6)
Building hybrid active pixels for CMOS imager on SOI substrate (1999) (6)
ESD reliability and protection schemes in SOI CMOS output buffers (1995) (6)
A self-assembly conductive device for direct DNA identification in integrated microarray based system (2002) (6)
The reduction of backgating in GaAs MESFETs by impact ionization (1990) (6)
A novel high-gain CMOS image sensor using floating N-well/gate tied PMOSFET (1998) (6)
A dynamic depletion SOI MOSFET model for SPICE (1998) (6)
A comparative study of the effect of dynamic stressing on high-field endurance and stability of reoxidized-nitrided, fluorinated and conventional oxides (1991) (6)
Large-signal and phase noise performance analysis of active inductor tunable oscillators (2003) (6)
Simulating the effects of single-event and radiation phenomena on GaAs MESFET integrated circuits (1989) (6)
Hot-carrier-reliability of mixed analog/digital technologies (1993) (6)
Measurement of Electron and Hole Saturation Velocities in Silicon Inversion Layers Using Soi Mosfets (1992) (5)
Impact of scaling silicon film thickness on hot carrier effects in thin film fully depleted SOI MOSFETs (1996) (5)
Evolution of the Microfabrication Facility at Berkeley (1989) (5)
Temperature effects on MOSFET driving capability and voltage gain (1996) (5)
Improved SOI image sensor design based on backside illumination on Silicon-On-Sapphire (SOS) substrate (2002) (5)
Interface quality of SOI MOSFET's reflected in noise and mobility (1991) (5)
Impact of scaling silicon film thickness and channel width on SOI MOSFET with reoxidized MESA isolation (1998) (5)
Temperature Effects of the Inversion Layer Electron and Hole Mobility of MOSFETs from 85K to 500K (1993) (5)
Simulating total-dose radiation effects on circuit behavior (1994) (4)
Implementation of fully self-aligned bottom-gate MOS transistor (2002) (4)
A physically based device model for fully depleted and nearly fully depleted SOI MOSFET (1995) (4)
Comparative analysis and parameter extraction of enhanced waffle MOSFET (2003) (4)
SOI formation from amorphous silicon by metal-induced-lateral-crystallization (MILC) and subsequent high temperature annealing (1999) (4)
A Unified BSIM I-V Model for Circuit Simulation (1995) (4)
Characterizing a single hot-electron-induced trap in submicron MOSFET using random telegraph noise (1990) (4)
Time dependence of fully-depleted SOI MOSFETs subthreshold current (1991) (4)
The effects of off-axis substrate orientation on MOSFET characteristics (1989) (3)
Optical response of photodiode in integrated DNA detection system (2001) (3)
An enhanced compact waffle MOSFET for RF integrated circuits (2002) (3)
Modeling the substrate depletion region for GaAs FETs fabricated on semi-insulating substrates (1989) (3)
GaAs MESFET model for circuit simulation (1989) (3)
High performance bulk MOSFET fabricated on SOI substrate for ESD protection and circuit applications (1994) (3)
Practical compact modeling approaches and options for sub-0.1 mum CMOS technologies (2003) (3)
Frequency dispersion in partially depleted SOI MOSFET output resistance (1996) (3)
Width dependence of substrate and gate currents in MOSFET's (1985) (3)
Effect Of Nickel In Large Grain Poly-Si Film Formed By Nickel Induced Lateral Crystallization and New Grain Enhancement Method (2000) (3)
Suppressing Flash EEPROM Erase Leakage With Negative Gate Bias And LDD Erase Junction (1993) (3)
A novel distributed system for plasma immersion ion implanter control and automation (1998) (3)
Hot-carrier currents of SOI MOSFETs (1993) (3)
Array-Based Electrical Detector of Integrated DNA Identification System for Genetic Chip Applications (2002) (3)
Effects of the field-edge transistor on SOI MOSFETs (1991) (3)
Minimum Detectable Signals Of Integrated Magnetic Sensors In Bulk Cmos And SOI Tech Nologies For Magnetic Read Heads (1995) (2)
On buried-oxide effects in SOI lateral bipolar transistors (1994) (2)
Short-channel effects on MOS transistor capacitances (1986) (2)
HOT ELECTRON GATE CURRENT &VD DEGRADATION P-CHANNEL SOI MOSFET'S (1991) (2)
Simulating radiation reliability with BERT (1995) (2)
High responsivity photo-sensor using gate-body tied SOI MOSFET (1998) (2)
Deep Sub-Micron, Bipolar-Mos Hybrid Transistors Fabricated on Simox (1992) (2)
A channel field model of SOI MOSFET (1993) (2)
High frequency characteristics of MOSFETs with compact waffle layout (2004) (2)
Interface characterization of fully-depleted SOI MOSFET by a subthreshold I-V method (1994) (2)
Characterization and modeling of waffle MOSFETs for high frequency applications (2004) (2)
High-performance sub-quarter-micrometer PMOSFET's on SOI (1993) (2)
Mechanisms for hot-carrier-induced degradation in reoxidized-nitrided-oxide n-MOSFET's under combined AC/DC stressing (1993) (2)
A Workable Use of the Floating-Body Silicon-On-Sapphire MOSFET as a Transconductance Mixer (2004) (2)
A highly-sensitive and low power SOI lateral thyristive magnetometer (1994) (2)
A viable self-aligned bottom-gate MOS transistor technology for deep submicron 3-D SRAM (2003) (2)
A CMOS active pixel sensor on silicon-on-sapphire substrate with backside illumination (2003) (2)
An active pixel sensor (APS) based on high gain CMOS compatible lateral bipolar transistor (LBT) on SOS substrate with backside illumination (2003) (2)
Fully depleted CMOS/SOI device design guidelines for low-power applications (1999) (2)
Improved thin-film transistor (TFT) characteristics on chemical-mechanically polished polycrystalline silicon film (1999) (2)
Lateral carrier-domain magnetometer fabricated on BESOI (1994) (2)
Narrow width effect of ROSIE isolated SOI MOSFET (1995) (2)
Oxides grown on textured single-crystal silicon for low programming voltage non-volatile memory applications (1987) (2)
Characterization of light emitting porous polycrystalline silicon films (1996) (1)
Model for photo-induced long-term drain current transients in GaAs MESFETs (1990) (1)
A self-aligned double-gate mos transistor technology with individually addressable gates (2002) (1)
On buried-oxide effects in SOI lateral bipolar transistors (1994) (1)
BERT- Circuit Oxide Reliability Simulator (CORS) (1990) (1)
Hot-carrier effects in depletion-mode MOSFETs (1989) (1)
Experimental characterization of transient floating body effect in non-fully depleted SOI MOSFET (1997) (1)
A physical approach to enhance BSIM3 NQS model for fast transient simulation (1999) (1)
Quasi-2 D Compact Modeling for Double-Gate MOSFET (2004) (1)
A Low-Barrier Body-Contact Scheme for SOI MOSFETs to Eliminate the Floating Body Effect (1993) (1)
Photon induced hump effect in NMOSFET (1997) (1)
VIB-3 correlation between substrate and gate currents in MOSFETs (1981) (1)
A novel methodology for reliability studies in fully-depleted SOI MOSFETs (1997) (1)
On the modelling of a CMOS magnetic sensor (1994) (1)
Non-quasistatic modeling of the BJT quasi-neutral base (1993) (1)
A Versatile, SO4 BiCMOS Technology with Complenientary Lateral B JT's (1992) (1)
Transient substrate current delay in NMOSFETs (1987) (1)
A deep-submicrometer raised source/drain LDD structure fabricated using hot-wall epitaxy (1991) (1)
The impact of the AC current crowding effect on BJT RF noise modeling (2003) (1)
Nearly-fully-depleted (NFD), 0.15 mu m SOI CMOS in a CBiCMOS technology (1993) (1)
Room temperature observation of velocity overshoot in silicon inversion layers (1993) (1)
Complementary, High-Performance Lateral Bjts in a Simox C-Bicmos Technology (1992) (1)
MOSFET drain/source charge partition under nonquasi-static switching (2001) (1)
p-MOSFET gate current and device degradation (1989) (0)
An analytical model and experimental results of a highly integrateable magnetic field sensor (1994) (0)
Effect of Ramp Annealing to Ni Induced Lateral Crystallization of Amorphous Silicon (2000) (0)
A comparative study of RF noise characteristics of different submicron SOI MOSFET structures on SIMOX technology (2002) (0)
Hot-Electron-Induced Traps Studied Through (1991) (0)
Session 22 Advanced IC interconnect technology (1987) (0)
Lateral carrier domain magnetometer in SOI technology (1996) (0)
Modelling for the current-voltage characteristics of SOI submicrometre gate controlled hybrid transistors (2001) (0)
VIA-5 hot-electron induced excess carriers in n-channel MOSFETs (1982) (0)
Evaluation of the Impact of Non-Quasi-Static Effects in RF Applications (2001) (0)
Session 2 Device technology — Selective epitaxy and merged bipolar — CMOS technology (1987) (0)
RECENT ADVANCES IN BiCMOS TECHNOLOGY (1990) (0)
Reoxidixed MESA Isolated SOI MOSFET Width Scaling as a Function of Silicon Film Thickness (1997) (0)
A Viable Self-aligned Bottom-Gate MOSFET Technology for High Density and Low Voltage SRAM (2002) (0)
Reply to "Comments on 'source-and-drain series resistance of LDD MOSFET's'" (1984) (0)
Improved thin dielectric characteristics on chemical-mechanically polished polycrystalline silicon film (1999) (0)
Effect of electric field on metal induced lateral crystallization of amorphous silicon (1999) (0)
A study of the spectral sensitivity of photodiode from a standard CMOS process for DNA detection (2001) (0)
The investigation of recessed channel SOI devices (1998) (0)
A Comparative Study of High-Field Endurance for Reoxidized-Nitrided and Fluorinated Oxides (1991) (0)
Observation of Visible-Light from Si MO (1983) (0)
A Study of Deep-submicron MOSFET Technology Prediction and Scaling with BSIM3 (1996) (0)
The impact of the distributed RC effect on high frequency noise modeling of bipolar transistor (2004) (0)
Dispositif a semi-conducteur d'oxyde metallique au silicium pouvant traiter des milliards de bits par seconde (1984) (0)
An enhanced BSIM3 NQS model for large signal transient simulation (1999) (0)
I"WWACE @JAUWoF SOIMOSRET's REFLECTED nvNors~AM) Mom (1991) (0)
Soista Initial Spice Initial Rise Fall Short-path Long-path Max Min Max Min Rise Fall Rise Fall (1999) (0)
Modeling CMOS Non-Quasi-Static Effects in a Quasi-Static Simulation Engine (2004) (0)
Study of current drive in deep sub-micrometer SOI PMOSFET'S (1993) (0)
A Workable Use of Floating-Body SOS MOSFET as a Transconductance Mixer (2003) (0)
( 10-1 ) Modeling Deep-submicron MOS Devices for Circuit Simulation (2007) (0)
A finite width impurity source model for linear doping profiles (1995) (0)
SOI Formation from Amorphous Silicon by Novel Gain Enhancement Method (1999) (0)
Experimental Investigation of Recessed Channel SOI Devices (1988) (0)
A novel SOI CBiCMOS compatible device structure for analog and mixed-mode circuits (1995) (0)
Anomalous narrow width behavior of deep sub-micrometer MOSFETs with LOCOS isolation (1995) (0)
Design and performance of resistive-gated MOSFETs for analog integrated circuits (1979) (0)
Analysis of Floating Body Effect in Non-fully Depleted SOI MOSFETs based on Capacitive Coupling (1997) (0)

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