Paritosh Pandya

Q: What Schools Are Affiliated With Paritosh Pandya

Paritosh Pandya is affiliated with the following schools: Tata Institute of Fundamental Research, IIT Kanpur, University of Mumbai, IIT Bombay, Stanford University, Maharaja Sayajirao University of Baroda

Paritosh Pandya's AcademicInfluence.com Rankings

Paritosh Pandya

Computer Science

#464

World Rank

#482

Historical Rank

Database

#1480

World Rank

#1555

Historical Rank

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Computer Science

Paritosh Pandya's Degrees

PhD Computer Science Stanford University

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Why Is Paritosh Pandya Influential?

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According to Wikipedia, Paritosh K. Pandya is an Indian computer scientist based at the Tata Institute of Fundamental Research in Mumbai, India. Since 2020, he is an adjunct professor at IIT Bombay. Paritosh Pandya studied for a BE degree in Electronics at the Maharaja Sayajirao University of Baroda , MTech degree in Computer Science at IIT Kanpur , and a PhD in Computer Science at Bombay University/TIFR .

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Paritosh Pandya's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Finding Response Times in a Real-Time System (1986) (1272)
FST TCS 2003: Foundations of Software Technology and Theoretical Computer Science (2004) (110)
Specifying and Deciding Quantified Discrete-time Duration Calculus Formulae using DCVALID (2000) (91)
Automated Technology for Verification and Analysis (2012) (81)
Representation, Verification, and Computation of Timed Properties in Web (2006) (79)
Timed modelling and analysis in Web service compositions (2006) (72)
Duration Calculus of Weakly Monotonic Time (1998) (43)
An Algebraic Approach to Verifiable Compiling Specification and Prototyping of the Procos Level 0 Programming Language (1990) (41)
Interval Duration Logic: Expressiveness and Decidability (2002) (38)
Digitizing Interval Duration Logic (2003) (36)
Model Checking CTL*[DC] (2001) (34)
Finite Divergence (1995) (32)
Formal Design of Hybrid Systems (1994) (32)
Timed Automata with Integer Resets: Language Inclusion and Expressiveness (2008) (32)
Bounded Validity Checking of Interval Duration Logic (2005) (30)
Principles of concurrent and distributed programming (1991) (26)
Marking the chops: an unambiguous temporal logic (2008) (26)
Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts (2008) (26)
P — A logic — a compositional proof system for distributed programs (1991) (25)
Some Extensions to Propositional Mean-Value Caculus: Expressiveness and Decidability (1995) (24)
Some Comments on the Assumption-Commitment Framework for Compositional Verification of Distributed Programs (1989) (24)
An Approach to Verifiable Compiling Specification and Prototyping (1990) (20)
On Expressive Powers of Timed Logics: Comparing Boundedness, Non-punctuality, and Deterministic Freezing (2011) (19)
Toward a theory of sequential hybrid programs (1998) (18)
Around Dot Depth Two (2010) (18)
An Approach to Veriiable Compiling Speciication and Prototyping (1990) (17)
Weak Chop Inverses and Liveness in Mean-Value Calculus (1996) (16)
Some extensions to mean-value calculus: expressiveness and de-cidability (1995) (16)
The Saga of Synchronous Bus Arbiter: On Model Checking Quantitative Timing Properties of Synchronous Programs (2002) (15)
A Compositional Semantics of Esterel in Duration Calculus (1995) (15)
Modal Strength Reduction in Quantified Discrete Duration Calculus (2005) (14)
Verification Tools in the Development of Provably Correct Compilers (1993) (11)
A Structure-Directed Total Correctness Proof Rule for Recursive Procedure Calls (1986) (11)
A Calculus for Hybrid Sampled Data Systems (1994) (10)
Two-variable Logic with a Between Relation (2016) (10)
Efficient guided symbolic reachability using reachability expressions (2006) (10)
The Unary Fragments of Metric Interval Temporal Logic: Bounded versus Lower Bound Constraints (2012) (10)
On construction of safety signal automata for MITL[ u, s] using temporal projections (2011) (10)
Determinization and Expressiveness of Integer Reset Timed Automata with Silent Transitions (2009) (9)
Some Decidability Results for Duration Calculus under Synchronous Interpretation (1998) (8)
Metric Temporal Logic with Counting (2015) (8)
Making Metric Temporal Logic Rational (2017) (8)
Finding Extremal Models of Discrete Duration Calculus formulae using Symbolic Search (2005) (8)
Automatic test case generation in model based software design to achieve higher reliability (2010) (7)
Partially Punctual Metric Temporal Logic is Decidable (2014) (7)
Chop Expressions and Discrete Duration Calculus (2012) (7)
On Sampling Abstraction of Continuous Time Logic with Durations (2007) (7)
Recursive Mean-Value Calculus (1998) (7)
Formalizing Timing Diagram Requirements in Discrete Duration Calculus (2017) (6)
DCSynth: Guided Reactive Synthesis with Soft Requirements (2019) (6)
Two-variable logics with some betweenness relations: Expressiveness, satisfiability and membership (2019) (5)
Logics Meet 1-Clock Alternating Timed Automata (2018) (5)
DCSYNTH: A Tool for Guided Reactive Synthesis with Soft Requirements (2019) (5)
Reasoning Algebraically about Recursion (1992) (5)
Unambiguity in Timed Regular Languages: Automata and Logics (2010) (5)
Some Results on the Decidability of Duration Calculus under Synchronous Interpretation (1996) (5)
On Construction of Safety Signal Automata for $MITL[\: \mathcal{U}, \: \mathcal{S}]$ Using Temporal Projections (2011) (4)
Specification and Reactive Synthesis of Robust Controllers (2019) (4)
On the Decidability and Complexity of Some Fragments of Metric Temporal Logic (2013) (4)
An Algebraic Decision Procedure for Two-Variable Logic with a Between Relation (2018) (4)
Modelling and Analysis of Time-related Properties in Web Service Compositions (2005) (3)
ICSP and Its Relationship with ACSP and CSP (1993) (3)
Specification and Verification of Total Correctness of Distributed Programs (1987) (3)
DCSYNTH: Guided Reactive Synthesis with Soft Requirements for Robust Controller and Shield Synthesis (2017) (3)
Two-variable Logic with a Between Predicate (2016) (3)
Towards a Theory of Sequential Hy- Brid Programs towards a Theory of Sequential Hy- Brid Programs (1998) (2)
Generalizing Non-Punctuality for Timed Temporal Logic with Freeze Quantifiers (2021) (2)
Beyond Swayambhu Gandhar : An Analysis of Perceived Tanpura Notes (2004) (2)
A Dose of Timed Logic, in Guarded Measure (2006) (2)
Büchi-Kamp Theorems for 1-clock ATA (2018) (2)
Model Checking CTL[DC] properties of SMV, Verilog and Esterel Designs (2000) (2)
Logical specification and uniform synthesis of robust controllers (2019) (2)
On Unary Fragments of MTL and TPTL over Timed Words (2014) (1)
Specification and Optimal Reactive Synthesis of Run-time Enforcement Shields (2019) (1)
A Compositional Semantics of Esterel in DurationCalculus ( Extended (1995) (1)
Deterministic Logics for UL (2013) (1)
On the Computational Power of Operators in ICSP with Fairness (1994) (0)
2-Way 1-Clock ATA & Its Logics: Back To The Future With Alternations (2022) (0)
Infinitary parallelism without unbounded nondeterminism in CSP (1993) (0)
Deterministic Temporal Logics and Interval Constraints (2017) (0)
Session details: Keynote Address (2015) (0)
Timed and Hybrid Automata in SAL (2008) (0)
38th IARCS Annual Conference on Foundations of Software Technology and Theoretical Computer Science, FSTTCS 2018, December 11-13, 2018, Ahmedabad, India (2018) (0)
An Introduction to Timed Automata (2012) (0)
Front Matter, Table of Contents, Preface, Conference Organization (2018) (0)
Logics Meet 2-Way 1-Clock Alternating Timed Automata (2021) (0)
All Those Duration Calculi: An Integrated Approach (2007) (0)
Hybrid Automata And SAL (2007) (0)
Session details: Keynote Address (2015) (0)
Level - fair derivations in context - free rewriting systems (2013) (0)
Decidability of Emptiness Checking in various Alternating Timed Automata and Connections to Timed Logics (2012) (0)
From Non-Punctuality to Non-Adjacency: A Quest for Decidability of Timed Temporal Logics with Quantifiers. (2022) (0)
A Regular Metric Temporal Logic (2017) (0)

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What Schools Are Affiliated With Paritosh Pandya?

Paritosh Pandya is affiliated with the following schools:

Paritosh Pandya's Academic­Influence.com Rankings