Peter Hofstee | Academic Influence

Peter Hofstee's AcademicInfluence.com Rankings

Peter Hofstee

Computer Science

#1936

World Rank

#2011

Historical Rank

Computer Architecture

#87

World Rank

#89

Historical Rank

Database

#9328

World Rank

#9818

Historical Rank

computer-science Degrees

Download Badge

Computer Science

Peter Hofstee's Degrees

PhD Computer Science Stanford University
Masters Computer Science Stanford University
Bachelors Computer Science Delft University of Technology

Similar Degrees You Can Earn

Why Is Peter Hofstee Influential?

(Suggest an Edit or Addition)

According to Wikipedia, Harm Peter Hofstee is a Dutch physicist and computer scientist who currently is a distinguished research staff member at IBM Austin, USA, and a part-time professor in Big Data Systems at Delft University of Technology, Netherlands.

(See a Problem?)

Peter Hofstee's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Introduction to the Cell multiprocessor (2005) (1080)
The design and implementation of a first-generation CELL processor (2005) (616)
Synergistic Processing in Cell's Multicore Architecture (2006) (460)
Power efficient processor architecture and the cell processor (2005) (402)
Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor (2006) (259)
The microarchitecture of the synergistic processor for a cell processor (2006) (103)
A 1.0 GHz single-issue 64 b powerPC integer processor (1998) (75)
ExtraV: Boosting Graph Processing Near Storage with a Coherent Accelerator (2017) (57)
Designing for a gigahertz [guTS integer processor] (1998) (53)
Design methodology for a 1.0 GHz microprocessor (1998) (50)
Multicore Processors and Systems (2009) (49)
In-memory database acceleration on FPGAs: a survey (2019) (47)
Future microprocessors and off-chip SOP interconnect (2004) (45)
Rome Reborn (2008) (42)
Custom circuit design as a driver of microprocessor performance (2000) (40)
High speed serializing/de-serializing design-for-test method for evaluating a 1 GHz microprocessor (1998) (36)
Big Data text-oriented benchmark creation for Hadoop (2013) (34)
SparkGA: A Spark Framework for Cost Effective, Fast and Accurate DNA Analysis at Scale (2017) (32)
Cell Broadband Engine processor vault security architecture (2007) (30)
Power-constrained microprocessor design (2002) (29)
ThymesisFlow: A Software-Defined, HW/SW co-Designed Interconnect Stack for Rack-Scale Memory Disaggregation (2020) (26)
The design and implementation of a first-generation CELL processor - a multi-core SoC (2005) (24)
Auto-tuning Spark big data workloads on POWER8: Prediction-based dynamic SMT threading (2016) (23)
Distributed Sorting (1990) (22)
Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor (2006) (21)
Timed circuit verification using TEL structures (2001) (21)
"Timing closure by design," a high frequency microprocessor design methodology (2000) (20)
The design methodology and implementation of a first-generation CELL processor: a multi-core SoC (2005) (20)
Verification of delayed-reset domino circuits using ATACS (1999) (20)
Fletcher: A Framework to Efficiently Integrate FPGA Accelerators with Apache Arrow (2019) (20)
Second-Generation Big Data Systems (2015) (18)
Supporting Columnar In-memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow (2019) (18)
Hardware and software architectures for the CELL processor (2005) (16)
A Distributed Implementation of a Task Pool (1991) (15)
True hardware random number generation implemented in the 32-nm SOI POWER7+ processor (2013) (15)
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI (2007) (14)
Giving Text Analytics a Boost (2014) (14)
A matrix-multiply unit for posits in reconfigurable logic leveraging (open)CAPI (2018) (12)
NASB: Neural Architecture Search for Binary Convolutional Neural Networks (2020) (12)
Feature detection for image analytics via FPGA acceleration (2015) (11)
Understanding System and Architecture for Big Data (2012) (10)
Refine and Recycle: A Method to Increase Decompression Parallelism (2019) (10)
PATer: A Hardware Prefetching Automatic Tuner on IBM POWER8 Processor (2016) (9)
AutoReCon: Neural Architecture Search-based Reconstruction for Data-free Compression (2021) (8)
Understanding system design for Big Data workloads (2013) (8)
An Efficient High-Throughput LZ77-Based Decompressor in Reconfigurable Logic (2020) (7)
Community Climate System Model (CCSM) (2011) (7)
FPGA Acceleration for Big Data Analytics: Challenges and Opportunities (2021) (7)
Real-time supercomputing and technology for games and entertainment (2006) (7)
Adopting OpenCAPI for High Bandwidth Database Accelerators (2017) (6)
A Fine-Grained Parallel Snappy Decompressor for FPGAs Using a Relaxed Execution Model (2019) (6)
Heterogeneous Multi-core Processors: The Cell Broadband Engine (2009) (5)
A 690 ps read-access latency register file for a GHz integer microprocessor (1998) (5)
A high-bandwidth snappy decompressor in reconfigurable logic: work-in-progress (2018) (5)
Optimizing performance of GATK workflows using Apache Arrow In-Memory data framework (2020) (4)
Battling the CPU Bottleneck in Apache Parquet to Arrow Conversion Using FPGA (2020) (4)
Analyzing In-Memory Hash Join: Granularity Matters (2017) (4)
Distributing a Class of Sequential Programs (1992) (4)
A hardware compilation framework for text analytics queries (2018) (4)
An Attention Module for Convolutional Neural Networks (2021) (4)
Cell Broadband Engine Processor Design Methodology (2007) (3)
Understanding Systems and Architectures for Big Data (2012) (3)
Tydi: An Open Specification for Complex Data Structures Over Hardware Streams (2020) (3)
Towards an optimal file allocation strategy for SPECweb99 (2001) (3)
REAF: Reducing Approximation of Channels by Reducing Feature Reuse Within Convolution (2020) (3)
VC@Scale: Scalable and high-performance variant calling on cluster environments (2021) (3)
Optimized Durable Commitlog for Apache Cassandra Using CAPI-Flash (2016) (3)
CAPI-Flash Accelerated Persistent Read Cache for Apache Cassandra (2018) (3)
An Accelerator for Posit Arithmetic Targeting Posit Level 1 BLAS Routines and Pair-HMM (2019) (3)
On Jan L. A. van de Snepscheut's “The Sliding-Window Protocol Revisited” (2005) (3)
HPPC 2009 Panel: Are Many-Core Computer Vendors on Track? (2009) (2)
Circuits and microarchitecture for gigahertz VLSI designs (1997) (2)
Benchmarking Apache Arrow Flight - A wire-speed protocol for data transfer, querying and microservices (2022) (2)
Cluster File Systems (2011) (1)
Beyond 1 GHz [microprocessor design] (1999) (1)
Community Ice Code (CICE) (2011) (1)
SoFAr: Shortcut-based Fractal Architectures for Binary Convolutional Neural Networks (2020) (1)
Constructing some Distributed Programs (1992) (1)
Critical Sections (2011) (1)
Configurable, Highly Parallel Computer (2011) (1)
A problem in the regularity calculus (1993) (1)
Hardware-accelerated text analytics (2014) (1)
Architecting interconnect (2003) (1)
A 64-GB Sort at 28 GB/s on a 4-GPU POWER9 Node for Uniformly-Distributed 16-Byte Records with 8-Byte Keys (2018) (1)
A Toolchain for Streaming Dataflow Accelerator Designs for Big Data Analytics: Defining an IR for Composable Typed Streaming Dataflow Designs (2022) (0)
Synchronizing Processes (1994) (0)
Derivation of a rotator circuit with homogeneous interconnect (2001) (0)
SALoBa: Maximizing Data Locality and Workload Balance for Fast Sequence Alignment on GPUs (2022) (0)
Tydi-lang: A Language for Typed Streaming Hardware (2022) (0)
Preface (2007) (0)
USING A CIRCUIT-CENTRIC APPROACH, A SMALL TEAM CONSTRUCTED A GIGAHERTZ INTEGER PROCESSOR , MORE THAN DOUBLING THE FREQUENCY OF FULL -FLEDGED DESIGNS IN THE SAME TECHNOLOGY. (1998) (0)
Generating High-Performance FPGA Accelerator Designs for Big Data Analytics with Fletcher and Apache Arrow (2021) (0)
7 Conclusions and Further Research Acknowledgements We like to Thank the Calculi for Distributed Program Construction Club Headed by Lambert Meertens and Doaitse Swierstra and the Formal Models Club at Utrecht University. We Also Want to Acknowledge (2007) (0)
System and method for a memory with combined circuit-switched and word access (2006) (0)
Communication and Synchronization in the Cell Processor - Invited Talk (2005) (0)
Arrow Flight (2022) (0)
Video-Text Compliance: Activity Verification Based on Natural Language Instructions (2019) (0)
The Next 25 Years of Computer Architecture? (2009) (0)
Community Climate Model (CCM) (2011) (0)
RAW 2016 Keynotes (2016) (0)
Cell Broadband Engine Processor (2011) (0)
Communication-Efficient Cluster Scalable Genomics Data Processing Using Apache Arrow Flight (2022) (0)
Running ahead approximate calculations (2012) (0)
In-memory database acceleration on FPGAs: a survey (2019) (0)
An Efficient High-Throughput LZ77-Based Decompressor in Reconfigurable Logic (2020) (0)
GenMPI: Cluster Scalable Variant Calling for Short/Long Reads Sequencing Data (2022) (0)
The future of multi-core technologies (2007) (0)
Improving Gradient Paths for Binary Convolutional Neural Networks (2022) (0)

This paper list is powered by the following services:

Other Resources About Peter Hofstee

en.wikipedia.org

What Schools Are Affiliated With Peter Hofstee?

Peter Hofstee is affiliated with the following schools:

Image Attributions

Image Source for Peter Hofstee