Peter Kogge

Q: What Schools Are Affiliated With Peter Kogge

Peter Kogge is affiliated with the following schools: University of Notre Dame, Stanford University

Peter Kogge's AcademicInfluence.com Rankings

Peter Kogge

Computer Science

#1661

World Rank

#1720

Historical Rank

#800

USA Rank

Computer Engineering

World Rank

Historical Rank

USA Rank

computer-science Degrees

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Computer Science

Peter Kogge's Degrees

PhD Electrical Engineering Stanford University
Masters Electrical Engineering Stanford University
Bachelors Electrical Engineering University of Notre Dame

Why Is Peter Kogge Influential?

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According to Wikipedia, Peter Michael Kogge is an American computer engineer and IBM Fellow. Background Kogge has been at the forefront of several innovations that have shaped the computing industry over the past three decades. While working on his PhD at Stanford in the 1970s, Kogge invented what is still today considered the fastest way of adding numbers in a computer, the Kogge–Stone Adder process, an approach still used in microprocessors by Intel and other companies.

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Peter Kogge's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations (1973) (1298)
The Architecture of Pipelined Computers (1981) (492)
Mapping Irregular Applications to DIVA, a PIM-based Data-Intensive Architecture (1999) (225)
EXECUBE-A New Architecture for Scaleable MPPs (1994) (224)
The energy complexity of register files (1998) (178)
Inherently Lower-Power High-Performance Superscalar Architectures (2001) (170)
Problems in designing with QCAs: Layout = Timing (2001) (161)
Memory in Motion : A Study of Storage Structures in QCA (2002) (124)
The state of state (2003) (109)
DOE Advanced Scientific Computing Advisory Subcommittee (ASCAC) Report: Top Ten Exascale Research Challenges (2014) (101)
Parallel Solution of Recurrence Problems (1974) (93)
A design of and design tools for a novel quantum dot based microprocessor (2000) (80)
A Potentially Implementable FPGA for Quantum-Dot Cellular Automata (2002) (79)
Exploring and exploiting wire-level pipelining in emerging technologies (2001) (79)
The Architecture of Symbolic Computers (1990) (76)
Combined DRAM and logic chip for massively parallel systems (1995) (73)
Pursuing a petaflop: point designs for 100 TF computers using PIM technologies (1996) (71)
On the Memory Access Patterns of Supercomputer Applications: Benchmark Selection and Its Implications (2007) (71)
Quantum-dot cellular automata (QCA) circuit partitioning: problem modeling and solutions (2004) (70)
Optimization of high-performance superscalar architectures for energy efficiency (2000) (68)
Logic in wire: using quantum dots to implement a microprocessor (1999) (67)
Exascale Computing Trends: Adjusting to the "New Normal"' for Computer Architecture (2013) (64)
Microservers: a new memory semantics for massively parallel computing (1999) (56)
The tops in flops (2011) (56)
An Architectural Trail to Threaded-Code Systems (1982) (55)
Using the TOP500 to trace and project technology and architecture trends (2011) (50)
Highly Scalable Near Memory Processing with Migrating Threads on the Emu System Architecture (2016) (48)
Energy-efficient issue queue design (2003) (46)
Energy-efficient instruction dispatch buffer design for superscalar processors (2001) (45)
Generation of permutations for SIMD processors (2005) (45)
Probabilistic Analysis of a Molecular Quantum-Dot Cellular Automata Adder (2007) (42)
A low cost, multithreaded processing-in-memory system (2004) (38)
The "4-diamond circuit" - a minimally complex nano-scale computational building block in QCA (2004) (35)
Partially Reversible Pipelined QCA Circuits: Combining Low Power With High Throughput (2011) (35)
Processing In Memory: Chips to Petaflops (1997) (34)
The Characterization of Data Intensive Memory Workloads on Distributed PIM Systems (2000) (32)
The microprogramming of pipelined processors (1977) (32)
Thread Migration to Improve Synchronization Performance (2006) (31)
The structural simulation toolkit: exploring novel architectures (2006) (29)
PIM architectures to support petaflops level computation in the HTMT machine (1999) (29)
Analyzing the Inherent Reliability of Moderately Sized Magnetic and Electrostatic QCA Circuits Via Probabilistic Transfer Matrices (2009) (26)
A parallel processing chip with embedded DRAM macros (1996) (26)
The implications of working set analysis on supercomputing memory hierarchy design (2005) (25)
Inherently Lower-Power High-Performance (2001) (24)
Petaflop Computing for Protein Folding (2001) (24)
Carbon nanotubes for quantum-dot cellular automata clocking (2004) (24)
Exascale Research: Preparing for the Post-Moore Era (2011) (23)
Molecular cellular networks: A non von Neumann architecture for molecular electronics (2016) (22)
Reliability Impact of N-Modular Redundancy in QCA (2011) (21)
Strategy and prototype tool for doing fault modeling in a nano-technology (2003) (20)
Polygonal path simplification with angle constraints (2005) (19)
Of Piglets and Threadlets: Architectures for Self-Contained, Mobile, Memory Programming (2004) (19)
VLSI and rule-based systems (1988) (18)
An exploration of the technology space for multi-core memory/logic chips for highly scalable parallel systems (2005) (18)
Characterizing a new class of threads in scientific applications for high end supercomputers (2004) (18)
An Analysis of Missing Cell Defects in Quantum-Dot Cellular Automata (2005) (18)
The effects of a new technology on the design, organization, and architectures of computing systems (2003) (17)
Yearly update : exascale projections for 2013. (2013) (17)
Using circuits and systems-level research to drive nanotechnology (2004) (16)
Reversible computation with quantum-dot cellular automata (QCA) (2005) (14)
Logic in wire: using quantum dots to implement a microprocessor (1999) (14)
Bouncing threads: merging a new execution model into a nanotechnology memory (2003) (13)
Application of STD to latch-power estimation (1999) (13)
Scalability of Hybrid Sparse Matrix Dense Vector (SpMV) Multiplication (2018) (12)
Programming future architectures: dusty decks, memory walls, and the speed of light (2006) (12)
System Reliabilities When Using Triple Modular Redundancy in Quantum-Dot Cellular Automata (2008) (12)
EXPLOITING BIT–SLICE INACTIVITIES FOR REDUCING ENERGY REQUIREMENTS OF SUPERSCALAR PROCESSORS* (12)
PIM Lite: On the Road Towards Relentless Multi-threading in Massively Parallel Systems (2003) (11)
Optimizing for KNL Usage Modes When Data Doesn't Fit in MCDRAM (2018) (11)
Steps to Petaflops computing: a hybrid technology multithreaded architecture (1997) (11)
Traveling threads: a new multithreaded execution model (2006) (10)
Implementing Radix Sort on Emu 1 (2015) (10)
Facing the Exascale Energy Wall. (2010) (10)
[2010] Facing the Exascale Energy Wall (2010) (10)
Evaluating synchronization techniques for light-weight multithreaded/multicore architectures (2007) (10)
A Case for Migrating Execution for Irregular Applications (2017) (10)
Origins and motivations for design rules in QCA (2004) (9)
Jaccard Coefficients as a Potential Graph Benchmark (2016) (9)
Big data, deep data, and the effect of system architectures on performance (2013) (9)
Probabilistic Analysis of a Quantum-Dot Cellular Automata Multiplier Implemented in Different Technologies (2007) (9)
High throughput and low power dissipation in QCA pipelines using Bennett clocking (2010) (9)
Maximal rate pipelined solutions to recurrence problems (1973) (9)
Comparative performance analysis of a Big Data NORA problem on a variety of architectures (2013) (8)
Cache-In-Memory: A Lower Power Alternative? (1998) (8)
A Heterogeneous Lightweight Multithreaded Architecture (2007) (7)
Multi-Core for HPC: breakthrough or breakdown? (2006) (7)
Morph : Adding an Energy Gear to a High Performance Microarchitecture for Embedded Applications (2000) (7)
Energy-efficient multithreading for a hierarchical heterogeneous multicore through locality-cognizant thread generation (2013) (7)
The Structural Simulation Toolkit: A Tool for Bridging the Ar chitectural/Microarchitectural Evaluation Gap (2004) (7)
Cache-In-Memory (2001) (7)
It's all about the signal routing: understanding the reliability of qca circuits and systems (2009) (7)
Maximal Rate Pipelined Solutions to Recurrance Problems (1973) (7)
The Challenges of Petascale Architectures (2009) (7)
Memory model effects on application performance for a lightweight multithreaded architecture (2008) (7)
Future High Performance Computing Capabilities: Summary Report of the Advanced Scientific Computing Advisory Committee (ASCAC) Subcommittee (2019) (7)
Trading bandwidth for latency: managing continuations through a carpet bag cache (2002) (6)
Graph Analytics: Complexity, Scalability, and Architectures (2017) (6)
From bits to chips: a multidisciplinary curriculum for microelectronics system design education (2003) (6)
A microserver view of HTMT (2001) (6)
The Case for Processing-in-Memory (1997) (6)
Basic Research Needs for Microelectronics: Report of the Office of Science Workshop on Basic Research Needs for Microelectronics, October 23 – 25, 2018 (2018) (6)
Implications of a PIM architectural model for MPI (2003) (6)
Optimizing Page Replacement for Multiple-Level Memory Hierarchy (1998) (6)
A comparative analysis of power and energy management techniques in real embedded applications (2003) (5)
EFFICIENT DATA PLACEMENT FOR PROCESSOR-IN-MEMORY ARRAY PROCESSORS (1997) (5)
The structural simulation toolkit :a tool for exploring parallel architectures and applications. (2007) (5)
Fine-Grained Message Pipelining for Improved MPI Performance (2006) (5)
Comparing the Reliability of PLA and Custom Logic Implementations of a QCA Adder (2008) (5)
Implementing the Jaccard Index on the Migratory Memory-Side Processing Emu Architecture (2018) (5)
Function-based computing and parallelism: A review (1985) (5)
General floorplan for reversible quantum-dot cellular automata (2007) (5)
Yearly Update: Exascale Projections for 2014. (2014) (5)
Cache implications of aggressively pipelined high performance microprocessors (2004) (5)
Design of a mask-programmable memory/multiplier array using G4-FET technology (2008) (4)
Techniques for optimizing loop scheduling (2002) (4)
Energy Usage in an Embedded Space Vision Application on a Tiled Architecture (2011) (4)
Exploiting Thread-Level Parallelism to Build Decision Trees (2006) (4)
Characterization of future deep space computing loads (2003) (4)
Some Initial Explorations into the Hierarchical Multi-core Chip Design Space for HPC Systems (2007) (4)
Improving Quantum Classifier Performance in NISQ Computers by Voting Strategy from Ensemble Learning (2022) (4)
Army Research Laboratory 2009 Annual Review (2009) (3)
Reading the Tea-Leaves: How Architecture Has Evolved at the High End (2014) (3)
8.0 Conclusions and Future Work (1999) (3)
Lightweight Chip Multi-Threading (LCMT): Maximizing Fine-Grained Parallelism On-Chip (2011) (3)
Scalable Software Transactional Memory for Global Address Space Architectures ∗ (2010) (3)
Introducing Streaming into Linear Algebra-based Sparse Graph Algorithms (2019) (3)
Transition Graph Methodology for Estimating Power Dissipation and its Application to Latch Design (1996) (3)
Modeling bounds on migration overhead for a traveling thread architecture (2010) (3)
Estimation of performance and power of simd processors (2005) (3)
Models for generating locality-tuned traveling threads for a hierarchical multi-level heterogeneous multicore (2010) (3)
Updating the Energy Model for Future Exascale Systems (2015) (3)
Facing up to the Inevitable: Intelligent Error Recovery in Massively Parallel Processing in Memory Architectures (2006) (3)
Real time artificial intelligence system (1995) (2)
Implementing Sparse Linear Algebra Kernels on the Lucata Pathfinder-A Computer (2020) (2)
Scalability of Sparse Matrix Dense Vector Multiply (SpMV) on a Migrating Thread Architecture (2020) (2)
Parallel content-based image analysis on PIM processors (1998) (2)
Processor-In-Memory (PIM) Based Architectures for PetaFlops Potential Massively Parallel Processing (1996) (2)
Yield Estimation of Molecular QCA Memory Structures with Geometric Analysis (2008) (2)
Introducing mNUMA: an extended PGAS architecture (2010) (2)
Optimizing the internal microarchitecture and isa of a traveling thread pim system (2011) (2)
Optimizing data scheduling on processor-in-memory arrays (1998) (2)
Scalability of Hybrid SpMV on Intel Xeon Phi Knights Landing (2019) (2)
[2009] Exploring the Possible Past Futures of a Single Part Type Multi-core PIM Chip (2010) (2)
Polygonal path approximation with angle constraints (2001) (2)
GrowHON: A Scalable Algorithm for Growing Higher-order Networks of Sequences (2020) (2)
Fault Tolerant Computer Network Study (1980) (2)
Teaching students computer architecture for new, nanotechnologies (2002) (2)
Organizing wires for reliability in magnetic QCA (2009) (2)
Reversibility for nanoscale systems (2009) (2)
Partially reversible pipelined QCA circuits : combining power and throughput (2006) (2)
for Energy Efficiency* Optimization of High-Performance Superscalar Architectures (2000) (1)
Processor in memory (2002) (1)
Locality: The 3rd Wall and the Need for Innovation in Parallel Architectures (2021) (1)
Scalability of Streaming on Migrating Threads (2020) (1)
Deluge: Achieving Superior Efficiency, Throughput, and Scalability with Actor Based Streaming on Migrating Threads (2021) (1)
Machine Learning Algorithm Performance on the Lucata Computer (2020) (1)
Issues for the future of supercomputing: impact of Moore's law and architecture on application performance (2006) (1)
Memory-Based Structured Application Specific Integrated Circuit (ASIC) Study (2008) (1)
Data Scheduling on Processor-In-Memory Arrays Based on Data Placement and Data Movement (1997) (1)
Scalability of Streaming Anomaly Detection in an Unbounded Key Space Using Migrating Threads (2021) (1)
Multi-threading Semantics for Highly Heterogeneous Systems Using Mobile Threads (2019) (1)
Passel: Improved Scalability and Efficiency of Distributed SVM using a Cacheless PGAS Migrating Thread Architecture (2021) (1)
Prototyping Execution Models for HTMT Petaflop Machine in Java (1999) (1)
XML Based File Format for QCADesigner (2004) (1)
Cost / Performance Analysis of a Multithreaded PIM Architecture (2005) (1)
New approaches to spaceborne computing (1998) (1)
Greatly Accelerated Scaling of Streaming Problems with A Migrating Thread Architecture (2021) (1)
Declarative Computing: A Technology Driver (1992) (0)
Reducing Communication Costs in Multiple Multicasts by Message Scheduling and Re-routing (1997) (0)
Sockets Router Sockets GPU Sockets ( b ) Lightweight Board : Blue Gene / Q ( a ) Hybrid Board : Cray XK ! 7 DDR DIMMs DDR Chips DDR DIMMs GDDR DRAM Chips (2013) (0)
Using method lookup caches and register windowing to speed up dynamically-bound object-oriented applications (1996) (0)
Recomposing an Irregular Algorithm Using a Novel Low-Level PGAS Model (2011) (0)
Redundancy in Multi-core Memory-Rich Application-Specific PIM Chips (2006) (0)
Morphable Computer Architectures for Highly Energy Aware Systems (2004) (0)
Discussion on "AI & Scientific Computing: Are They Incompatible?" (1987) (0)
Design and Simulation of a Programmable Memory/Multiplier Array Using G4-FET Technology (2007) (0)
ParLearning 2016 Keynote (2016) (0)
Cache Oblivious Strategies to Exploit Multi-Level Memory on Manycore Systems (2020) (0)
Computing within Memory Using Transforms (1997) (0)
Efficient Data Placement and Replacement Algorithms for Multiple-Level Memory (2007) (0)
Workshop 20 introduction: Workshop on multithreaded architectures and applications - MTAAP’08 (2008) (0)
Compile-time priority assignment and re-routing for communication minimization in parallel systems (1998) (0)
The Shape of Things to Come: Future Potential of "Heavy Node" Multi-Core HPC Architectures (2008) (0)
1989 International Conference on Parallel Processing, University Park, PA, Aug. 8-12, 1989, Proceedings. Volume 3 - Algorithms and applications (1989) (0)
Multi-Level Memory Algorithmics for Large Sparse Problems. (2019) (0)
Design and characterization of a clock distribution circuit for QCA (2006) (0)
SMT Possibilities for Decoupled Architecture (0)
Algorithms and applications (1989) (0)
Frontier vs the Exascale Report: Why so long? and Are We Really There Yet? (2022) (0)
The implications of spatial locality on scientific computing benchmark selection and analysis. (2005) (0)
Towards Advantages of Parameterized Quantum Pulses (2023) (0)
Inferencing production control computer system (1997) (0)
Migratory Memory-Side Processing Breakthrough Architecture for Graph Analytics (2018) (0)
The Evolution of a New Model of Computation (2022) (0)
Hardware/software codesign for video compression using the EXECUBE processing array (1997) (0)
Mobile-Subjective Programming for massively multithreaded shared memory applications (2010) (0)
An Exploration of Tiled Architectures for Space Applications (2009) (0)
Exploring Strategies to Improve Locality Across Many-Core Affinities (2021) (0)
Instruction Control Mechanisms for Simplified Low Power-Multi-Cluster Microarchitectures (1999) (0)
Avionics, artificial intelligence, and embedded processing systems (1987) (0)
Exploiting Morphable Microarchitectures for Saving Energy (2001) (0)
Preface (1994) (0)
Application Performance of Physical System Simulations (2019) (0)
Accelerating object-oriented applications using method lookup caches and register windowing (1999) (0)
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, New York, NY, USA, April 18-19, 2002 (2002) (0)
A Mi roserver View of HTMT : New Ben hmarks andAppli ations for HTMTTe hni al (2000) (0)
Mining the DataSheets: Unveiling the True Efficiency of Modern Microprocessor Design (1998) (0)
A Microserver View of HTMT : New Benchmarks and Applications for HTMT Technical Report (0)
1989 International Conference on Parallel Processing, University Park, PA, Aug. 8-12, 1989, Proceedings. Volume 2 - Software (1989) (0)
Custom-Enabled System Architectures for High End Computing (2004) (0)

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What Schools Are Affiliated With Peter Kogge?

Peter Kogge is affiliated with the following schools:

Peter Kogge's Academic­Influence.com Rankings