R. Iris Bahar
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Professor at the school of engineering, Brown University
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Electrical Engineering
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Applied Physics
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Engineering
Why Is R. Iris Bahar Influential?
(Suggest an Edit or Addition)According to Wikipedia, R. Iris Bahar is Department Head of Computer Science at the Colorado School of Mines. Previously, she was professor at the School of Engineering at Brown University. Her interests include computer architecture; computer-aided design for synthesis, verification and low-power applications; and design, test, and reliability issues for nanoscale systems.
R. Iris Bahar's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- Algebraic decision diagrams and their applications (1993) (775)
- DRUM: A Dynamic Range Unbiased Multiplier for approximate applications (2015) (244)
- Algebric Decision Diagrams and Their Applications (1997) (239)
- Power and energy reduction via pipeline balancing (2001) (194)
- ABACUS: A technique for automated behavioral synthesis of approximate computing circuits (2014) (159)
- Power and performance tradeoffs using various caching strategies (1998) (138)
- A probabilistic-based design methodology for nanoscale computation (2003) (119)
- Designing logic circuits for probabilistic computation in the presence of noise (2005) (95)
- Architectures for silicon nanoelectronics and beyond (2007) (94)
- Understanding the impact of precision quantization on the accuracy and energy of neural networks (2016) (94)
- Runtime configurable deep neural networks for energy-accuracy trade-off (2016) (67)
- Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors (2000) (56)
- Automated High-Level Generation of Low-Power Approximate Computing Circuits (2019) (52)
- Nano, quantum and molecular computing: implications to high level design and validation (2004) (47)
- Parametric yield management for 3D ICs: Models and strategies for improvement (2008) (46)
- A low-power dynamic divider for approximate applications (2016) (45)
- Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems (2010) (43)
- Timing analysis of combinational circuits using ADDs (1994) (40)
- Using Implications for Online Error Detection (2008) (40)
- The non-critical buffer: using load latency tolerance to improve data cache efficiency (1999) (40)
- Computing the Maximum Power Cycles of a Sequential Circuit (1995) (38)
- Nano, Quantum and Molecular Computing (2004) (38)
- Strategies for improving the parametric yield and profits of 3D ICs (2007) (38)
- A probabilistic-based design for nanoscale computation (2004) (37)
- Designing Nanoscale Logic Circuits Based on Markov Random Fields (2007) (36)
- A Cost Effective Approach for Online Error Detection Using Invariant Relationships (2010) (32)
- Energy reduction in multiprocessor systems using transactional memory (2005) (32)
- A Symbolic Method To Reduce Power Consumption Of Circuits Containing False Paths (1994) (30)
- Energy-Aware Microprocessor Synchronization : Transactional Memory vs . Locks (2006) (28)
- A Probabilistic Approach to Nano-computing (2003) (27)
- Hardware acceleration of feature detection and description algorithms on low-power embedded platforms (2016) (26)
- A novel parallel Tier-1 coder for JPEG2000 using GPUs (2011) (26)
- NBTI-aware data allocation strategies for scratchpad memory based embedded systems (2011) (24)
- SoC-TM: Integrated HW/SW support for transactional memory programming on embedded MPSoCs (2011) (24)
- AutoRex: An automated post-silicon clock tuning tool (2009) (23)
- Temperature-insensitive synthesis using multi-vt libraries (2008) (22)
- Thermally-induced soft errors in nanoscale CMOS circuits (2007) (21)
- GRIP: Generative Robust Inference and Perception for Semantic Robot Manipulation in Adversarial Environments (2019) (20)
- Temperature-Insensitive Dual- $V_{\rm th}$ Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence (2010) (20)
- Power/performance advantages of victim buffer in high-performance processors (1999) (20)
- Energy-optimal synchronization primitives for single-chip multi-processors (2009) (20)
- Edge-TM (2017) (19)
- Combining software and hardware monitoring for improved power and performance tuning (2003) (19)
- Energy efficient synchronization techniques for embedded architectures (2008) (19)
- Symbolic computation of logic implications for technology-dependent low-power synthesis (1996) (18)
- Optimizing noise-immune nanoscale circuits using principles of Markov random fields (2006) (18)
- A Model for Soft Errors in the Subthreshold CMOS Inverter (2006) (18)
- A hardware/software framework for supporting transactional memory in a MPSoC environment (2007) (18)
- Enhancing online error detection through area-efficient multi-site implications (2011) (18)
- Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits (2008) (17)
- Trends and Future Directions in Nano Structure Based Computing and Fabrication (2006) (16)
- Designing MRF based Error Correcting Circuits for Memory Elements (2006) (16)
- A comparison of software code reordering and victim buffers (1999) (16)
- Boolean techniques for low power driven re-synthesis (1995) (16)
- Reducing the leakage and timing variability of 2D ICs using 3D ICs (2009) (15)
- High Performance Parallel JPEG2000 Streaming Decoder Using GPGPU-CPU Heterogeneous System (2012) (15)
- A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic (2012) (15)
- Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems (2010) (13)
- Concurrent Data Structures with Near-Data-Processing: an Architecture-Aware Implementation (2019) (12)
- Markov Chain Analysis of Thermally Induced Soft Errors in Subthreshold Nanoscale CMOS Circuits (2009) (12)
- Accurate Timing Analysis using SAT and Pattern-Dependent Delay Models (2007) (11)
- Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths (1997) (11)
- MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits (2006) (11)
- Fetch Halting on critical load misses (2004) (11)
- Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGA-Based Accelerators (2014) (11)
- Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems (2011) (11)
- Power-aware issue queue design for speculative instructions (2003) (10)
- High-performance, cost-effective heterogeneous 3D FPGA architectures (2009) (10)
- A 100-MHz macropipelined VAX microprocessor (1992) (10)
- An Application of ADD-Based Timing Analysis to Combinational Low Power Re-Synthesis (1994) (10)
- Fundamental Thermal Limits on Data Retention in Low-Voltage CMOS Latches and SRAM (2020) (9)
- Guest Editors' Introduction: Challenges for Reliable Design at the Nanoscale (2005) (9)
- Compacting test vector sets via strategic use of implications (2009) (9)
- Techniques for Designing Noise-Tolerant Multi-Level Combinational Circuits (2007) (9)
- Performance Analysis of Wrong-Path Data Cache Accesses (1998) (9)
- Full Two-Dimensional Markov Chain Analysis of Thermal Soft Errors in Subthreshold Nanoscale CMOS Devices (2011) (9)
- Fast Multi-Objective Algorithmic Design Co-Exploration for FPGA-based Accelerators (2012) (8)
- Shot-Noise-Induced Failure in Nanoscale Flip-Flops Part II: Failure Rates in 10-nm Ultimate CMOS (2012) (8)
- Speculative synchronization for coherence-free embedded NUMA architectures (2014) (8)
- Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing (2005) (8)
- Complexity-Effective Issue Queue Design Under Load-Hit Speculation (2002) (7)
- A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors (2006) (7)
- Flexible data allocation for scratch-pad memories to reduce NBTI effects (2013) (7)
- High-performance, cost-effective heterogeneous 3D FPGA architectures (2009) (7)
- Thermal-Aware Design Techniques for Nanometer CMOS Circuits (2008) (6)
- Two-Dimensional Markov Chain Analysis of Radiation-Induced Soft Errors in Subthreshold Nanoscale CMOS Devices (2010) (6)
- RESTA: a robust and extendable symbolic timing analysis tool (2004) (6)
- Attacking memory-hard scrypt with near-data-processing (2019) (6)
- Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009 (2009) (6)
- Timing analysis for full-custom circuits using symbolic DC formulations (2006) (6)
- Power optimization of technology-dependent circuits based on symbolic computation of logic implications (2000) (6)
- Workshops on Extreme Scale Design Automation (ESDA) Challenges and Opportunities for 2025 and Beyond (2020) (6)
- Robust Object Estimation using Generative-Discriminative Inference for Secure Robotics Applications (2018) (6)
- Playing with Fire: Transactional Memory Revisited for Error-Resilient and Energy-Efficient MPSoC Execution (2015) (6)
- “Scaling” the impact of EDA education Preliminary findings from the CCC workshop series on extreme scale design automation (2013) (6)
- Using implications to choose tests through suspect fault identification (2013) (5)
- NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems (2012) (5)
- A low-power in-order/out-of-order issue queue (2004) (5)
- Detecting errors using multi-cycle invariance information (2009) (5)
- Evaluating critical bits in arithmetic operations due to timing violations (2017) (5)
- A dynamically reconfigurable mixed in-order/out-of-order issue queue for power-aware microprocessors (2003) (5)
- A Simulation Framework for Analyzing Transient Effects Due to Thermal Noise in Sub-Threshold Circuits (2015) (5)
- A fast simulator for the analysis of sub-threshold thermal noise transients (2016) (4)
- An ADD-based algorithm for shortest path back-tracing of large graphs (1994) (4)
- Effects of speculation on performance and issue queue design (2004) (4)
- Design of error-resilient logic gates with reinforcement using implications (2016) (4)
- A Sub-Threshold Noise Transient Simulator Based on Integrated Random Telegraph and Thermal Noise Modeling (2018) (4)
- Energy-Efficient and High-Performance Lock Speculation Hardware for Embedded Multicore Systems (2015) (4)
- Hardware Acceleration of Robot Scene Perception Algorithms (2020) (3)
- Hardware Acceleration of Monte-Carlo Sampling for Energy Efficient Robust Robot Manipulation (2020) (3)
- Symbolic failure analysis of custom circuits due to excessive leakage current (2003) (3)
- Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis (2011) (3)
- Using Existing Reconfigurable Logic in 3D Die Stacks for Test (2016) (3)
- Built-in Self-Repair in a 3D die stack using programmable logic (2013) (3)
- Energy implications of multiprocessor synchronization (2006) (3)
- Conference Reports: Report on the 2017 International Conference on Computer-Aided Design (ICCAD) (2018) (2)
- IgnoreTM: Opportunistically Ignoring Timing Violations for Energy Savings using HTM (2019) (2)
- Techniques for Fault Reduction in Out-of-Order Microprocessors (2005) (2)
- Barrier Synchronization vs. Voltage Noise: A Quantitative Analysis* (2019) (2)
- Proceedings of the 20th symposium on Great lakes symposium on VLSI (2010) (2)
- Special Session: Does Approximation Make Testing Harder (or Easier)? (2019) (2)
- Repairing a 3-D Die-Stack Using Available Programmable Logic (2015) (2)
- HybriDS: Cache-Conscious Concurrent Data Structures for Near-Memory Processing Architectures (2022) (2)
- Transparent and energy-efficient speculation on NUMA architectures for embedded MPSoCs (2013) (2)
- Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices (2010) (2)
- CMOS dynamic power estimation based on collapsible current source transistor modeling (1995) (2)
- Instruction Queue Based Transient Error Identification and Correction through Cost-Effective Hardware ECC (1)
- Power , Delay , and Area Constrained Synthesis for Mixed Domino / Static Logic Optimization (1)
- Testing Aspects of Nanotechnology Trends (2008) (1)
- Thrifty-malloc: A HW/SW codesign for the dynamic management of hardware transactional memory in embedded multicore systems (2016) (1)
- Power and energy-aware architectural techniques for high-performance uniprocessor and multiprocessor systems (2006) (1)
- Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack (2019) (1)
- Ensuring temperature-insensitivity of dual-Vt designs through ITD-aware synthesis (2008) (1)
- Conference Reports: Recap of the 37th Edition of the International Conference on Computer-Aided Design (ICCAD 2018) (2019) (1)
- Reducing issue queue power for multimedia applications using a feedback control algorithm (2004) (1)
- A Reconfigurable Hardware Library for Robot Scene Perception (2022) (1)
- Improving the testability and reliability of sequential circuits with invariant logic (2010) (1)
- A Research Tool for the Power and Performance Analysis of Sensor-Based Mobile Robots (2017) (1)
- Comprehensive comparison of gradient-based cross-spectral stereo matching generated disparity maps (2017) (1)
- Thermal Noise-Induced Error Simulation Framework for Subthreshold CMOS SRAM (2019) (1)
- Designing Nanoscale Logic Circuits Based on Principles of Markov Random Fields (2008) (1)
- Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies (2008) (0)
- Introduction to special section: Best of NANOARCH 2008 (2009) (0)
- Using Human-Guided Causal Knowledge for More Generalized Robot Task Planning (2021) (0)
- Dynamically reconfiguring resources to reduce power dissipation in high-performance microprocessors (2005) (0)
- Automated High-Level Synthesis of Low Power / Area Approximate Computing Circuits Kumud Nepal (2014) (0)
- Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation (2008) (0)
- Voltage Noise Mitigation With Barrier Approximation (2020) (0)
- A Cost Effective Approach For Online Error (2009) (0)
- Hardware Transactional Memory Exploration in Coherence-Free Many-Core Architectures (2018) (0)
- Symbolic Failure Analysis of Custom CMOS Circuits due to Excessive Leakage Current (0)
- Algorithms of All Pair Shortest Path Problem (2016) (0)
- FPGA Synthesis and CAD for Reconfigurable Systems (2009) (0)
- Investigating Energy / Performance Tradeoffs using Transactional Memory in a MPSoC Environment (2006) (0)
- Part III - Nano-scale quantum computing: preface (2004) (0)
- Trends and FutureDirections inNano Structure Based Computingand Fabrication (2006) (0)
- Introduction to the Special Issue on Reliable, Resilient, and Robust Design of Circuits and Systems (2015) (0)
- HybriDS (2022) (0)
- Exploiting Hardware Transactional Memory for Error-Resilient and Energy-Efficient Execution (2015) (0)
- Towards the Simulation Based Design and Validation of Mobile Robotic Cyber-Physical Systems (2018) (0)
- Eliminating Micro-Architectural Side-Channel Attacks using Near Memory Processing (2022) (0)
- EDAML 2022 Invited Speaker 3: Scalable ML Architectures for Real-time Energy-efficient Computing (2022) (0)
- Part I - Nano-computing at the physical layer: preface (2004) (0)
- Harnessing an FPGA for Built-in Self-Repair in a 3 D Die Stack (2013) (0)
- Timing Analysis for Full-Custom Circuits Using (2006) (0)
- Hardware Acceleration of Nonparametric Belief Propagation for Efficient Robot Manipulation (2022) (0)
- Hardware Transactional Memory Exploration in Coherence-Free Many-Core Architectures (2018) (0)
- Symbolic methods for reliability and timing analysis for full-custom circuits (2006) (0)
- Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010 (2010) (0)
- Acceleration Techniques for Energy Efficient Sampling based Machine Learning (2020) (0)
- Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies (2008) (0)
- Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits (2021) (0)
- Dual-Vt assignment policies in ITD-aware synthesis (2010) (0)
- Towards Hardware Accelerated Garbage Collection with Near-Memory Processing (2022) (0)
- Test Architecture for Fine Grained Capture Power Reduction (2019) (0)
- NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems (2012) (0)
- Part IV - Validation of nano-scale architectures: preface (2004) (0)
- Part II - Defect tolerant nono-computing: preface (2004) (0)
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