Ramesh Karri

Q: What Schools Are Affiliated With Ramesh Karri

Ramesh Karri is affiliated with the following schools: University of Delaware, New York University

Ramesh Karri's AcademicInfluence.com Rankings

Ramesh Karri

Engineering

#4840

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#6062

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Electrical Engineering

#1271

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#1361

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engineering Degrees

Ramesh Karri

Computer Science

#6169

World Rank

#6504

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#3282

World Rank

#3420

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computer-science Degrees

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Engineering
Computer Science

Ramesh Karri's Degrees

PhD Electrical Engineering University of California, Berkeley
Masters Electrical Engineering University of California, Berkeley

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Ramesh Karri's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

A Primer on Hardware Security: Models, Methods, and Metrics (2014) (471)
Trustworthy Hardware: Identifying and Classifying Hardware Trojans (2010) (446)
Security analysis of logic obfuscation (2012) (400)
Security analysis of integrated circuit camouflaging (2013) (349)
Scan based side channel attack on dedicated hardware implementations of Data Encryption Standard (2004) (345)
Fault Analysis-Based Logic Encryption (2015) (326)
Secure Scan: A Design-for-Test Architecture for Crypto Chips (2005) (316)
The Cybersecurity Landscape in Industrial Control Systems (2016) (252)
The Robust QCA Adder Designs Using Composable QCA Building Blocks (2007) (238)
On Improving the Security of Logic Locking (2016) (232)
Hardware Trojans (2016) (221)
Manufacturing and Security Challenges in 3D Printing (2016) (194)
Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers (2002) (194)
On design vulnerability analysis and trust benchmarks development (2013) (193)
Is split manufacturing secure? (2013) (175)
Attacks and Defenses for JTAG (2010) (155)
Parity-Based Concurrent Error Detection of Substitution-Permutation Network Block Ciphers (2003) (142)
Logic encryption: A fault analysis perspective (2012) (138)
Low cost concurrent error detection for the advanced encryption standard (2004) (133)
Hardware security: Threat models and metrics (2013) (121)
Leveraging Memristive Systems in the Construction of Digital Logic Circuits (2012) (119)
Hardware and embedded security in the context of internet of things (2013) (117)
Quantum-Dot Cellular Automata Design Guideline (2005) (115)
Fault-based side-channel cryptanalysis tolerant Rijndael symmetric block cipher architecture (2001) (113)
Nano-PPUF: A Memristor-Based Security Primitive (2012) (105)
NumChecker: Detecting kernel control-flow modifying rootkits by using Hardware Performance Counters (2013) (99)
Towards designing robust QCA architectures in the presence of sneak noise paths (2005) (97)
Are hardware performance counters a cost effective way for integrity checking of programs (2011) (97)
Trustworthy Hardware: Trojan Detection and Design-for-Trust Challenges (2011) (94)
Detecting malicious modifications of data in third-party intellectual property cores (2015) (93)
An Energy-Efficient Memristive Threshold Logic Circuit (2012) (91)
Sensor physical unclonable functions (2010) (90)
Sneak-Path Testing of Crossbar-Based Nonvolatile Random Access Memories (2013) (88)
Nano Meets Security: Exploring Nanoelectronic Devices for Security Applications (2015) (87)
Regaining Trust in VLSI Design: Design-for-Trust Techniques (2014) (83)
Design and analysis of ring oscillator based Design-for-Trust technique (2011) (83)
ConFirm: Detecting firmware modifications in embedded systems using Hardware Performance Counters (2015) (79)
Security analysis of concurrent error detection against differential fault analysis (2015) (77)
Simultaneous scheduling and binding for power minimization during microarchitecture synthesis (1995) (71)
Cybersecurity for Control Systems: A Process-Aware Perspective (2016) (68)
Towards a comprehensive and systematic classification of hardware Trojans (2010) (68)
Recomputing with Permuted Operands: A Concurrent Error Detection Approach (2013) (67)
NIST Post-Quantum Cryptography- A Hardware Evaluation Study (2019) (66)
Architectures and protocols that enable new applications on optical networks (2001) (64)
Reusing Hardware Performance Counters to Detect and Identify Kernel Control-Flow Modifying Rootkits (2016) (63)
Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit symmetric block ciphers (2001) (63)
Building Trustworthy Systems Using Untrusted Components: A High-Level Synthesis Approach (2016) (63)
Modeling, Detection, and Diagnosis of Faults in Multilevel Memristor Memories (2015) (61)
Memristor based programmable threshold logic array (2010) (59)
A High Speed Architecture for Galois/Counter Mode of Operation (GCM) (2005) (59)
Automatic Synthesis of Self-Recovering VLSI Systems (1996) (57)
Public Plug-in Electric Vehicles + Grid Data: Is a New Cyberattack Vector Viable? (2019) (56)
Scan-based attacks on linear feedback shift register based stream ciphers (2011) (55)
Asleep at the Keyboard? Assessing the Security of GitHub Copilot’s Code Contributions (2021) (52)
Hardware Performance Counter-Based Malware Identification and Detection with Adaptive Compressive Sensing (2016) (47)
Security Assessment of Cyberphysical Digital Microfluidic Biochips (2016) (46)
Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures (1994) (43)
Additive Manufacturing Cyber-Physical System: Supply Chain Cybersecurity and Risks (2020) (43)
Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage (2016) (42)
Logic Mapping in Crossbar-Based Nanoarchitectures (2009) (42)
Cybersecurity of Smart Electric Vehicle Charging: A Power Grid Perspective (2020) (42)
Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPs Through Security- Driven Task Scheduling (2013) (42)
Minimizing energy consumption of secure wireless session with QoS constraints (2002) (41)
Secure Randomized Checkpointing for Digital Microfluidic Biochips (2018) (41)
Fault secure datapath synthesis using hybrid time and hardware redundancy (2004) (41)
Securing Hardware Accelerators: A New Challenge for High-Level Synthesis (2018) (41)
Optimizing the Energy Consumed by Secure Wireless Sessions – Wireless Transport Layer Security Case Study (2003) (41)
Transformation-based high-level synthesis of fault-tolerant ASICs (1992) (41)
Invariance-based concurrent error detection for Advanced Encryption Standard (2012) (40)
BRAIN: BehavioR Based Adaptive Intrusion Detection in Networks: Using Hardware Performance Counters to Detect DDoS Attacks (2016) (40)
VLSI testing based security metric for IC camouflaging (2013) (40)
High-level synthesis for security and trust (2013) (40)
An Approach to Tolerate Process Related Variations in Memristor-Based Applications (2011) (39)
TAO: Techniques for Algorithm-Level Obfuscation during High-Level Synthesis (2018) (39)
Novel Test-Mode-Only Scan Attack and Countermeasure for Compression-Based Scan Architectures (2015) (38)
New scan-based attack using only the test mode (2013) (38)
Malicious Firmware Detection with Hardware Performance Counters (2016) (38)
Shielding and securing integrated circuits with sensors (2014) (38)
Sneak-path Testing of Memristor-based Memories (2013) (38)
Security-aware SoC test access mechanisms (2011) (37)
Topology aware mapping of logic functions onto nanowire-based crossbar architectures (2006) (36)
Fault tolerant quantum cellular array (QCA) design using triple modular redundancy with shifted operands (2005) (36)
Scheduling with rollback constraints in high-level synthesis of self-recovering ASICs (1992) (36)
Run-time detection of hardware Trojans: The processor protection unit (2013) (35)
Time-constrained scheduling during high-level synthesis of fault-secure VLSI digital signal processors (1996) (35)
Blue team red team approach to hardware trust assessment (2011) (35)
Hardware security strategies exploiting nanoelectronic circuits (2013) (34)
Microfluidic encryption of on-chip biochemical assays (2016) (34)
Electromigration reliability enhancement via bus activity distribution (1996) (34)
Toward Future Systems with Nanoscale Devices: Overcoming the Reliability Challenge (2011) (33)
Anomaly Detection in Real-Time Multi-Threaded Processes Using Hardware Performance Counters (2020) (32)
Automotive Electrical and Electronic Architecture Security via Distributed In-Vehicle Traffic Monitoring (2017) (31)
MAGIC: Malicious Aging in Circuits/Cores (2015) (31)
A Theoretical Study of Hardware Performance Counters-Based Malware Detection (2020) (30)
Concurrent Error Detection Schemes for Involution Ciphers (2004) (30)
NNoculation: Broad Spectrum and Targeted Treatment of Backdoored DNNs (2020) (30)
Security Vulnerabilities of Emerging Nonvolatile Main Memories and Countermeasures (2015) (30)
Reconciling the IC test and security dichotomy (2013) (29)
TaintHLS: High-Level Synthesis for Dynamic Information Flow Tracking (2019) (29)
Improving Tolerance to Variations in Memristor-Based Applications Using Parallel Memristors (2015) (28)
Security of Cloud FPGAs: A Survey (2020) (28)
Detection, diagnosis, and repair of faults in memristor-based memories (2014) (28)
High-reliability, low-energy microarchitecture synthesis (1998) (28)
Computer Aided Design of Fault-Tolerant Application Specific Programmable Processors (2000) (28)
Process-Aware Covert Channels Using Physical Instrumentation in Cyber-Physical Systems (2018) (27)
High-Level Synthesis of Fault-Secure Microarchitectures (1993) (27)
Shielding heterogeneous MPSoCs from untrustworthy 3PIPs through security-driven task scheduling (2014) (27)
Synthesis Of Application Specific Programmable Processors (1997) (26)
Nanoelectronic Solutions for Hardware Security (2012) (26)
ASSURE: RTL Locking Against an Untrusted Foundry (2020) (26)
Can OpenAI Codex and Other Large Language Models Help Us Fix Security Bugs? (2021) (26)
Introspection: A register transfer level technique for cocurrent error detection and diagnosis in data dominated designs (2001) (25)
Logic Level Fault Tolerance Approaches Targeting Nanoelectronics PLAs (2007) (25)
Provably Secure Concurrent Error Detection Against Differential Fault Analysis (2012) (25)
Belling the CAD: Toward Security-Centric Electronic System Design (2015) (25)
An Empirical Cybersecurity Evaluation of GitHub Copilot's Code Contributions (2021) (24)
Securing Processors Against Insider Attacks: A Circuit-Microarchitecture Co-Design Approach (2013) (24)
SLICED: Slide-based concurrent error detection technique for symmetric block ciphers (2010) (23)
Towards Secure Analog Designs: A Secure Sense Amplifier Using Memristors (2014) (23)
Locking of biochemical assays for digital microfluidic biochips (2018) (22)
Fault Tolerant Approaches to Nanoelectronic Programmable Logic Arrays (2007) (22)
Test-mode-only scan attack using the boundary scan chain (2014) (22)
Architecture Support for Dynamic Integrity Checking (2012) (22)
A Hardware Evaluation Study of NIST Post-Quantum Cryptographic Signature schemes (2019) (21)
A hardware-accelerated implementation of the RSVP-TE signaling protocol (2004) (21)
On-line error detection and BIST for the AES encryption algorithm with different S-box implementations (2005) (21)
Securing pressure measurements using SensorPUFs (2016) (20)
Hardware implementation of a signaling protocol (2002) (20)
A Survey of Cybersecurity of Digital Manufacturing (2020) (20)
Opening the Doors to Dynamic Camouflaging: Harnessing the Power of Polymorphic Devices (2018) (20)
Phantom redundancy: a high-level synthesis approach for manufacturability (1995) (19)
CAD-Base: An Attack Vector into the Electronics Supply Chain An (2019) (19)
Fault Attacks on AES and Their Countermeasures (2016) (19)
Sneak path testing and fault modeling for multilevel memristor-based memories (2013) (19)
Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking (2020) (19)
Parity-based concurrent error detection in symmetric block ciphers (2003) (19)
FPGA Trust Zone: Incorporating trust and reliability into FPGA designs (2016) (19)
Security implications of cyberphysical digital microfluidic biochips (2015) (19)
Security Implications of Cyberphysical Flow-Based Microfluidic Biochips (2017) (18)
A high-performance, low-overhead microarchitecture for secure program execution (2012) (18)
Optimal checkpointing for secure intermittently-powered IoT devices (2017) (18)
Test-mode-only scan attack and countermeasure for contemporary scan architectures (2014) (18)
Hardware Trojan Detection Using the Order of Path Delay (2018) (18)
A study on the effectiveness of Trojan detection techniques using a red team blue team approach (2013) (17)
Scan attack in presence of mode-reset countermeasure (2013) (16)
Concurrent error detection for involutional functions with applications in fault-tolerant cryptographic hardware design (2006) (16)
A Design Methodology For The High-level Synthesis Of Fault-tolerant Asics (1992) (16)
Toward Secure and Trustworthy Cyberphysical Microfluidic Biochips (2019) (16)
Security challenges during VLSI test (2011) (15)
Algorithm level re-computing-a register transfer level concurrent error detection technique (2001) (15)
Idle cycles based concurrent error detection of RC6 encryption, [FPGAs] (2001) (14)
Exploring eFPGA-based Redaction for IP Protection (2021) (14)
Nanofabric topologies and reconfiguration algorithms to support dynamically adaptive fault tolerance (2006) (14)
Emerging (un-)reliability based security threats and mitigations for embedded systems: special session (2017) (14)
High-level synthesis of fault-tolerant ASICs (1992) (14)
Cyber security threat modeling in the AEC industry: An example for the commissioning of the built environment (2021) (14)
Power optimization using divide-and-conquer techniques for minimization of the number of operations (1997) (14)
Algorithm-level recomputing with shifted operands-a register transfer level concurrent error detection technique (2006) (14)
Bio-Protocol Watermarking on Digital Microfluidic Biochips (2019) (14)
Optimal algorithms for synthesis of reliable application-specific heterogeneous multiprocessors (1995) (13)
Scan Based Side Channel Attack on Data Encryption Standard (2004) (13)
Security Assessment of Micro-Electrode-Dot-Array Biochips (2019) (13)
Adversarial Perturbation Attacks on ML-based CAD (2020) (13)
Design of a high-performance RSVP-TE hardware signaling accelerator (2005) (13)
Execution of provably secure assays on MEDA biochips to thwart attacks (2019) (13)
New scan attacks against state-of-the-art countermeasures and DFT (2014) (13)
Computer-Aided Design of Fault-Tolerant VLSI Systems (1996) (13)
Poisoning the (Data) Well in ML-Based CAD: A Case Study of Hiding Lithographic Hotspots (2020) (13)
Versatile BIST: An Integrated Approach to On-line/Off-line BIST for Data-Dominated Architectures (1998) (13)
Algorithm level re-computing with shifted operands-a register transfer level concurrent error detection technique (2000) (13)
On the Difficulty of Inserting Trojans in Reversible Computing Architectures (2017) (12)
Black-Hat High-Level Synthesis: Myth or Reality? (2019) (12)
Divide-and-concatenate: an architecture-level optimization technique for universal hash functions (2004) (12)
Multi-Tenant FPGA-based Reconfigurable Systems: Attacks and Defenses (2019) (12)
Toward Increasing the Difficulty of Reverse Engineering of RSFQ Circuits (2020) (12)
Examining Zero-Shot Vulnerability Repair with Large Language Models (2021) (12)
Built in self test: a complete test solution for telecommunication systems (1999) (12)
A High-Speed Hardware Architecture for Universal Message Authentication Code (2006) (11)
Controlling your control flow graph (2016) (11)
Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics (2006) (11)
Modeling energy efficient secure wireless networks using network simulation (2003) (11)
Can the SHIELD protect our integrated circuits? (2014) (11)
Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided Attacks (2021) (11)
Feasibility study of dynamic Trusted Platform Module (2010) (11)
Register Transfer Level Concurrent Error Detection in Elliptic Curve Crypto Implementations (2007) (11)
PREEMPT: PReempting Malware by Examining Embedded Processor Traces (2019) (11)
Are Adversarial Perturbations a Showstopper for ML-Based CAD? A Case Study on CNN-Based Lithographic Hotspot Detection (2019) (11)
Online VLSI Testing (1998) (10)
Toward Secure Microfluidic Fully Programmable Valve Array Biochips (2019) (10)
Introspection: a low overhead binding technique during self-diagnosing microarchitecture synthesis (1996) (10)
Is Register Transfer Level Locking Secure? (2020) (10)
Desieve the Attacker: Thwarting IP Theft in Sieve-Valve-based Biochips (2019) (10)
CYSEP - a cyber-security processor for 10 Gbps networks and beyond (2004) (10)
NREPO: Normal basis Recomputing with Permuted Operands (2014) (10)
Towards Reverse Engineering Reversible Logic (2017) (10)
Secure design-for-debug for Systems-on-Chip (2015) (10)
CAD-Base (2019) (10)
Secure and Flexible Trace-Based Debugging of Systems-on-Chip (2016) (10)
Security Trade-Offs in Microfluidic Routing Fabrics (2017) (10)
Tamper-Resistant Pin-Constrained Digital Microfluidic Biochips (2018) (10)
Guest Editorial Special Issue on Secure and Trustworthy Computing (2016) (10)
Fault tolerant arithmetic with applications in nanotechnology based systems (2004) (10)
Architectural-level fault tolerant computation in nanoelectronic processors (2005) (10)
Hardware Architectures for Post-Quantum Digital Signature Schemes (2021) (9)
Programmable Daisychaining of Microelectrodes to Secure Bioassay IP in MEDA Biochips (2020) (9)
System-level power optimization for wireless multimedia communication : power aware computing (2002) (9)
Algorithm level recomputing using allocation diversity: a registertransfer level approach to time redundancy-based concurrent errordetection (2002) (9)
Optimal self-recovering microarchitecture synthesis (1993) (9)
Hot-carrier reliability enhancement via input reordering and transistor sizing (1996) (9)
Securing digital microfluidic biochips by randomizing checkpoints (2016) (9)
Fault tolerant nanoelectronic processor architectures (2005) (9)
Cyber Insurance Against Cyberattacks on Electric Vehicle Charging Stations (2021) (9)
Configurable spare processors: a new approach to system level fault-tolerance (1996) (9)
Towards Nanoelectronics Processor Architectures (2007) (9)
AES design space exploration new line for scan attack resiliency (2014) (9)
On enhancing the debug architecture of a system-on-chip (SoC) to detect software attacks (2015) (9)
Securing IJTAG against data-integrity attacks (2018) (9)
Proceedings of the 2017 ACM on Asia Conference on Computer and Communications Security (2017) (9)
Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique (2002) (8)
Toward Hardware-Based IP Vulnerability Detection and Post-Deployment Patching in Systems-on-Chip (2021) (8)
DPFEE: A High Performance Scalable Pre-Processor for Network Security Systems (2018) (8)
Methodology For Behavioral Synthesis-based Algorithm-level Design Space Exploration: DCT Case Study (1997) (8)
Towards a New Thermal Monitoring Based Framework for Embedded CPS Device Security (2020) (8)
Hardware Trojans Inspired IP Watermarks (2019) (8)
Reversible Circuits: IC/IP Piracy Attacks and Countermeasures (2019) (8)
Heterogeneous built-in resiliency of application specific programmable processors (1996) (8)
A parameterized VHDL library for on-line testing (1997) (8)
Robust Deep Learning for IC Test Problems (2022) (8)
Improving GPU Robustness by making use of faulty parts (2011) (8)
Shadow Attacks on MEDA Biochips (2018) (8)
Boolean Circuit Camouflage: Cryptographic Models, Limitations, Provable Results and a Random Oracle Realization (2017) (7)
MINIMIZING THE SECURE WIRELESS SESSION ENERGY (2001) (7)
DAVE: Deriving Automatically Verilog from English (2020) (7)
Tamper Proofing by Design Using Generalized Involution-Based Concurrent Error Detection for Involutional Substitution Permutation and Feistel Networks (2006) (7)
IC/IP Piracy Assessment of Reversible Logic (2018) (7)
Deep Packet Field Extraction Engine (DPFEE): A pre-processor for network intrusion detection and denial-of-service detection systems (2015) (7)
Vertical IP Protection of the Next-Generation Devices: Quo Vadis? (2021) (7)
Special session: emerging (Un-)reliability based security threats and mitigations for embedded systems (2017) (7)
TAO (2018) (7)
Optimizing Ipsec for Energy-Efficient Secure Wireless Sessions (2002) (7)
Nano, quantum, and molecular computing: are we ready for the validation and test challenges? (2003) (7)
Parallel memristors: Improving variation tolerance in memristive digital circuits (2011) (6)
Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit RC6 block cipher (2003) (6)
Standard seven segmented display for Burmese numerals (1990) (6)
Security Implications of Large Language Model Code Assistants: A User Study (2022) (6)
Algorithm level recomputing with allocation diversity: a register transfer level time redundancy based concurrent error detection technique (2001) (6)
TAINT: Tool for Automated INsertion of Trojans (2017) (6)
Security Assessment of Microfluidic Fully-Programmable-Valve-Array Biochips (2019) (6)
Micropreemption synthesis: an enabling mechanism for multitask VLSI systems (2006) (6)
FLAW3D: A Trojan-Based Cyber Attack on the Physical Outcomes of Additive Manufacturing (2021) (6)
Attacking a CNN-based Layout Hotspot Detector Using Group Gradient Method (2021) (6)
HOLL: Program Synthesis for Higher OrderLogic Locking (2022) (6)
Benchmarking Security Closure of Physical Layouts: ISPD 2022 Contest (2022) (6)
Bias Busters: Robustifying DL-Based Lithographic Hotspot Detectors Against Backdooring Attacks (2020) (6)
Stealthy Rootkits in Smart Grid Controllers (2019) (6)
Approximating the age of RF/analog circuits through re-characterization and statistical estimation (2014) (6)
Exploiting idle cycles for algorithm level re-computing (2002) (6)
A Survey of Microarchitecture Support for Embedded Processor Security (2012) (5)
Compact hardware architectures for BLAKE and LAKE hash functions (2010) (5)
Fingerprinting Field Programmable Gate Arrays (2017) (5)
Security verification of 3rd party intellectual property cores for information leakage (2015) (5)
COPPTCHA: COPPA Tracking by Checking Hardware-Level Activity (2020) (5)
The Association for Computing Machinery/Special Interest Group on Design Automation (ACWSIGDA) presents its Distinguished Service Award (2004) (5)
Rapid prototyping of fault tolerant VLSI systems (1994) (5)
Synthesis of Tamper-Resistant Pin-Constrained Digital Microfluidic Biochips (2020) (5)
Detecting Hardware Trojans in PCBs Using Side Channel Loopbacks (2022) (5)
Power, Area, Speed, and Security (PASS) Trade-Offs of NIST PQC Signature Candidates Using a C to ASIC Design Flow (2019) (5)
New Scan-Based Attack Using Only the Test Mode and an Input Corruption Countermeasure (2013) (5)
Microfluidic Trojan Design in Flow-based Biochips (2020) (5)
Identifying Reversible Circuit Synthesis Approaches to Enable IP Piracy Attacks (2017) (5)
Protection against Counterfeiting Attacks in 3D Printing by Streaming Signature-embedded Manufacturing Process Instructions (2021) (5)
Security and Testing (2012) (5)
Low-Cost Concurrent Error Detection for GCM and CCM (2014) (5)
Detecting Kernel Control-Flow Modifying Rootkits (2014) (5)
Not All Fabrics Are Created Equal: Exploring eFPGA Parameters For IP Redaction (2021) (5)
Area-EfficientFault Detection During Self-Recovering Microarchitecture Synthesis (1994) (5)
Pop Quiz! Can a Large Language Model Help With Reverse Engineering? (2022) (5)
Analysis of Energy Consumed by Secure Session Negotiation Protocols in Wireless Networks (2003) (5)
Abetting Planned Obsolescence by Aging 3D Networks-on-Chip (2018) (5)
Towards 10-100 Gbps crypotographic architectures (2002) (5)
Process-aware side channel monitoring for embedded control system security (2017) (5)
Computer aided design (CAD) model search and retrieval using frequency domain file conversion (2020) (5)
Bio-chemical Assay Locking to Thwart Bio-IP Theft (2019) (5)
Heterogeneous BISR-approach using system level synthesis flexibility (1998) (5)
Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-Chip (2014) (5)
Synthesis of fault-tolerant and real-time microarchitectures (1994) (5)
Security Assessment of Cyberphysical Digital Microfluidic Biochips. (2016) (5)
MAGIC (2015) (5)
Exploiting Small Leakages in Masks to Turn a Second-Order Attack into a First-Order Attack and Improved Rotating Substitution Box Masking with Linear Code Cosets (2015) (5)
NNoculation: Catching BadNets in the Wild (2020) (4)
High-Level Synthesis of Benevolent Trojans (2019) (4)
Design automation for hybrid CMOS-nonoelectronics crossbars (2007) (4)
ALPS: an algorithm for pipeline data path synthesis (1991) (4)
ALICE: an automatic design flow for eFPGA redaction (2022) (4)
Selectively breaking data dependences to improve the utilization of idle cycles in algorithm level re-computing data paths (2003) (4)
Can Monitoring System State + Counting Custom Instruction Sequences Aid Malware Detection? (2019) (4)
Reliable Integrity Checking in Multicore Processors (2015) (4)
Challenges and New Directions for AI and Hardware Security (2020) (4)
Phantom redundancy: a register transfer level technique for gracefully degradable data path synthesis (2002) (4)
Security Closure of Physical Layouts ICCAD Special Session Paper (2021) (4)
Efficient Hardware Implementation of PQC Primitives and PQC algorithms Using High-Level Synthesis (2021) (4)
Security Against Data-Sniffing and Alteration Attacks in IJTAG (2021) (4)
CoFHEE: A Co-processor for Fully Homomorphic Encryption Execution (2022) (4)
High-level synthesis of self-recovering microarchitectures (1992) (4)
Hardware Trojan Detection Using Controlled Circuit Aging (2020) (4)
Secure Assay Execution on MEDA Biochips to Thwart Attacks Using Real-Time Sensing (2020) (4)
Hardware Trojan detection using path delay order encoding with process variation tolerance (2018) (4)
Thwarting Bio-IP Theft Through Dummy-Valve-Based Obfuscation (2021) (3)
Physical Unclonable Functions and Intellectual Property Protection Techniques (2017) (3)
Can Multi-Layer Microfluidic Design Methods Aid Bio-Intellectual Property Protection? (2019) (3)
Locking the Design of Building Blocks for Quantum Circuits (2019) (3)
Allocation and binding during fault-secure microarchitecture synthesis (1994) (3)
ℰℱect olerant layout synthesis (1994) (3)
HOST: HLS Obfuscations against SMT ATtack (2021) (3)
Switch level hot-carrier reliability enhancement of VLSI circuits (1995) (3)
OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesis (2021) (3)
Trustworthy Hardware [Scanning the Issue] (2014) (3)
Balancing performance and fault detection for GPGPU workloads (2012) (3)
Exploiting small leakages in masks to turn a second-order attack into a first-order attack (2015) (3)
How Secure Are Checkpoint-Based Defenses in Digital Microfluidic Biochips? (2021) (3)
System-Level Power Optimization for Wireless Multimedia (2002) (3)
Cyberphysical Microfluidic Biochips (2019) (3)
Exposing Hardware Trojans in Embedded Platforms via Short-Term Aging (2020) (3)
Security Assessment of Microfluidic Immunoassays (2019) (3)
Designing ML-resilient locking at register-transfer level (2022) (3)
Identification of Synthesis Approaches for IP/IC Piracy of Reversible Circuits (2019) (3)
Digital microfluidic biochip security (2017) (3)
Guest Editorial Special Section on Hardware Security and Trust (2015) (3)
Programmable Daisychaining of Microelectrodes for IP Protection in MEDA Biochips (2019) (3)
Secure and Trustworthy Cyberphysical Microfluidic Biochips (2019) (3)
A Composable Design Space Exploration Framework to Optimize Behavioral Locking (2022) (3)
NNoculation (2021) (2)
Engineering crossbar based emerging memory technologies (2012) (2)
Uncertainty quantification in dimensions dataset of additive manufactured NIST standard test artifact (2021) (2)
Optimizing the Use of Behavioral Locking for High-Level Synthesis (2021) (2)
Can flexible, domain specific programmable logic prevent IP theft? (2016) (2)
Split Manufacturing-Based Register Transfer-Level Obfuscation (2019) (2)
IEEE International Symposium on Hardware Oriented Security and Trust (HOST): Past, Present, and Future (2019) (2)
Synthesis of Application Speci c Programmable Processors (1997) (2)
Field Programmable Gate Array Implem Ri (2001) (2)
On the Optimization of Behavioral Logic Locking for High-Level Synthesis (2021) (2)
Special Session: Machine Learning for Semiconductor Test and Reliability (2021) (2)
Power optimization using divide-and-conquer techniques for minimization of the number of operations (1999) (2)
Fixing Hardware Security Bugs with Large Language Models (2023) (2)
Toward Secure Checkpointing for Micro-Electrode-Dot-Array Biochips (2020) (2)
Fault-tolerant vlsi systems (1999) (2)
Simulation and analysis of negative-bias temperature instability aging on power analysis attacks (2015) (2)
Verifying Physical Trustworthiness of ICs and Systems (2009) (2)
A Survey of Cybersecurity and Resilience of Digital Manufacturing (2020) (2)
Can Algorithm Diversity in Stream Cipher Implementation Thwart (Natural and) Malicious Faults? (2016) (2)
Provably Secure Concurrent Error Detection for Advanced Encryption Standard (2014) (2)
Molecular Barcoding as a Defense Against Benchtop Biochemical Attacks on DNA Fingerprinting and Information Forensics (2020) (2)
PREEMPT (2019) (2)
Concurrent error detection architectures for symmetric block ciphers (2000) (2)
Causative Cyberattacks on Online Learning-Based Automated Demand Response Systems (2021) (2)
Micro-preemption synthesis: an enabling mechanism for multi-task VLSI systems (1997) (2)
Guest Editorial Integrated Circuit and System Security (2012) (2)
Explaining and Interpreting Machine Learning CAD Decisions: An IC Testing Case Study (2020) (2)
Analysis and Design of Tamper-Mitigating Microfluidic Routing Fabrics (2020) (2)
Guest Editors' Introduction: Cyber-Physical Systems Security and Privacy (2017) (2)
False Data Injection Attacks on Data Markets for Electric Vehicle Charging Stations (2022) (2)
Power Optimization for Universal Hash Function Data Path Using Divide-and-Concatenate Technique (2005) (2)
A secure design-for-test infrastructure for lifetime security of SoCs (2015) (2)
Special Issue on Emerging Nanoscale Architectures for Hardware Security, Trust, and Reliability: Part 1 (2014) (2)
Lost at C: A User Study on the Security Implications of Large Language Model Code Assistants (2022) (1)
Benchmarking Large Language Models for Automated Verilog RTL Code Generation (2022) (1)
Hardware-Supported Patching of Security Bugs in Hardware IP Blocks (2023) (1)
Applying IC testing concepts to secure ICs (2012) (1)
Register transfer level approach to hybrid time and hardware redundancy based fault secure datapath synthesis (2003) (1)
Learning Malicious Circuits in FPGA Bitstreams (2023) (1)
Anomaly Detection in Embedded Systems Using Power and Memory Side Channels (2020) (1)
A security imbedded authentication protocol (1988) (1)
Low-Cost Concurrent Error Detection for GCM and CCM (2014) (1)
Hack3D: Crowdsourcing the Assessment of Cybersecurity in Digital Manufacturing (2021) (1)
Maximizing the fault-tolerance of application specific programmable signal processors (1996) (1)
High speed architectures for Leviathan: a binary tree based stream cipher (2004) (1)
Divide and concatenate: a scalable hardware architecture for universal MAC (2004) (1)
A constant array multiplier core generator with dynamic partial evaluation architecture selection (abstract only) (2005) (1)
Synthesis of reliable application specific heterogeneous multiprocessors (1995) (1)
Training Data Poisoning in ML-CAD: Backdooring DL-Based Lithographic Hotspot Detectors (2020) (1)
Runtime Malware Detection Using Embedded Trace Buffers (2022) (1)
An investigation into the design of energy-efficient session negotiation protocols for wireless networks (2003) (1)
Concurrent Error Detection Schemes for Fault Based Side-Channel Cryptanalysis of Symmetric Block Ciphers Polytechnic (2002) (1)
Process-Aware Side Channel Shaping and Watermarking for Cyber-Physical Systems (2018) (1)
Security Assessment of Interposer-based Chiplet Integration (2020) (1)
Issues in developing a parametrized VHDL library for on-line testing (1998) (1)
Automatic systems of fault-tolerant vlsi systems (1993) (1)
HPC-Based Malware Detectors Actually Work: Transition to Practice After a Decade of Research (2022) (1)
Fuzzing+Hardware Performance Counters-Based Detection of Algorithm Subversion Attacks on Postquantum Signature Schemes (2022) (1)
Fault Analysis-based Logic Encryption (Preprint) (2013) (1)
High Assurance Virtualization Engine (HAVEN) (2009) (1)
Guest editor's introduction to special section on high-level design validation and test (2001) (1)
Securing Biochemical Samples Using Molecular Barcoding on Digital Microfluidic Biochips* (2021) (1)
A heterogeneous built-in self-repair approach using system-level synthesis flexibility (2004) (1)
Guest Editors' Introduction: Online VLSI Testing (1998) (1)
Cyber Security Threat Modeling in the Construction Industry: A Countermeasure Example During the Commissioning Process (2020) (1)
Don’t CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Design (2022) (1)
Hardware Performance Counters: Ready-Made vs Tailor-Made (2021) (1)
Hybrid silicon CMOS-carbon nanotube physically unclonable functions (2017) (0)
ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning (2023) (0)
Multi-Modal Side Channel Data Driven Golden-Free Detection of Software and Firmware Trojans (2022) (0)
Invited: Independent Verification and Validation of Security-Aware EDA Tools and IP (2021) (0)
Innovation Practices Track: Security in Test and Test for Security (2022) (0)
1 Nanoelectronic Solutions for Hardware Security (2012) (0)
Synthesis of fault-tolerant application specific programmable processors (1998) (0)
Security engineering of nanostructures and nanomaterials (2016) (0)
Error detection method for cryptographic transformation of binary data and circuit arrangement (2002) (0)
2012 JETTA Reviewers (2013) (0)
CUWS - Central University Workstation for VLSI CAD (1988) (0)
Security analysis of concurrent error detection against differential fault analysis (2014) (0)
Globalization of the semiconductor industry and associated supply chains have made integrated circuits increasingly vulnerable to Trojans. Researchers must expand efforts to verify trust in intellectual property cores and ICs. (2011) (0)
Microfluidic Device Security (2020) (0)
3 PIP Vendor SoC Integrator Foundry User O 1 2 3 ? ? ? O ? ? ? O 4 5 6 O ? O 7 8 ? O ? ? ? C C C O ? ? ? (2013) (0)
Mitigation: Tamper-Mitigating Routing Fabrics (2019) (0)
Simulated annealing based yield enhancement of layouts (1994) (0)
We modeled the signaling protocol in VHDL * and then mapped onto two FPGAs on the WILDFORCE TM reconfigurable board – a (2002) (0)
Prevention: Tamper-Resistant Pin-Constrained Digital Microfluidic Biochips (2019) (0)
2.2 Physical Attacks (2019) (0)
Security of Biochip Cyberphysical Systems (2022) (0)
Determining an aspect of behavior of an embedded device such as, for example, detecting unauthorized modifications of the code and/or behavior of an embedded device (2018) (0)
Triple Modular Redundancy with Shifted Operands (2005) (0)
The Industrial Control Systems Cyber Security Landscape (2016) (0)
Protecting Hardware IP Cores During High-Level Synthesis (2022) (0)
Scaling Attacks on Large Logic-Locked Designs (2023) (0)
Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition (2021) (0)
A hardware-accelerated implementation of a signaling protocol (2002) (0)
Algorithmic level recomputing with shifted operands: A high level synthesis approach to concurrent error detection (2000) (0)
Energy-efficient secure embedded systems (2004) (0)
Automatic synthesis of application-specific programmable processors (1998) (0)
Bulls-Eye: Active Few-shot Learning Guided Logic Synthesis (2022) (0)
ALPS: Algorithm for pipelined data path synthsis (1991) (0)
Research Challenges in Security-Aware Physical Design (2017) (0)
Reconciling the Dichotomy Between Test and Security (2013) (0)
Structural Attacks and Defenses for Flow-Based Microfluidic Biochips (2022) (0)
Benchmarking Advanced Security Closure of Physical Layouts: ISPD 2023 Contest (2023) (0)
A survey of Digital Manufacturing Hardware and Software Trojans (2023) (0)
HACK3D: Evaluating Cybersecurity of Additive Manufacturing by Crowdsourcing (2020) (0)
Design trade-offs during fault-tolerant data path synthesis (1999) (0)
2 . 3 FPGA Implementation of Advanced Architectures for AES Block Ciphers (2002) (0)
Leveraging CMOS design tools for QCA designs (2008) (0)
Automatic reconfiguration tool (2001) (0)
Efficient construction of minimal Spanning Tree avoiding rectilinear directional obstacles (2008) (0)
Boole - a hardware description language (1988) (0)
A Community Review of Logic Locking: Reﬂections, Benchmarking, and Outlook (2022) (0)
SCANNING THE ISSUE Trustworthy Hardware (2014) (0)
Maintenance Registers with Boundary Scan Interface (2017) (0)
Computer-aided design-for-reliability of deep sub-micron integrated circuits (1996) (0)
Register transfer level approaches to on-line testing (1999) (0)
Can assay outcomes of digital microfluidic biochips be manipulated (2015) (0)
Trojan Detection in Embedded Systems With FinFET Technology (2022) (0)
High-Level Approaches to Hardware Security: A Tutorial (2022) (0)
Cybersecurity Road Map for Digital Manufacturing (2020) (0)
Tutorial 1 (2012) (0)
Reconfigurable Logic for Hardware IP Protection: Opportunities and Challenges (Invited Paper) (2022) (0)
Conclusions (2019) (0)
DEFending Integrated Circuit Layouts (2023) (0)
Globalization of the semiconductor industry and evolving fabrication processes have made integrated circuits increasingly vulnerable to Trojans (2011) (0)
Tutorial 1 (2012) (0)
Security and Trust (2019) (0)
Hot topic session 12A: Split manufacturing — IARPA's TIC program (2014) (0)
A method for error detection in the cryptographic transforming binary data and circuitry (2002) (0)
Silicon-proven ASIC design for the Polynomial Operations of Fully Homomorphic Encryption (2022) (0)
Editorial (2020) (0)
A Secure Design-for-Test Architecture to Thwart Attacks Throughout The Life Cycle of SoCs (2015) (0)
Cyberattack on Phase-Locked Loops in Inverter-Based Energy Resources (2023) (0)
1 Architectures and Protocols for Optical Networks (2000) (0)
High-level design methods for hardware security: is it the right choice? invited (2022) (0)
Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2012 (2012) (0)
Detection: Randomizing Checkpoints on Cyberphysical Digital Microfluidic Biochips (2019) (0)

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