Rob A. Rutenbar

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Rob A. Rutenbar is affiliated with the following schools: University of Michigan, Wayne State University, Carnegie Mellon University, University of Illinois Urbana-Champaign, University of Pittsburgh

Rob A. Rutenbar's AcademicInfluence.com Rankings

Rob A. Rutenbar

Computer Science

#2838

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#2970

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#1180

USA Rank

Information Systems

#26

World Rank

#29

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USA Rank

Computer Architecture

#47

World Rank

#49

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#24

USA Rank

Database

#4617

World Rank

#4796

Historical Rank

#711

USA Rank

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Computer Science

Why Is Rob A. Rutenbar Influential?

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According to Wikipedia, Rob A. Rutenbar is an American academic noted for contributions to software tools that automate analog integrated circuit design, and custom hardware platforms for high-performance automatic speech recognition. He is Senior Vice Chancellor for Research at the University of Pittsburgh, where he leads the university's strategic and operational vision for research and innovation.

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Rob A. Rutenbar's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Simulated annealing algorithms: an overview (1989) (655)
Computer-aided design of analog and mixed-signal integrated circuits (2000) (558)
OASYS: a framework for analog circuit synthesis (1989) (455)
Synthesis of high-performance analog circuits in ASTRX/OBLX (1996) (354)
KOAN/ANAGRAM II: new tools for device-level analog placement and routing (1991) (298)
Anaconda: simulation-based synthesis of analog circuits viastochastic pattern search (2000) (271)
Addressing substrate coupling in mixed-mode ICs: simulation and power distribution synthesis (1994) (247)
Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs (2007) (225)
Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS (2008) (212)
Reducing power by optimizing the necessary precision/range of floating-point arithmetic (2000) (180)
MAELSTROM: efficient simulation-based synthesis for custom analog cells (1999) (168)
Why Quasi-Monte Carlo is Better Than Monte Carlo or Latin Hypercube Sampling for Statistical Circuit Analysis (2010) (151)
A comparative study of two Boolean formulations of FPGA detailed routing constraints (2001) (143)
Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design (2009) (139)
Statistical Blockade: A Novel Method for Very Fast Monte Carlo Simulation of Rare Circuit Events, and its Application (2007) (136)
Placement by Simulated Annealing on a Multiprocessor (1987) (130)
FPGA routing and routability estimation via Boolean satisfiability (1997) (125)
Remembrance of circuits past: macromodeling by data mining in large analog design spaces (2002) (115)
Fast, accurate static analysis for fixed-point finite-precision effects in DSP designs (2003) (108)
Integer programming based topology selection of cell-level analog circuits (1995) (106)
Towards formal verification of analog designs (2004) (105)
Verifying analog oscillator circuits using forward/backward abstraction refinement (2006) (104)
Canonical Symbolic Analysis of Large Analog Circuits with Determinant Decision Diagrams (2002) (103)
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration (2006) (99)
A prototype framework for knowledge-based analog circuit synthesis (1987) (93)
Satisfiability-based layout revisited: detailed routing of complex FPGAs via search-based Boolean SAT (1999) (90)
Synthesis tools for Mixed-Signal ICs: progress on frontend and backend strategies (1996) (88)
Realizing the potential of data science (2018) (87)
Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modeling (2003) (82)
Automatic layout of custom analog cells in ANAGRAM (1988) (76)
Reengineering the curriculum: design and analysis of a new undergraduate Electrical and Computer Engineering degree at Carnegie Mellon University (1995) (76)
From Finance to Flip Flops: A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit Analysis (2007) (75)
sub-SAT: a formulation for relaxed boolean satisfiability with applications in routing (2003) (73)
A 1000-word vocabulary, speaker-independent, continuous live-mode speech recognizer implemented in a single FPGA (2007) (72)
Exploring multiplier architecture and layout for low power (1996) (72)
Practical, fast Monte Carlo statistical static timing analysis: Why and how (2008) (69)
Analog design automation: Where are we? Where are we going? (1993) (64)
Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design (2008) (64)
CAD solutions and outstanding challenges for mixed-signal and RF IC design (2001) (64)
Computer-Aided Design of Analog Integrated Circuits and Systems (2002) (63)
Scalable trajectory methods for on-demand analog macromodel extraction (2005) (62)
How to automate analog IC designs (1988) (62)
ILAC: An Automated Layout Tool for Analog CMOS Circuits (2002) (62)
Statistical modeling for the minimum standby supply voltage of a full SRAM array (2007) (59)
A methodology for rapid estimation of substrate-coupled switching noise (1995) (58)
Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits (2011) (56)
Substrate-aware mixed-signal macro-cell placement in WRIGHT (1994) (52)
WiCkeD: Analog Circuit Synthesis Incorporating Mismatch (2002) (52)
Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits (2009) (51)
Multiprocessor-Based Placement by Simulated Annealing (1986) (49)
ASF: a practical simulation-based methodology for the synthesis of custom analog circuits (2001) (49)
Substrate-aware mixed-signal macrocell placement in WRIGHT (1995) (47)
A Tutorial Introduction to Research on Analog and MixedSignal Circuit Testing (2002) (47)
Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting (2007) (45)
ASTRX/OBLX: Tools for Rapid Synthesis of High-Performance Analog Circuits (1994) (45)
A case study of synthesis for industrial-scale analog IP: redesign of the equalizer/filter frontend for an ADSL CODEC (2000) (45)
Time Domain Verification of Oscillator Circuit Properties (2006) (44)
A mixed-integer nonlinear programming approach to analog circuit synthesis (1992) (44)
FLOORPLANNING BY ANNEALING ON A HYPERCUBE MULTIPROCESSOR. (1987) (43)
Efficiently Enforcing Diversity in Multi-Output Structured Prediction (2014) (43)
Floating-point bit-width optimization for low-power signal processing applications (2002) (43)
Macromodeling of Integrated Circuit Operational Amplifiers (2002) (42)
ANACONDA: robust synthesis of analog circuits via stochastic pattern search (1999) (42)
Faster, Parametric Trajectory-based Macromodels Via Localized Linear Reductions (2006) (41)
Efficient handling of operating range and manufacturing linevariations in analog cell synthesis (2000) (41)
Floating-point error analysis based on affine arithmetic (2003) (40)
Layout tools for analog ICs and mixed-signal SoCs: a survey (2000) (39)
A new FPGA detailed routing approach via search-based Booleansatisfiability (2002) (38)
Performance-driven simultaneous placement and routing for FPGA's (1998) (38)
Wire packing: a strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution (2000) (38)
Optimal Design of a CMOS OpAmp via Geometric Programming (2002) (36)
Bayesian Virtual Probe: Minimizing variation characterization cost for nanoscale IC technologies via Bayesian inference (2010) (36)
Interval-Valued Reduced-Order Statistical Interconnect Modeling (2007) (36)
ACACIA: the CMU analog design system (1989) (35)
Lightweight Floating-Point Arithmetic: Case Study of Inverse Discrete Cosine Transform (2002) (35)
Synthesis of HighPerformance Analog Circuits in ASTRX/OBLX (2002) (35)
A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits (2004) (34)
Fast interval-valued statistical modeling of interconnect and effective capacitance (2006) (34)
Large-scale placement by grid-warping (2004) (33)
A multi-fpga 10x-real-time high-speed search engine for a 5000-word vocabulary speech recognizer (2009) (33)
Addressing noise decoupling in mixed-signal IC's: power distribution design and cell customization (1995) (32)
Design Automation for Analog: The Next Generation of Tool Challenges (2006) (32)
Static statistical timing analysis for latch-based pipeline designs (2004) (32)
Massively Parallel Switch-Level Simulation: A Feasibility Study (1989) (31)
An O(n) algorithm for transistor stacking with performance constraints (1996) (31)
Automatic clustering of wafer spatial signatures (2013) (31)
System-level routing of mixed-signal ASICs in WREN (1992) (31)
A Class of Cellular Architectures to Support Physical Design Automation (1984) (30)
ComputerAided Design of Analog and MixedSignal Integrated Circuits (2002) (30)
Practical Synthesis of High-Performance Analog Circuits (1998) (30)
Novel Algorithms for Fast Statistical Analysis of Scaled Circuits (2009) (30)
Multi-Wafer Virtual Probe: Minimum-cost variation characterization by exploring wafer-to-wafer correlation (2010) (29)
Interval-valued reduced order statistical interconnect modeling (2004) (28)
A Unified Formulation (1998) (28)
Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs (2010) (28)
Early research experience with OpenAccess gear: an open source development environment for physical design (2005) (27)
Pareto optimal modeling for efficient PLL optimization (2004) (26)
Analysis and design of low power digital multipliers (1999) (26)
Latchup-aware placement and parasitic-bounded routing of custom analog cells (1993) (25)
DELIGHT.SPICE: An OptimizationBased System for the Design of Integrated Circuits (2002) (25)
Techniques for simultaneous placement and routing of custom analog cells in KOAN/ANAGRAM II (1991) (25)
Moving speech recognition from software to silicon: the in silico vox project (2006) (24)
Analog circuit synthesis for performance in OASYS (1988) (24)
Extreme Statistics in Nanoscale Memory Design (2010) (24)
Hardware implementation of MRF map inference on an FPGA platform (2012) (24)
Video-Rate Stereo Matching Using Markov Random Field TRW-S Inference on a Hybrid CPU+FPGA Computing Platform (2013) (23)
Analog circuit synthesis for large, realistic cells: designing a pipelined A/D converter with ASTRX/OBLX (1994) (22)
A Prototype Framework for Knowledge-Based Analog Circuit Synthesis (1987) (22)
DARWIN: CMOS opamp Synthesis by means of a Genetic Algorithm (2002) (22)
Automation of IC Layout with Analog Constraints (2002) (22)
Analog circuit synthesis and exploration in OASYS (1988) (22)
Hardware Architecture of a Number Theoretic Transform for a Bootstrappable RNS-based Homomorphic Encryption Scheme (2020) (21)
Synthesis Of Manufacturable Analog Circuits (1994) (20)
Probabilistic interval-valued computation: toward a practical surrogate for statistics inside CAD tools (2006) (20)
STAIC: An Interactive Framework for Synthesizing CMOS and BiCMOS Analog Circuits (2002) (19)
Analog layout synthesis: what's missing? (2010) (19)
Cellular Image Processing Techniques for VLSI Circuit Layout Validation and Routing (1982) (19)
A New FPGA Detailed Routing Approach Via (2002) (19)
Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs (1996) (19)
Efficient Spatial Pattern Analysis for Variation Decomposition Via Robust Sparse Regression (2013) (19)
Timing-driven placement by grid-warping (2005) (19)
Performance-driven simultaneous place and route for island-style FPGAs (1995) (19)
Fast interval-valued statistical interconnect modeling and reduction (2005) (18)
Mask verification on the Connection Machine (1988) (18)
Knowledge Representation and Reasoning in a Software Synthesis Architecture (1992) (18)
LAYOUT BY ANNEALING IN A PARALLEL ENVIRONMENT. (1986) (17)
Techniques and Applications of Symbolic Analysis for Analog Integrated Circuits: A Tutorial Overview (2002) (16)
Stereophonic spectrogram segmentation using Markov random fields (2012) (16)
Error resilient MRF message passing architecture for stereo matching (2013) (15)
Power distribution synthesis for analog and mixed-signal ASICs in RAIL (1993) (15)
Logic Simulation On Massively Parallel Architectures (1989) (15)
Interactive AC Modeling and Characterization of Analog Circuits via Symbolic Analysis (2002) (15)
Toward efficient spatial variation decomposition via sparse regression (2011) (14)
Flowgraph Analysis of Large Electronic Networks (2002) (14)
Analog Circuit and Layout Synthesis Revisited (2015) (13)
Wire packing - a strong formulation of crosstalk-aware chip-leveltrack/layer assignment with an efficient integer programming solution (2001) (13)
Profiling large-vocabulary continuous speech recognition on embedded devices: a hardware resource sensitivity analysis (2009) (13)
Next-Generation Design and EDA Challenges: Small Physics, Big Systems, and Tall Tool-Chains (2007) (13)
Device-level early floorplanning algorithms for RF circuits (1998) (13)
Performance-Driven Simultaneous Place and Route for Row-Based FPGAs (1994) (13)
A low-power hardware search architecture for speech recognition (2008) (13)
Designer-driven topology optimization for pipelined analog to digital converters (2005) (12)
Anaconda: SimulationBased Synthesis of Analog Circuits Via Stochastic Pattern Search (2002) (12)
Direct transistor-level layout for digital blocks (2004) (12)
Probabilistic interval-valued computation: representing and reasoning about uncertainty in dsp and vlsi design (2005) (12)
A Boolean satisfiability-based incremental rerouting approach with application to FPGAs (2001) (12)
Systolic routing hardware: performance evaluation and optimization (1988) (12)
Knowledge-based synthesis of custom VLSI physical design tools; first steps (1988) (11)
New algorithms for placement and routing of custom analog cells in ACACIA (1990) (11)
A Scanline Data Structure Processor for VLSI Geometry Checking (1987) (11)
Panel: (When) Will FPGAs Kill ASICs? (2001) (11)
Position Statements (2009) (11)
The Generalized Boundary Curve A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits (2002) (11)
Mixed-signal noise-decoupling via simultaneous power distribution design and cell customization in RAIL (1994) (10)
Satisfiability-based detailed FPGA routing (1999) (10)
FlexGibbs: Reconfigurable Parallel Gibbs Sampling Accelerator for Structured Graphs (2019) (10)
A High-Rate, Low-Power, ASIC Speech Decoder Using Finite State Transducers (2012) (10)
FPGA-based Accelerators of Fully Pipelined Modular Multipliers for Homomorphic Encryption (2019) (10)
Circuit Analysis and Optimization Driven by WorstCase Distances (2002) (9)
OPASYN: A Compliler for CMOS Operational Amplifiers (2002) (9)
On the feasibility of synthesizing CAD software from specifications: generating maze router tools in ELF (1991) (9)
Fast hierarchical implementation of sequential tree-reweighted belief propagation for probabilistic inference (2015) (9)
Yield Optimization of Analog IC's Using TwoStep Analytic Modeling Methods (2002) (9)
FPGA Routing and Routability Estimation (1998) (8)
(When) will FPGAs kill ASICs? (2001) (8)
Exploiting Correlation Kernels for Ef£cient Handling of Intra-Die Spatial Correlation, with Application to Statistical Timing (2008) (8)
Inverse polarity techniques for high-speed/low-power multipliers (1999) (8)
In silico vox: Towards speech recognition in silicon (2006) (7)
Testability-oriented channel routing (1995) (7)
A Macromodeling Algorithm for Analog Circuits (2002) (7)
A case study of machine learning hardware: Real-time source separation using Markov Random Fields via sampling-based inference (2017) (7)
Accelerating Bayesian Inference on Structured Graphs Using Parallel Gibbs Sampling (2019) (7)
Error Resilient and Energy Efficient MRF Message-Passing-Based Stereo Matching (2016) (7)
IDAC: An Interactive Design Tool for Analog CMOS Circuits (2002) (7)
The first EDA MOOC: Teaching design automation to planet earth (2014) (7)
Design and performance evaluation of new massively parallel VLSI mask verification algorithms in JIGSAW (1990) (7)
Mixed-size placement with fixed macrocells using grid-warping (2007) (7)
(When) will FPGAs kill ASICs? (panel session) (2001) (6)
A 3mm2 Programmable Bayesian Inference Accelerator for Unsupervised Machine Perception using Parallel Gibbs Sampling in 16nm (2020) (6)
An Area-Efficient Iterative Single-Precision Floating-Point Multiplier Architecture for FPGA (2019) (5)
HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming (2022) (5)
WIRE ROUTING EXPERIMENTS ON A RASTER PIPELINE SUBARRAY MACHINE. (1983) (5)
Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search (2002) (5)
A hierarchical decomposition methodology for single-stage clock circuits (1997) (5)
A Class of Cellular Computer Architectures to Support Physical Design Automation (Vlsi Layout, Integrated Circuit, Routing) (1984) (5)
Real-Time and Low-Power Streaming Source Separation Using Markov Random Field (2018) (5)
Optimum CMOS Stack Generation with Analog Constraints (2002) (5)
A High-Performance Hardware Speech Recognition System for Mobile Applications (5)
Analog Cell-Level Synthesis using a Novel Problem Formulation (1993) (4)
Synthesis and layout for analog and mixed-signal ICs in the ACACIA system (1995) (4)
ELF: A Tool for Automatic Synthesis of Custom Physical CAD Software (1989) (4)
Integrated CAD, CAM and CAT of VLSI Circuits and Systems: The CMU Perspective (1985) (4)
Efficient Static Analysis of Fixed-Point Error in DSP Applications via Affine Arithmetic Modeling (2007) (4)
Will Moore's Law rule in the land of analog? (2004) (3)
Efficient area minimization for dynamic CMOS circuits (1996) (3)
Automatic Generation of Parasitic Constraints for PerformanceConstrained Physical Design of Analog Circuits (2002) (3)
Towards Formal Verification of Analog and Mixed-Signal Designs (2003) (3)
A parallel Steiner heuristic for wirelength estimation of large net populations (1991) (3)
On-the-Fly Fidelity Assessment for Trajectory-Based Circuit Macromodels (2006) (3)
Synthesis of analog and mixed-signal integrated electronic circuits (2001) (3)
Efficient Variation Decomposition via Robust Sparse Regression (2013) (3)
sub-SAT: a formulation for relaxed boolean satisfiability with applications in routing (2002) (3)
FPGA acceleration of Markov Random Field TRW-S inference for stereo matching (2013) (3)
Extreme Value Theory: Application to Memory Statistics (2010) (3)
A methodology for distributed simulation-based synthesis of custom analog circuits (2000) (3)
Integration and Electrical Isolation in CMOS MixedSignal Wireless Chips (2002) (3)
Advanced Routing Techniques for Nanometer IC Designs (2006) (3)
Metrics, Techniques and Recent Developments in MixedSignal Testing (2002) (3)
A hierarchical decomposition methodology for multistage clock circuits (1997) (3)
Low-power technology mapping for mixed-swing logic (2001) (3)
Studying the Potential of Automatic Optimizations in the Intel FPGA SDK for OpenCL (2020) (2)
Toward a pixel-parallel architecture for graph cuts inference on FPGA (2017) (2)
Life at the end of CMOS scaling (and beyond) (panel session) (abstract only) (2000) (2)
Interval-valued statistical modeling of oxide chemical-mechanical polishing (2005) (2)
A Scalable Bayesian Inference Accelerator for Unsupervised Learning (2020) (2)
DAC at 50: The Second 25 Years (2014) (2)
Generating small, accurate acoustic models with a modified Bayesian information criterion (2007) (2)
DATA STRUCTURE PROCESSOR FOR VLSI GEOMETRY CHECKING. (1986) (2)
Consistency Checking and Optimization of Macromodels (2002) (2)
Algorithmic approach to design and optimization of vlsi interconnect (1999) (2)
EMERALD: Characterization of emerging applications and algorithms for low-power devices (2013) (2)
A robust message passing based stereo matching kernel via system-level error resiliency (2014) (2)
Accelerator Design with Effective Resource Utilization for Binary Convolutional Neural Networks on an FPGA (2018) (1)
Simulation of Mixed SwitchedCapacitor/Digital Networks with SignalDriven Switches (2002) (1)
Analysis of error resiliency of belief propagation in computer vision (2016) (1)
Spatial variation decomposition via sparse regression (2012) (1)
Case study of a VLSI design project: A simple inner product machine (1981) (1)
SubstrateAware MixedSignal Macrocell Placement in WRIGHT (2002) (1)
Configurable and scalable belief propagation accelerator for computer vision (2016) (1)
Statistical Blockade: Estimating Rare Event Statistics (2009) (1)
Simulation Methods for RF Integrated Circuits (2002) (1)
Case studies: Chip design on the bleeding edge (panel session abstract). (2000) (1)
Structured Simulation-Based Analog Design Synthesis (2002) (1)
Future Directions for DA Machine Research (1985) (1)
Design Automation: Even When It's Old It's New (1989) (1)
A Statistical OptimizationBased Approach for Automated Sizing of Analog Cells (2002) (1)
The Selection Stage (1990) (1)
Mixed signals on mixed-signal: the right next technology (2003) (1)
Collaborative VLSI-CAD Instruction in the Digital Sandbox (2007) (1)
Session details: Panel (2008) (0)
Session details: Mixed signals on mixed-signal: the right next technology (2003) (0)
Session details: Session 3: From the Trenches (invited) (2003) (0)
Efficient Approximation of Symbolic Network Functions Using Matroid Intersection Algorithms (2002) (0)
Analog Modeling and Analysis (2002) (0)
Quasi-Monte Carlo for Fast Statistical Simulation of Circuits (2009) (0)
Session details: Interconnect synthesis and structured ASIC (2008) (0)
A Circuit Compiler (1998) (0)
ComputerAided Design Considerations for MixedSignal Coupling in RF Integrated Circuits (2002) (0)
Specialized Analog Simulation (2002) (0)
Layout Tools for Analog Integrated Circuits and Mixed-Signal Systems-on-Chip: A Survey (2018) (0)
Design of MixedSignal SystemsonaChip (2002) (0)
CAD & Methodology for Design of Cell-Level Analog Building Blocks (2000) (0)
Survival strategies for mixed-signal systems-on-chip (panel session) (2000) (0)
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996 (1996) (0)
Expanding the realm of physical design (panel session) (2001) (0)
Statistical Integrated Circuit Design (2002) (0)
Geometry Sharing Placement (1994) (0)
Simulating and Testing Oversampled AnalogtoDigital Converters (2002) (0)
Session details: Will Moore's law rule in the land of analog? (2004) (0)
Mobile Speech Hardware: The Case for Custom Silicon (2012) (0)
Synthesis for industrial-scale analog intellectual property (2001) (0)
The design and implementation of a large-scale placer based on grid-warping (2006) (0)
Efficient Process Variation Characterization by Virtual Probe (2019) (0)
An interval-valued computation methodology for statistical retrofitting of existing circuit and technology cad tools (2006) (0)
Future directions for DA machine research (panel session) (1985) (0)
Analog Centering and Yield Optimization (2002) (0)
DC, AC, and Transient Electrical Models and Analysis (1996) (0)
Solving the Infinite Program (1998) (0)
Oil fields, hedge funds, and drugs (2009) (0)
Case studies (panel session) (abstract only): Chip design on the bleeding edge (2000) (0)
Nominal Circuit Synthesis Results (1998) (0)
Synthesis Via Annealing (1998) (0)
Statistical Blockade: Estimating Rare Event Statistics for Memories (2009) (0)
Additional Koan/Anagram II Results (1994) (0)
Session details: Session 11A: Panel: automatic hierarchical design: fantasy or reality? (2001) (0)
ELF: A Program Synthesis Architecture (1990) (0)
Application Domain: Routing Algorithms (1990) (0)
Zen and the Art of Analog Design Automation (1989) (0)
INNER PRODUCT INTEGRATED CIRCUIT. (1984) (0)
Verifying Really Complex Systems: On earth and beyond (2008) (0)
D&T Research (1985) (0)
The Code Generator Stage (1990) (0)
VHDLAMSA Hardware Description Language for Analog and MixedSignal Applications (2002) (0)
Panel: nanometer design: what hurts next....? (2002) (0)
Automatic Hierarchical Design: Fantasy or Reality? (Panel) (2001) (0)
VLSI Design 2008 Best Paper Awards (2008) (0)
Line-Expansion Routing (1994) (0)
Power Distribution Noise and Physical Design Methods (1996) (0)
A New Nominal Synthesis Strategy (1998) (0)
Design Centering by Yield Prediction (2002) (0)
Systemlevel Routing of MixedSignal ASICs in WREN (2002) (0)
A Pixel-Parallel Virtual-Image Architecture for High Performance and Power Efficient Graph Cuts Inference (2019) (0)
PerformanceDriven Compaction for Analog Integrated Circuits (2002) (0)
Introduction to Analog CAD (2002) (0)
Crosstalk Avoidance Routing (1994) (0)
Validating the Tool Design (1998) (0)
Variation-Tolerant Synthesis Results (1998) (0)
Methods for Nominal Analog Circuit Synthesis (1998) (0)
Keynote address Wednesday: Hardware inference accelerators for machine learning (2016) (0)
Layout Tools for Analog Integrated Circuits and Mixed-Signal Systems-on-Chip (2016) (0)
Minimizing Floating Point Power by Optimizing Operand Range and Precision (1999) (0)
The Input Stage (1990) (0)
Physical Design and Optimization (1996) (0)
Highlights in Analog and Digital Circuit Design and Synthesis at ICCAD (2003) (0)
Session details: Session 1D: Analog macromodeling (2001) (0)
Session details: Design Above the Silicon Surface (2002) (0)
The Second Challenge: Handling Variations (1998) (0)
A Virtual Image Accelerator for Graph Cuts Inference on FPGA (2019) (0)

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