Robert Bogdan Staszewski
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Researcher, ORCID id # 0000-0001-9848-1129
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Robert Bogdan Staszewskiengineering Degrees
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Electrical Engineering
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Engineering
Robert Bogdan Staszewski's Degrees
- PhD Electrical Engineering Stanford University
- Masters Electrical Engineering Stanford University
- Bachelors Electrical Engineering Stanford University
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(Suggest an Edit or Addition)Robert Bogdan Staszewski's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- All-digital PLL and transmitter for mobile phones (2005) (629)
- All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS (2004) (592)
- 1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS (2006) (343)
- All-digital frequency synthesizer in deep-submicron CMOS (2006) (307)
- Cryo-CMOS Circuits and Systems for Quantum Computing Applications (2018) (212)
- Phase-domain all-digital phase-locked loop (2005) (203)
- Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process (2003) (189)
- A first multigigahertz digitally controlled oscillator for wireless applications (2003) (160)
- A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones (2005) (143)
- A Class-F CMOS Oscillator (2013) (140)
- A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS (2014) (139)
- Event-driven Simulation and modeling of phase noise of an RF oscillator (2005) (133)
- A discrete-time Bluetooth receiver in a 0.13/spl mu/m digital CMOS process (2004) (121)
- A discrete-time Bluetooth receiver in a 0.13/spl mu/m digital CMOS process (2004) (121)
- The First Fully Integrated Quad-Band GSM/GPRS Receiver in a 90-nm Digital CMOS Process (2006) (119)
- All-Digital PLL With Ultra Fast Settling (2007) (117)
- 9.8 An 860μW 2.1-to-2.7GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth Smart and ZigBee) applications (2014) (117)
- All-digital phase-domain TX frequency synthesizer for Bluetooth radios in 0.13/spl mu/m CMOS (2004) (113)
- Digital RF processing: toward low-cost reconfigurable radios (2005) (111)
- Direct RF sampling mixer with recursive filtering in charge domain (2004) (99)
- A 1/f Noise Upconversion Reduction Technique for Voltage-Biased RF CMOS Oscillators (2016) (96)
- A digital-to-RF-amplitude converter for GSM/GPRS/EDGE in 90-nm digital CMOS (2005) (91)
- A digitally controlled oscillator system for SAW-less transmitters in cellular handsets (2006) (82)
- A 60 GHz Frequency Generator Based on a 20 GHz Oscillator and an Implicit Multiplier (2016) (80)
- TDC-based frequency synthesizer for wireless applications (2004) (79)
- A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network (2017) (75)
- State-of-the-Art and Future Directions of High-Performance All-Digital Frequency Synthesis in Nanometer CMOS (2011) (74)
- A Wideband 2$\times$ 13-bit All-Digital I/Q RF-DAC (2014) (72)
- An Ultra-Low Phase Noise Class-F 2 CMOS Oscillator With 191 dBc/Hz FoM and Long-Term Reliability (2015) (71)
- High-Resolution Millimeter-Wave Digitally Controlled Oscillators With Reconfigurable Passive Resonators (2013) (69)
- Spur-Free Multirate All-Digital PLL for Mobile Phones in 65 nm CMOS (2011) (69)
- A 24mm2 Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS (2008) (65)
- A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm (2016) (65)
- RF Built-in Self Test of a Wireless Transmitter (2007) (61)
- Analysis and Design of a High-Order Discrete-Time Passive IIR Low-Pass Filter (2014) (61)
- Analysis and Design of a Multi-Core Oscillator for Ultra-Low Phase Noise (2016) (59)
- A Low-Flicker-Noise 30-GHz Class-F23 Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path (2018) (57)
- LMS-based calibration of an RF digitally controlled oscillator for mobile phones (2006) (54)
- A discrete time quad-band GSM/GPRS receiver in a 90nm digital CMOS process (2005) (52)
- Just-in-time gain estimation of an RF digitally-controlled oscillator for digital direct frequency modulation (2003) (51)
- Multi-Mode/Multi-Band RF Transceivers for Wireless Communications: Advanced Techniques, Architectures, and Trends (2009) (51)
- A 33-GHz LNA for 5G Wireless Systems in 28-nm Bulk CMOS (2018) (51)
- A Technique to Reduce Phase/Frequency Modulation Bandwidth in a Polar RF Transmitter (2010) (48)
- A 0.8mm2 all-digital SAW-less polar transmitter in 65nm EDGE SoC (2010) (47)
- A 160 MHz analog equalizer for magnetic disk read channels (1997) (47)
- 15.5 Cryo-CMOS circuits and systems for scalable quantum computing (2017) (44)
- Time-Domain Modeling of an RF All-Digital PLL (2008) (43)
- A 550-MSample/s 8-Tap FIR digital filter for magnetic recording read channels (2000) (42)
- Digital Deep-Submicron CMOS Frequency Synthesis for RF Wireless Appllications (2002) (41)
- 3.8 A fully integrated highly reconfigurable discrete-time superheterodyne receiver (2014) (41)
- Breaking the Bandwidth Limit: A Review of Broadband Doherty Power Amplifier Design for 5G (2019) (40)
- Tunable Bandpass Filter With Two Adjustable Transmission Poles and Compensable Coupling (2014) (40)
- A 3.5–6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH $\Delta \Sigma $ -TDC for Low In-Band Phase Noise (2017) (39)
- 25.4 A 1/f noise upconversion reduction technique applied to Class-D and Class-F oscillators (2015) (39)
- Time-to-digital converter for RF frequency synthesis in 90 nm CMOS (2005) (39)
- A 56.4-to-63.4GHz spurious-free all-digital fractional-N PLL in 65nm CMOS (2013) (38)
- Energy-Efficient Wide-Range Voltage Level Shifters Reaching 4.2 fJ/Transition (2018) (37)
- Software Assisted Digital RF Processor (DRP™) for Single-Chip GSM Radio in 90 nm CMOS (2010) (36)
- A Phase Domain Approach for Mitigation of Self-Interference in Wireless Transceivers (2009) (36)
- Charge-Domain Signal Processing of Direct RF Sampling Mixer with Discrete-Time Filters in Bluetooth and GSM Receivers (2006) (35)
- An Ultra-Low Power 1.7-2.7 GHz Fractional-N Sub-Sampling Digital Frequency Synthesizer and Modulator for IoT Applications in 40 nm CMOS (2017) (34)
- All-Digital RF $I/Q$ Modulator (2012) (34)
- Challenges in On-Chip Antenna Design and Integration With RF Receiver Front-End Circuitry in Nanoscale CMOS for 5G Communication Systems (2019) (33)
- A Low-Noise Fractional- ${N}$ Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications (2019) (33)
- An Efficient Linearization Scheme for a Digital Polar EDGE Transmitter (2010) (32)
- A 12mW all-digital PLL based on class-F DCO for 4G phones in 28nm CMOS (2014) (32)
- Direct frequency modulation of an ADPLL for bluetooth/GSM with injection pulling elimination (2005) (32)
- A Novel Approach for Mitigation of RF Oscillator Pulling in a Polar Transmitter (2011) (31)
- 3 V 20 ps Time-to-Digital Converter for Frequency Synthesis in 90-nm CMOS (2006) (31)
- 14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S (2015) (31)
- A High IIP2 SAW-Less Superheterodyne Receiver With Multistage Harmonic Rejection (2016) (31)
- A Mixed-Signal Control Core for a Fully Integrated Semiconductor Quantum Computer System-on-Chip (2019) (31)
- A 3.5–6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise (2016) (31)
- An Amplitude Resolution Improvement of an RF-DAC Employing Pulsewidth Modulation (2011) (30)
- A clip-and-restore technique for phase desensitization in a 1.2V 65nm CMOS oscillator for cellular mobile and base stations (2012) (30)
- A 5.9 GHz RFDAC-based outphasing power amplifier in 40-nm CMOS with 49.2% efficiency and 22.2 dBm power (2016) (29)
- Built-in Self Testing of a DRP-Based GSM Transmitter (2007) (26)
- Digitally intensive wireless transceivers (2012) (26)
- Spur-free all-digital PLL in 65nm for mobile phones (2011) (26)
- 24.1 A 770pJ/b 0.85V 0.3mm2 DCO-based phase-tracking RX featuring direct demodulation and data-aided carrier tracking for IoT applications (2017) (26)
- Recombination of Envelope and Phase Paths in Wideband Polar Transmitters (2010) (26)
- The (R)evolution of Distributed Amplifiers: From Vacuum Tubes to Modern CMOS and GaN ICs (2018) (26)
- Noise Analysis of Time-to-Digital Converter in All-Digital PLLs (2006) (25)
- A low-power all-digital PLL architecture based on phase prediction (2012) (25)
- Speed, power, area, and latency tradeoffs in adaptive FIR filtering for PRML read channels (2001) (24)
- A 0.27mm2 13.5dBm 2.4GHz all-digital polar transmitter using 34%-efficiency Class-D DPA in 40nm CMOS (2013) (24)
- A 2mW 800MS/s 7th-order discrete-time IIR filter with 400kHz-to-30MHz BW and 100dB stop-band rejection in 65nm CMOS (2013) (23)
- A wideband 60 GHz class-E/F2 power amplifier in 40nm CMOS (2015) (23)
- Modeling of Semiconductor Electrostatic Qubits Realized Through Coupled Quantum Dots (2019) (23)
- Cost-Efficient, High-Volume Transmission: Advanced Transmission Design and Architecture of Next Generation RF Modems and Front-Ends (2015) (23)
- A study of RF oscillator reliability in nanoscale CMOS (2013) (22)
- Third-harmonic injection technique applied to a 5.87-to-7.56GHz 65nm CMOS Class-F oscillator with 192dBc/Hz FOM (2013) (22)
- A Wideband 2 13-bit All-Digital I/Q RF-DAC (22)
- A 2×13-bit all-digital I/Q RF-DAC in 65-nm CMOS (2013) (22)
- A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE With PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOS (2018) (21)
- Tuning Range Extension of a Transformer-Based Oscillator Through Common-Mode Colpitts Resonance (2017) (21)
- A Fully Integrated Discrete-Time Superheterodyne Receiver (2017) (20)
- Quantization noise improvement of Time to Digital converter (TDC) for ADPLL (2009) (20)
- A 2-GHz digital I/Q modulator in 65-nm CMOS (2011) (20)
- A 2.4GHz class-D power amplifier with conduction angle calibration for −50dBc harmonic emissions (2014) (20)
- High-resolution 60-GHz DCOs with reconfigurable distributed metal capacitors in passive resonators (2012) (20)
- A sigma-delta ADC with a built-in anti-aliasing filter for Bluetooth receiver in 130nm digital process (2004) (20)
- Spurious free time-to-digital conversion in an ADPLL using short dithering sequences (2010) (20)
- All-Digital PLL for Bluetooth Low Energy Using 32.768-kHz Reference Clock and ≤0.45-V Supply (2018) (20)
- Analog Path for Triple Band WCDMA Polar Modulated Transmitter in 90nm CMOS (2007) (19)
- Bandwidth Enhancement of GaN MMIC Doherty Power Amplifiers Using Broadband Transformer-Based Load Modulation Network (2019) (19)
- A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter (2016) (19)
- Joint common mode voltage and differential offset voltage control scheme in a low-IF receiver (2004) (19)
- Spurious-Free Time-to-Digital Conversion in an ADPLL Using Short Dithering Sequences (2011) (18)
- A 0.2-V 30-MS/s 11b-ENOB Open-Loop VCO-Based ADC in 28-nm CMOS (2018) (18)
- From two types of electrostatic position-dependent semiconductor qubits to quantum universal gates and hybrid semiconductor-superconducting quantum computer (2019) (17)
- Curse of digital polar transmission: Precise delay alignment in amplitude and phase modulation paths (2008) (17)
- Software Assisted Digital RF Processor for Single-Chip GSM Radio in 90 nm CMOS (2006) (17)
- Accurate self-characterization of mismatches in a capacitor array of a digitally-controlled oscillator (2010) (17)
- Design of Highly Linear Broadband Continuous Mode GaN MMIC Power Amplifiers for 5G (2019) (17)
- Analysis and Design of I/Q Charge-Sharing Band-Pass-Filter for Superheterodyne Receivers (2015) (17)
- Design and Analysis of a DCO-Based Phase-Tracking RF Receiver for IoT Applications (2019) (16)
- 19.6 A 0.2V trifilar-coil DCO with DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution, and frequency pushing of 38MHz/V for energy harvesting applications (2017) (16)
- A mm-Wave FMCW radar transmitter based on a multirate ADPLL (2013) (16)
- A first RF digitally-controlled oscillator for mobile phones (2005) (16)
- CMOS Position-Based Charge Qubits: Theoretical Analysis of Control and Entanglement (2019) (16)
- A 0.5V 0.5mW switching current source oscillator (2015) (16)
- A 0.02–4.5-GHz LN(T)A in 28-nm CMOS for 5G Exploiting Noise Reduction and Current Reuse (2020) (16)
- Elimination of spurious noise due to time-to-digital converter (2009) (15)
- All-Digital PLL with Ultra Fast Acquisition (2005) (15)
- A digital ultra-fast acquisition linear frequency modulated PLL for mm-wave FMCW radars (2009) (15)
- A 65nm CMOS high-IF superheterodyne receiver with a High-Q complex BPF (2013) (15)
- An Ultracompact 9.4–14.8-GHz Transformer-Based Fractional-N All-Digital PLL in 40-nm CMOS (2017) (15)
- An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with −55 dBc Fractional and −91 dBc Reference Spurs (2018) (15)
- A 1 V Bandgap Reference in 7-nm FinFET with a Programmable Temperature Coefficient and an Inaccuracy of ±0.2% from −45°C to 125°C (2018) (15)
- SoC with an integrated DSP and a 2.4-GHz RF transmitter (2005) (15)
- Orthogonal summing and power combining network in a 65-nm all-digital RF I/Q modulator (2011) (14)
- A first RF digitally-controlled oscillator for SAW-less TX in cellular systems (2005) (14)
- Verification of Digital RF Processors: RF, Analog, Baseband, and Software (2007) (14)
- An all-digital offset PLL architecture (2010) (13)
- A 60 GHz 25% tuning range frequency generator with implicit divider based on third harmonic extraction with 182 dBc/Hz FoM (2015) (13)
- Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased Oscillators (2019) (13)
- A 0.36-V 5-MS/s Time-Mode Flash ADC With Dickson-Charge-Pump-Based Comparators in 28-nm CMOS (2020) (13)
- Quad Band Digitally Controlled Oscillator for WCDMA Transmitter in 90nm CMOS (2006) (13)
- A highly selective LNTA capable of large-signal handling for RF receiver front-ends (2013) (13)
- A Time-Domain Resolution Improvement of an RF-DAC (2010) (13)
- Digital RF Processor Techniques for Single-Chip Radios (2006) (13)
- A Digitally Controlled Injection-Locked Oscillator With Fine Frequency Resolution (2016) (13)
- A 0.5V 1.6mW 2.4GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28nm CMOS (2017) (12)
- DiscreteTime Processing of RF Signals (2011) (12)
- Digital I/Q RF transmitter using time-division duplexing (2011) (12)
- 30.8 A 3.5mm×3.8mm Crystal-Less MICS Transceiver Featuring Coverages of ±160ppm Carrier Frequency Offset and 4.8-VSWR Antenna Impedance for Insertable Smart Pills (2020) (12)
- A 103fsrms 1.32mW 50MS/s 1.25MHz bandwidth two-step flash-ΔΣ time-to-digital converter for ADPLL (2015) (12)
- Design and built-in characterization of digital-to-time converters for ultra-low power ADPLLs (2015) (12)
- System Design of a 2.75-mW Discrete-Time Superheterodyne Receiver for Bluetooth Low Energy (2017) (12)
- Time-to-digital converter (TDC) for WiMAX ADPLL in 40-nm CMOS (2011) (12)
- Gain Estimation of a Digital-to-Time Converter for Phase-Prediction All-Digital PLL (2013) (11)
- Built-In Measurements in Low-Cost Digital-RF Transceivers (2011) (11)
- Verification of RF SoCs: RF, analog, baseband and software (2006) (11)
- Towards quantum internet and non-local communication in position-based qubits (2019) (11)
- A 1-V Bandgap Reference in 7-nm FinFET With a Programmable Temperature Coefficient and Inaccuracy of ±0.2% From −45°C to 125°C (2019) (11)
- A Single-Electron Injection Device for CMOS Charge Qubits Implemented in 22-nm FD-SOI (2020) (11)
- A 38 GHz on-chip antenna in 28-nm CMOS using artificial magnetic conductor for 5G wireless systems (2016) (10)
- A Low Phase Noise Oscillator Principled on Transformer-Coupled Hard Limiting (2014) (10)
- Broadband Fully Integrated GaN Power Amplifier With Minimum-Inductance BPF Matching and Two-Transistor AM-PM Compensation (2020) (10)
- On the Reconfigurability of All-Digital Phase-Locked Loops for Software Defined Radios (2007) (10)
- Analytical solutions for N interacting electron system confined in graph of coupled electrostatic semiconductor and superconducting quantum dots in tight-binding model (2019) (10)
- A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS (2015) (10)
- A 30-GHz class-F23 oscillator in 28nm CMOS using harmonic extraction and achieving 120 kHz 1/f3 corner (2017) (10)
- Digital RF Processing Techniques for Device Mismatch Tolerant Transmitters in Nanometer-Scale CMOS (2007) (10)
- 17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and −250dB FoM (2020) (10)
- A Type-II Phase-Tracking Receiver (2020) (9)
- A 184.6-dBc/Hz FoM 100-kHz Flicker Phase Noise Corner 30-GHz Rotary Traveling-Wave Oscillator Using Distributed Stubs in 22-nm FD-SOI (2019) (9)
- Ultra-low phase noise 7.2–8.7 Ghz clip-and-restore oscillator with 191 dBc/Hz FoM (2013) (9)
- A Fully Integrated DAC for CMOS Position-Based Charge Qubits with Single-Electron Detector Loopback Testing (2020) (9)
- A TDD/FDD SAW-less superheterodyne receiver with blocker-resilient band-pass filter and multi-stage HR in 28nm CMOS (2015) (9)
- Design of ADPLL system for WiMAX applications in 40-nm CMOS (2012) (9)
- Digital RF Processor (DRP™) for Cellular Radios (2005) (9)
- A Fully Integrated GaN Dual-Channel Power Amplifier With Crosstalk Suppression for 5G Massive MIMO Transmitters (2020) (9)
- Ultra-high data-rate wireless transfer in a saturated spectrum — new paradigms (2014) (9)
- An Event-Driven Quasi-Level-Crossing Delta Modulator Based on Residue Quantization (2020) (9)
- Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF Applications (2007) (9)
- Built-in self testing (BIST) of RF performance in a system-on-chip (SoC) (2005) (9)
- Sigma-delta noise shaping for digital-to-frequency and digital-to-RF-amplitude conversion (2005) (8)
- A Tiny Quadrature Oscillator Using Low-Q Series LC Tanks (2015) (8)
- Toward Solving Multichannel RF-SoC Integration Issues Through Digital Fractional Division (2016) (8)
- Digital RF Processor (DRP) for Mobile Phones (2007) (8)
- Oscillator Flicker Phase Noise: A Tutorial (2020) (8)
- An EDGE transmitter with mitigation of oscillator pulling (2010) (8)
- A Supply Pushing Reduction Technique for LC Oscillators Based on Ripple Replication and Cancellation (2019) (8)
- A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS (2017) (8)
- RF Impairment Compensation for Future Radio Systems (2011) (7)
- Top-down simulation methodology of a 500 MHz mixed-signal magnetic recording read channel using stan (1999) (7)
- A statistical approach for design and testing of analog circuitry in low-cost SoCs (2010) (7)
- A Mismatch Calibration Technique for SAR ADCs Based on Deterministic Self-Calibration and Stochastic Quantization (2020) (7)
- A fully integrated 28nm Bluetooth Low-Energy transmitter with 36% system efficiency at 3dBm (2015) (7)
- Digitally controlled oscillator in a 65nm GSM/EDGE transceiver with built-in compensation for capacitor mismatches (2011) (7)
- A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC (2022) (7)
- Digital Signal Processing for RF at 45-nm CMOS and Beyond (2006) (7)
- A 20 MHz–2 GHz Inductorless Two-Fold Noise-Canceling Low-Noise Amplifier in 28-nm CMOS (2021) (7)
- A Built-in Tester for Modulation Noise in a Wireless Transmitter (2006) (7)
- A Time-Domain 147fsrms 2.5-MHz Bandwidth Two-Step Flash-MASH 1-1-1 Time-to-Digital Converter With Third-Order Noise-Shaping and Mismatch Correction (2020) (7)
- Characterization and Modeling of Multiple Coupled Inductors Based on On-Chip Four-Port Measurement (2014) (7)
- Occupancy Oscillations and Electron Transfer in Multiple-Quantum-Dot Qubits and their Circuit Representation (2018) (7)
- A 350-mV 2.4-GHz quadrature oscillator with nearly instantaneous start-up using series LC tanks (2017) (7)
- Unbalanced Power Amplifier: An Architecture for Broadband Back-Off Efficiency Enhancement (2020) (7)
- Event-driven simulation and modeling of an RF oscillator (2004) (7)
- Characterization of deep-submicron varactor mismatches in a digitally controlled oscillator (2005) (7)
- A Single-Pin Antenna Interface RF Front End Using a Single-MOS DCO-PA and a Push–Pull LNA (2020) (7)
- Digital RF and digitally-assisted RF (invited) (2011) (7)
- Design of Spur-Free ΣΔ Frequency Tuning Interface for Digitally Controlled Oscillators (2015) (7)
- A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS (2021) (6)
- Broadband Fully Integrated GaN Power Amplifier With Embedded Minimum Inductor Bandpass Filter and AM–PM Compensation (2019) (6)
- BJT Device and Circuit Co-Optimization Enabling Bandgap Reference and Temperature Sensing in 7-nm FinFET (2018) (6)
- Implementation and Experimental Results (2005) (6)
- Tuning Word Retiming of a Digitally-Controlled Oscillator Using RF Built-In Self Test (2006) (6)
- A Practical Step Forward Toward Software-Defined Radio Transmitters (2007) (6)
- Photon Enhanced Interaction and Entanglement in Semiconductor Position-Based Qubits (2019) (6)
- Top-Down Simulation Methodology of a Mixed-Signal Read Channel Using Standard VHDL (2007) (6)
- Implementation of a high speed digital band-pass sigma-delta modulator for a wireless transmitter (2005) (6)
- Fine frequency tuning using injection-control in a 1.2V 65nm CMOS quadrature oscillator (2012) (6)
- Synchronization-Phase Alignment of All-Digital Phase-Locked Loop Chips for a 60-GHz MIMO Transmitter and Evaluation of Phase Noise Effects (2019) (6)
- High-speed digital circuits for a 2.4 GHz all-digital RF frequency synthesizer in 130 nm CMOS (2004) (6)
- Cryo-CMOS for Quantum System On-Chip Integration: Quantum Computing as the Development Driver (2021) (6)
- A 0.3V, 35% Tuning-Range, 60kHz 1/f3-Corner Digitally Controlled Oscillator with Vertically Integrated Switched Capacitor Banks Achieving FoMT of -199dB in 28-nm CMOS (2019) (6)
- Design of Spur-Free $\Sigma\Delta$ Frequency Tuning Interface for Digitally Controlled Oscillators (2015) (6)
- Semiconductor Quantum Computing: Toward a CMOS quantum computer on chip (2021) (6)
- A Tiny Complementary Oscillator With 1/f3 Noise Reduction Using a Triple-8-Shaped Transformer (2020) (6)
- A Fully Integrated 28 nm Bluetooth Low-Energy Transmitter with 36 % System Efficiency at 3 dBm (2017) (5)
- All-Digital RF Modulator (2012) (5)
- A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking (2021) (5)
- An impedance sensor for MEMS adaptive antenna matching (2015) (5)
- Digitally Controlled Oscillator (2005) (5)
- An Adaptive-Resolution Quasi-Level-Crossing-Sampling ADC Based on Residue Quantization in 28-nm CMOS (2018) (5)
- A low cost-low loss broadband integration of a CMOS transmitter and its antenna for mm-wave FMCW radar applications (2018) (5)
- Low power time-of-flight 3D imager system in standard CMOS (2012) (5)
- A mm-Wave Switched-Capacitor RFDAC (2022) (5)
- Dickson-Charge-Pump-Based Voltage-to-Time Conversion for Time-Based ADCs in 28-nm CMOS (2021) (5)
- Fully-integrated CMOS RF transceivers (2006) (5)
- A constrained asymmetry LMS algorithm for PRML disk drive read channels (2000) (5)
- Frequency translation through fractional division for a two-channel pulling mitigation (2013) (5)
- VHDL simulation and modeling of an all-digital RF transmitter (2005) (5)
- A 0 . 2 GHz to 4 GHz Hybrid PLL ( ADPLL / Charge-Pump-PLL ) in 7 nm FinFET CMOS Featuring 0 . 619 ps Integrated Jitter and 0 . 6 us Settling Time at 2 . 3 mW (2018) (4)
- A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference (2018) (4)
- A 2.02–2.87-GHz −249-dB FoM 1.1-mW Digital PLL Exploiting Reference-Sampling Phase Detector (2020) (4)
- Time-domain behavioral modeling of a multigigahertz digital RF oscillator using VHDL (2005) (4)
- CMOS charge qubits and qudits: entanglement entropy and mutual information as an optimization method to construct CNOT and SWAP Gates (2021) (4)
- Simulation Methodology for Electron Transfer in CMOS Quantum Dots (2020) (4)
- A 180 mV 81.2%-Efficient Switched-Capacitor Voltage Doubler for IoT Using Self-Biasing Deep N-Well in 16-nm CMOS FinFET (2018) (4)
- Digital RF Processor (DRP TM ) for Cellular Phones (2005) (4)
- Monolithic Integration of Quantum Resonant Tunneling Gate on a 22nm FD-SOI CMOS Process (2021) (4)
- Position-Based CMOS Charge Qubits for Scalable Quantum Processors at 4K (2020) (4)
- Effects of Subharmonics in LO Generation on RF Transceivers (2018) (4)
- A 32–42-GHz RTWO-Based Frequency Quadrupler Achieving >37 dBc Harmonic Rejection in 22-nm FD-SOI (2021) (4)
- A 0.2-V Three-Winding Transformer-Based DCO in 16-nm FinFET CMOS (2020) (4)
- An Adaptive-Resolution Quasi-Level-Crossing Delta Modulator With VCO-Based Residue Quantizer (2020) (4)
- Injection Spurs due to Reference Frequency Retiming by a Channel Dependent Clock at the ADPLL RF Output and its Mitigation (2007) (4)
- A Hybrid-PLL (ADPLL/Charge-Pump PLL) Using Phase Realignment With 0.6-us Settling, 0.619-ps Integrated Jitter, and −240.5-dB FoM in 7-nm FinFET (2020) (4)
- A Broadband Fully Integrated Power Amplifier Using Waveform Shaping Multi-Resonance Harmonic Matching Network (2021) (4)
- A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW (2018) (3)
- Numerical Model of an Injection-Locked Wideband Frequency Modulator for Polar Transmitters (2017) (3)
- Interpolative pulse-shape filtering for a GSM/Bluetooth transmitter (2005) (3)
- Interpolative pulse-shape filtering for a GSM/Bluetooth transmitter (2005) (3)
- Digital RF Processor (DRP (2007) (3)
- DSP-coupled 2.4 GHz RF transmitter in 130 nm CMOS (2004) (3)
- Implementation and Simulation of Electrostatically Controlled Quantum Dots in CMOS Technology (2019) (3)
- A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8–19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS (2016) (3)
- Design Considerations of the Interpolative Digital Transmitter for Quantization Noise and Replicas Rejection (2020) (3)
- Envelope and phase path recombination in ADPLL-based wideband polar transmitters (2008) (3)
- Design procedure of a U-slot patch antenna array for 60 GHz MIMO application (2018) (3)
- 1.3V 20p Time-to-Digital Converter for Frequency Synthesis in 90-nm CMOS (2006) (3)
- filter for Bluetooth receiver in 13Onm digital process (2004) (3)
- A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL (2021) (3)
- Design for test of a mm-Wave ADPLL-based transmitter (2014) (3)
- A 38.6-fJ/Conv.-Step Inverter-Based Continuous-Time Bandpass ΔΣ ADC in 28 nm Using Asynchronous SAR Quantizer (2021) (3)
- Digital RF architectures for wireless transceivers (invited) (2011) (3)
- A 184.6-dBc/Hz FoM 100-kHz Flicker Phase Noise Corner 30-GHz Rotary Traveling-Wave Oscillator Using Distributed Stubs in 22-nm FD-SOI (2019) (3)
- Mismatch considerations in an RF-DAC design for a digital polar EDGE transmitter (2011) (3)
- Analog, Mixed-Signal, and RF Circuit Design in Nanometer CMOS (2007) (3)
- Digital RF and Digitally-Assisted RF (2011) (3)
- A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs (2022) (3)
- Just-in-time gain estimation of an RF digitally-controlled oscillator (2003) (3)
- Harmonic characterization of mismatches in deep sub-micron varactors for a digitally controlled RF oscillator (2005) (3)
- Frequency-domain adaptive-resolution level-crossing-sampling ADC (2017) (3)
- Active mitigation of induced phase distortion in a GSM SoC (2008) (3)
- A 0.7-V Sub-mW Type-II Phase-Tracking Bluetooth Low Energy Receiver in 28-nm CMOS (2021) (3)
- A 2.4-GHz Single-Pin Antenna Interface RF Front-End with a Function-Reuse Single-MOS VCO-PA and a Push-Pull LNA (2018) (3)
- MILLIMETER-WAVE DIGITALLY INTENSIVE FREQUENCY GENERATION IN CMOS (2017) (2)
- Towards Ultra-Low-Voltage and Ultra-Low-Power Discrete-Time Receivers for Internet-of-Things (2018) (2)
- RF CMOS Oscillators for Modern Wireless Applications (2022) (2)
- A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and <−54-dBc Spurs Under 50-mVpp Supply Ripple (2022) (2)
- A 77/79-GHz Frequency Generator in 16-nm CMOS for FMCW Radar Applications Based on a 26-GHz Oscillator with Co-Generated Third Harmonic (2019) (2)
- Passive SC ΔΣ Modulator Based on Pipelined Charge-Sharing Rotation in 28-nm CMOS. (2020) (2)
- RF Clock Distribution System for a Scalable Quantum Processor in 22-nm FDSOI Operating at 3.8 K Cryogenic Temperature (2020) (2)
- State-of-the-art and future directions of high-performance all-digital frequency synthesis in nanometer CMOS (2010) (2)
- An FM demodulator operating across 2–10GHz IF (2013) (2)
- A Broadband Continuous Class-FGaN MMIC PA Using Multi-Resonance Matching Network (2019) (2)
- CMOS RF Circuits for Wireless Applications (2006) (2)
- A Compact 0.2–0.3-V Inverse-Class-F23 Oscillator for Low 1/f3 Noise Over Wide Tuning Range (2021) (2)
- Cryogenic Low-Drop-Out Regulators Fully Integrated with Quantum Dot Array in 22-nm FD-SOI CMOS (2021) (2)
- A Ka-band Switched-Capacitor RFDAC Using Edge-Combining in 22nm FD-SOI (2021) (2)
- A Fully Integrated Reconfigurable Multimode Class-F2,3 GaN Power Amplifier (2020) (2)
- Mitigation of CMOS device variability in the transmitter amplitude path using Digital RF Processing (2008) (2)
- Crystal Drift Compensation in a Mobile Phone (2006) (2)
- A Distributed Stubs Technique to Mitigate Flicker Noise Upconversion in a mm-Wave Rotary Traveling-Wave Oscillator (2021) (2)
- A 4GHz clock distribution architecture using subharmonically injection-locked coupled oscillators with clock skew calibration in 16nm CMOS (2017) (2)
- An SoC with automatic bias optimization of an RF oscillator (2009) (2)
- Interchannel Mismatch Calibration Techniques for Time-Interleaved SAR ADCs (2021) (2)
- Bias Generation and Calibration of CMOS Charge Qubits at 3.5 Kelvin in 22-nm FDSOI (2021) (2)
- Digital RF processing techniques for SoC radios (invited) (2005) (2)
- A 0.85mm2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD2 Self-Suppression and Pulling Mitigation (2019) (2)
- A 1.2V 110-MHz-UGB differential class-AB amplifier in 65nm CMOS (2014) (2)
- Behavioral Modelling and Optimization of a Cyclic Feedback-Based Successive Approximation TDC with Dynamic Delay Equalization (2019) (2)
- Digital RF processor (DRP™) for cellular phones (2005) (2)
- Digitally Enhanced Alternate Path Linearization of RF Receivers (2011) (2)
- A Millimeter-Wave ADPLL With Reference Oversampling and Third-Harmonic Extraction Featuring High FoMjitter-N (2021) (2)
- A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS (2021) (1)
- Design of High-IF Discrete-Time Receivers for IoT: Demystifying Aliasing Trade-Offs (2022) (1)
- A Feedforward and Feedback Constant-Slope Digital-to-Time Converter in 28nm CMOS Achieving ≤ 0.12% INL/Range over >100mV Supply Range (2021) (1)
- Techniques for the Analysis of Digital BangBang PLLs (2011) (1)
- A Low Profile Highly Isolated Phased Array MIMO Antenna System for 5G Applications at 28 GHz (2021) (1)
- Flicker Phase-Noise Reduction Using Gate–Drain Phase Shift in Transformer-Based Oscillators (2022) (1)
- An On-Chip Self-Characterization of a Digital-to-Time Converter by Embedding it in a First-Order $\Delta\Sigma$ Loop (2018) (1)
- Towards the Co-Simulation of Charge Qubits: A Methodology Grounding on an Equivalent Circuit Representation (2021) (1)
- Adaptive MultiMode RF FrontEnd Circuits (2011) (1)
- A 4.4mW-TX, 3.6 mW-RX Fully Integrated Bluetooth Low Energy Transceiver for IoT Applications (2018) (1)
- Cryogenic Transistor Confinement Well Simulation through Material and Carrier Transport Decoupling (2022) (1)
- IEEE 802.11n-2009 Standard + IEEE 802.11n Mac Layer e-Learning Course Bundle (2012) (1)
- Design and calibration procedure of a proposed V-band antenna array on fused silica technology intended for MIMO applications (2018) (1)
- All-Digital RF <formula formulatype="inline"><tex Notation="TeX">$I/Q$</tex></formula> Modulator (2012) (1)
- A Charge-Sharing IIR Filter With Linear Interpolation and High Stopband Rejection (2022) (1)
- A Gm-Boosting Technique for Millimeter-Wave Low-Noise Amplifiers in 28-nm Triple-Well Bulk CMOS Using Floating Resistor in Body Biasing (2022) (1)
- A Verilog-A Model of the Shuttle of an Electron in a Two Quantum-Dot System (2019) (1)
- A 28-GHz Switched-Filter Phase Shifter with Fine Phase-Tuning Capability Using Back-Gate Biasing in 22-nm FD-SOI CMOS (2021) (1)
- Dynamic bandwidth adjustment of an RF all-digital PLL (2011) (1)
- On the portability and performance of fully monolithic transformer structures for RF power amplfiers in standard CMOS process (2008) (1)
- A methodological approach for the minimization of self-interference effects in highly integrated transceiver SoCs (2009) (1)
- All-digital RF frequency modulation (2011) (1)
- A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur (2022) (1)
- CMOS Quantum Computing: Toward A Quantum Computer System-on-Chip. (2020) (1)
- A 31- $\mu$ W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS (2019) (1)
- Three-Winding Transformer-Based 60-GHz DCO With −185.1-dB FoM in 40-nm CMOS (2022) (1)
- Appendix B: Gaussian Pulse‐Shaping Filter (2005) (1)
- A 1.8dB NF Receiver front-end for GSM/GPRS in a 90nm Digital CMOS (2005) (1)
- Overview of FrontEnd RF Passive Integration into SoCs (2011) (1)
- A DPLL-Based Phase Modulator Achieving -46dB EVM with A Fast Two-Step DCO Nonlinearity Calibration and Non-Uniform Clock Compensation (2022) (1)
- Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS (2021) (1)
- A 24–31 GHz Reference Oversampling ADPLL Achieving FoMjitter−N of -269.3 dB (2021) (1)
- Topological order detection and qubit encoding in Su–Schrieffer–Heeger type quantum dot arrays (2022) (1)
- Oscillator-based ADCs: An exploration of time-mode analog-to-digital conversion (2017) (1)
- A Sigma-Delta ADC with Decimation and Gain Control Function for a Bluetooth Receiver in 130 nm Digital CMOS (2006) (1)
- Self-calibration of a power pre-amplifier in a digital polar transmitter (2010) (1)
- An Active-Under-Coil RFDAC With Analog Linear Interpolation in 28-nm CMOS (2021) (1)
- Low power techniques and design tradeoffs in adaptive FIR filtering for PRML read channels (2000) (1)
- Is RF doomed to digitization? What shall RF circuit designers do? (2012) (1)
- Linearity and Efficiency Strategies for NextGeneration Wireless Communications (2011) (1)
- Digital RF Processor Serves Plethora Of Cellular Systems (2009) (1)
- Method and device for retiming of an asynchronous clock (2001) (0)
- DL R. Bogdan Staszewski Addresses SSCS-Taipei on Fundamentals of Digital RF and Digitally Assisted RF in March [People] (2011) (0)
- Wireless Discrete-Time Receivers (2022) (0)
- Scalable multi-chip quantum architectures enabled by cryogenic hybrid wireless/quantum-coherent network-in-package (2023) (0)
- I Lllll Llllllll Ii Llllll Lllll Lllll Lllll Lllll Lllll Lllll Lllll 111111111111111111111111111111111 Us 20140085012al C19) United States C12) Patent Application Publication (2013) (0)
- Broadband Fully Integrated GaN Power Amplifier With Embedded Minimum Inductor Bandpass Filter and AM–PM Compensation (2019) (0)
- Challenges in integrated CMOS transceivers for short distance wireless (2001) (0)
- New Type of Airborne Agricultural Equipment (1980) (0)
- Title Fractional spur suppression in all-digital phase-locked loops (2017) (0)
- Application: A 60-GHz All-Digital PLL for FMCW Transmitter Applications (2015) (0)
- A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain–Gate–Source for Low Flicker Phase Noise and I/Q Exactness (2023) (0)
- Digitally Assisted RF Architectures: Two Illustrative Designs (2011) (0)
- ET4371: "Digital RF" (2013) (0)
- US 7 , 786 , 913 B 2 Page 2 OTHER PUBLICATIONS (2017) (0)
- Bias Generation and Calibration of CMOS Charge Qubits at 3.5 Kelvin in 22-nm FDSOI (2021) (0)
- RF front-end (RFDAC) of the polar transmitter (2017) (0)
- Cryogenic Controller for Electrostatically Controlled Quantum Dots in 22-nm Quantum SoC (2022) (0)
- Differential I/Q DPA and power-combining network * *The authors acknowledge substantial contributions from Prof. Dr. Leo de Vreede (TU Delft). (2017) (0)
- SoftwareDefined Radio Front Ends (2011) (0)
- Control of Quantum Systems: Comparison of Different Techniques by the Example of Charge and Spin Semiconductor Qubits (2022) (0)
- Future of RFDAC (2017) (0)
- Electrostatic Control and Entanglement of CMOS Position-Based Qubits (2020) (0)
- Appendix A: Spurs Due to DCO Switching (2005) (0)
- Charge Analysis in SAR ADC with Discrete-Time Reference Driver (2020) (0)
- A Wideband Digital-to-Frequency Converter with Built-In Mechanism for Self-Interference Mitigation (2016) (0)
- An Edge-Combining Frequency-Multiplying Class-D Power Amplifier (2023) (0)
- Chapter 5 – Millimeter-Wave Digitally Controlled Oscillator (2015) (0)
- An On-Chip Self-Characterization of a Digital-to-Time Converter by Embedding it in a First-Order <inline-formula> <tex-math notation="LaTeX">$\Delta\Sigma$ </tex-math></inline-formula> Loop (2018) (0)
- Chapter 11 – Measurement results of the 2 × 13-bit I/Q RFDAC* (2017) (0)
- A Wideband Digital-to-Frequency Converter with Built-In Mechanism for Self-Interference Mitigation (2016) (0)
- Session 20 overview: RF frequency generation: RF subcommittee (2012) (0)
- Type II completely digital phase-locked loop (2004) (0)
- Chapter 8 – Design for Test of the mm-Wave ADPLL (2015) (0)
- LowPower Spectrum Processors for Cognitive Radios (2011) (0)
- Time-Domain Techniques for mm-Wave Frequency Generation (2015) (0)
- GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS (0)
- Modelling of Electron Injection and Confinement in Cryogenic 22-nm FD-SOI Quantum Dot Arrays (2022) (0)
- Modeling of an Electronic Noise and Media in a Magnetic Recording Read Channel Using VHDL (2007) (0)
- A Python-Verilog Toolbox for Modeling of a Hadamard Gate Based on Position-Based CMOS Qubits (2019) (0)
- Multirate Timestamp Modeling for Ultralow-Jitter Frequency Synthesis: A Tutorial (2022) (0)
- Title A High IIP 2 SAW-Less Superheterodyne Receiver with Multi-Stage Harmonic Rejection (0)
- Ultra-low phase noise ADPLL for millimeter wave (2020) (0)
- Session 24 Overview: Wireless Receivers and Synthesizers (2017) (0)
- Appendix C: VHDL Source Code (2005) (0)
- A Compact, Low-Power, Low-NF, Millimeter-Wave Cascode LNA With Magnetic Coupling Feedback in 22-nm FD-SOI CMOS for 5G Applications (2023) (0)
- Correction to “A 32–42-GHz RTWO-Based Frequency Quadrupler Achieving >37 dBc Harmonic Rejection in 22-nm FD-SOI” (2021) (0)
- A 55.9-fs Integrated Jitter (100 kHz–100 MHz) Hybrid LC-Tank PLL in 5-nm FinFET Using Programmable Phase Realignment and Dynamic Coarse Tuning (2021) (0)
- F1: Advanced transmitters for wireless infrastructure (2011) (0)
- A CMOS Impedance Sensor for MEMS Adaptive Antenna Matching (2017) (0)
- Mixer using sub-sampling of signals (2001) (0)
- A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit (2022) (0)
- Delft University of Technology A Fully Integrated Discrete-Time Superheterodyne Receiver (2018) (0)
- Transmission filter whose reference clock is not an integer multiple of the symbol clock (2002) (0)
- A Charge-Rotating IIR Filter with Linear Interpolation and High Stop-Band Rejection (2021) (0)
- Clock generation (2019) (0)
- Charge and Hybrid Qubits in 22nm FDSOI process (2020) (0)
- Oversampled ADC Using VCOBased Quantizers (2011) (0)
- DTC-Assisted All-Digital Phase-Locked Loop Exploiting Hybrid Time/Voltage Phase Digitization (2019) (0)
- (54) CLOCK GENERATOR FOR GENERATING OUTPUT CLOCK HAVING NON-HARMONIC RELATIONSHIP WITH INPUT CLOCK AND RELATED CLOCK GENERATING METHOD THEREOF (2013) (0)
- Cost-Efficient, Transmission (2015) (0)
- A 1 . 8 dB NF Receiver front-end for GSM / GPRS in a 90 nm Digital CMOS (2005) (0)
- Tutorial #1: Implementation considerations for CMOS millimeter wave circuits and systems (2011) (0)
- Digital polar transmitter architecture (2017) (0)
- Two-Fold Noise-Cancelling Low-Noise Amplifier in 28-nm CMOS (2019) (0)
- SA 19.5: A 160MHz Analog Equalizer for Magnetic Disk Read Channels (1997) (0)
- SE3: Favorite Circuit Design and Testing Mistakes of Starting Engineers (2021) (0)
- RF Amplitude Control in an All-Digital PLL based Transmitter (2005) (0)
- All-Digital RF Phase-Locked Loops Exploiting Phase Prediction (2014) (0)
- DL Bogdan Staszewski Presents Seminar on RF at SSCS-Shanghai: Toward a Radio Frequency Computer [People] (2012) (0)
- Digital Techniques for Higher RF Performance (2015) (0)
- Chapter 2 – Millimeter-Wave Frequency Synthesizers (2016) (0)
- Toward high-resolution RFDAC: The system design perspective**The authors acknowledge substantial contributions from Prof. Dr. Leo de Vreede (TU Delft). (2017) (0)
- Time-Domain Multiply-Accumulator using Digital-to-Time Multiplier for CNN Processors in 28-nm CMOS (2020) (0)
- A Switched-Capacitor DC-DC Converter Powering an LC Oscillator to Achieve 85% System Peak Power Efficiency and −65dBc Spurious Tones (2020) (0)
- Exploring Speed Maximization of Frequency-to-Digital Conversion for Ultra-Low-Voltage VCO-Based ADCs (2023) (0)
- Reduced External Hardware and Reconfigurable RF Receiver Front Ends for Wireless Mobile Terminals (2011) (0)
- An On-Chip Picoampere-Level Leakage Current Sensor for Quantum Processors in 22-nm FD-SOI CMOS (2022) (0)
- Autonomous predistortion calibration of an RF power amplifier (2011) (0)
- Advances in Digital RF Architectures and Digitally-Assisted RF (2010) (0)
- Delft University of Technology An Ultracompact 9.4–14.8-GHz Transformer-Based Fractional-N All-Digital PLL in 40-nm CMOS (2017) (0)
- EFFECTS OF LONGW ALL MINING SUBSIDENCE ON GROUND WATER LEVELS WITHIN A WATERSHED HYDRAULICALLY ISOLATED FROM MINE DRAINAGE (1994) (0)
- A Clock-Phase Reuse Technique for Discrete-Time Bandpass Filters (2022) (0)
- Silicon timing sensors (2021) (0)
- A Digital-to-Time Converter Based on Crystal Oscillator Waveform Achieving 86-fs Jitter in 22-nm FD-SOI CMOS (2022) (0)
- Exponential extended flash time-to-digital converter (2016) (0)
- Behavioral Modeling and Simulation (2005) (0)
- An 85-GHz Low-Power Low-Noise Amplifier with 15 GHz Bandwidth in 22nm FD-SOI CMOS for 5G Communications (2022) (0)
- United States Patent Staszewski (2009) (0)
- Passive SC $\Delta\Sigma$ Modulator Based on Pipelined Charge-Sharing Rotation in 28-nm CMOS (2020) (0)
- Introduction to the Special Issue on the 46th European Solid-State Circuits Conference (ESSCIRC) (2017) (0)
- Digital baseband of the polar transmitter (2017) (0)
- A Sigma-Delta ADCwith Decimation and Gain Control Function for a Bluetooth Receiver in 130 nmDigital CMOS (2006) (0)
- Mitigation of CMOS Device Variability in Digital RF Processor (2008) (0)
- Other Publications Khurram Waheed, Et Ai., Injection Spurs Due to Reference Frequency Retiming by a Channel Dependent Clock at the Adpll Rf Output and Its Mitigation, Ieee International Symposium on Circuits and Systems (2010) (0)
- (54) APPARATUS AND METHOD FOR CALIBRATING TIMING MISMATCH OF EDGE ROTATOR OPERATING ON MULTIPLE PHASES OF OSCILLATOR (75) Inventors: Chi-Hsueh Wang, Kaohsiung (TW); (2014) (0)
- A 0.5ps 1.4mW 50MS/s Nyquist bandwidth time amplifier based two-step flash-ΔΣ time-to-digital converter (2016) (0)
- Cellular and wireless LAN transceivers: From systems to circuit design (2011) (0)
- Chapter 3 – Circuit Design Techniques for mm-Wave Frequency Synthesizer (2015) (0)
- Design of a Non-Linear Sized I/Q Digital PA for 5G mm-Wave Communications in 28 nm CMOS (2020) (0)
- A wideband 2 x 13-bit all-digital I / Q RF (2018) (0)
- Title Analysis and Design of a High-Order Discrete-Time Passive IIR Low-Pass Filter (0)
- ES5: Can RF SoCs (Self)test their own RF? (2010) (0)
- OFDM TransformDomain Receivers for MultiStandard Communications (2011) (0)
- 28 GHz Quadrature Frequency Generation Exploiting Injection-Locked Harmonic Extractors for 5G Communications (2019) (0)
- All-Digital PLL with Variable Loop Type Characteristics (2006) (0)
- Fractional spur suppression in all-digital phase-locked loops (2015) (0)
- WSG: Challenges for future RF integration (2009) (0)
- Orthogonal summation: A 2 × 3-bit all-digital I/Q RFDAC**The authors acknowledge substantial contributions from Prof. Dr. Leo de Vreede (TU Delft). (2017) (0)
- Application: ADPLL‐Based Transmitter (2005) (0)
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What Schools Are Affiliated With Robert Bogdan Staszewski?
Robert Bogdan Staszewski is affiliated with the following schools:
