Rolf Drechsler

Q: What Schools Are Affiliated With Rolf Drechsler

Rolf Drechsler is affiliated with the following schools: University of Bremen, Johannes Kepler University Linz, University of California, Berkeley, Stanford University

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Rolf Drechsler

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Rolf Drechsler

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Why Is Rolf Drechsler Influential?

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According to Wikipedia, Rolf Drechsler is an electrical engineer at the University of Bremen, Germany. He was named a Fellow of the Institute of Electrical and Electronics Engineers in 2015 for his contributions in testing and verification of electronic circuits and systems.

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Rolf Drechsler's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Applications of Evolutionary Computing, EvoWorkshops 2008: EvoCOMNET, EvoFIN, EvoHOT, EvoIASP, EvoMUSART, EvoNUM, EvoSTOC, and EvoTransLog, Naples, Italy, March 26-28, 2008. Proceedings (2008) (568)
RevLib: An Online Resource for Reversible Functions and Reversible Circuits (2008) (433)
BDD-based synthesis of reversible logic for large functions (2009) (324)
Applications of Evolutionary Computing (2004) (237)
Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams (1994) (228)
Binary Decision Diagrams - Theory and Implementation (2013) (201)
Synthesis of quantum circuits for linear nearest neighbor architectures (2011) (187)
Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques (2009) (184)
Verifying UML/OCL models using Boolean satisfiability (2010) (155)
RTL-datapath verification using integer linear programming (2002) (143)
Binary decision diagrams in theory and practice (2001) (123)
A genetic algorithm for variable ordering of obdds (1996) (118)
Towards a Design Flow for Reversible Logic (2010) (116)
Advanced Formal Verification (2004) (115)
RevKit: A Toolkit for Reversible Circuit Design (2012) (110)
Automatic Fault Localization for Property Checking (2006) (110)
Multi-objective Optimisation Based on Relation Favour (2001) (110)
Robust Multi-Objective Optimization in High Dimensional Spaces (2007) (109)
On Acceleration of SAT-Based ATPG for Industrial Designs (2008) (107)
Synthesis of reversible circuits with minimal lines for large functions (2012) (105)
Look-ahead schemes for nearest neighbor optimization of 1D and 2D quantum circuits (2016) (103)
Fast OFDD based minimization of fixed polarity Reed-Muller expressions (1994) (101)
Implementing a multiple-valued decision diagram package (1998) (98)
An Energy-Aware Model for the Logic Synthesis of Quantum-Dot Cellular Automata (2018) (95)
Equivalence Checking of Reversible Circuits (2009) (89)
QMDDs: Efficient Quantum Function Representation and Manipulation (2016) (89)
Determining the minimal number of swap gates for multi-dimensional nearest neighbor quantum circuits (2015) (87)
RevKit: An Open Source Toolkit for the Design of Reversible Circuits (2011) (87)
Exact Reordering of Circuit Lines for Nearest Neighbor Quantum Architectures (2014) (86)
Assisted Behavior Driven Development Using Natural Language Processing (2012) (86)
Proving transaction and system-level properties of untimed SystemC TLM designs (2010) (84)
Spectral Techniques in VLSI CAD (2001) (84)
Post-verification debugging of hierarchical designs (2005) (83)
Formal verification of integer multipliers by combining Gröbner basis with logic reduction (2016) (77)
Reducing Reversible Circuit Cost by Adding Lines (2010) (75)
K*BMDs: a new data structure for verification (1996) (74)
On the Relation between BDDs and FDDs (1995) (73)
BDD minimization using symmetries (1999) (71)
Using lower bounds during dynamic BDD minimization (1999) (70)
Exact one-pass synthesis of digital microfluidic biochips (2014) (70)
On the construction of multiple-valued decision diagrams (2002) (69)
Using unsatisfiable cores to debug multiple design errors (2008) (69)
Optimal SWAP gate insertion for nearest neighbor quantum circuits (2014) (69)
Reducing the number of lines in reversible circuits (2010) (66)
Synthesis of fully testable circuits from BDDs (2004) (65)
Verifying dynamic aspects of UML models (2011) (65)
Fast exact minimization of BDDs (1998) (65)
SyReC: A Programming Language for Synthesis of Reversible Circuits (2010) (64)
SWORD: A SAT like prover using word level information (2007) (60)
Formal verification of LTL formulas for SystemC designs (2003) (60)
Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs (2016) (60)
Encoding OCL Data Types for SAT-Based Verification of UML/OCL Models (2011) (59)
The K*BMD: A Verification Data Structure (1997) (57)
Binary decision diagrams (1998) (57)
Ordered Kronecker functional decision diagrams-a data structure for representation and manipulation of Boolean functions (1998) (57)
Trading off circuit lines and gate costs in the synthesis of reversible logic (2014) (57)
Automatic design of low-power encoders using reversible circuit synthesis (2012) (56)
PASSAT: efficient SAT-based test pattern generation for industrial circuits (2005) (56)
Improved SAT-based ATPG: More constraints, better compaction (2013) (56)
How many Decomposition Types do we need (1995) (55)
Reversible Logic Synthesis with Output Permutation (2009) (53)
Approximation-aware rewriting of AIGs for error tolerant applications (2016) (52)
HW/SW co-verification of embedded systems using bounded model checking (2006) (52)
Improving the mapping of reversible circuits to quantum circuits using multiple target lines (2013) (52)
Weighted A* search - unifying view and application (2009) (52)
Debugging sequential circuits using Boolean satisfiability (2004) (52)
Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares (2008) (50)
Determining the minimal number of lines for large reversible circuits (2011) (49)
Learning heuristics for OKFDD minimization by evolutionary algorithms (1996) (49)
Embedding of Large Boolean Functions for Reversible Logic (2014) (48)
Mapping NCV Circuits to Optimized Clifford+T Circuits (2014) (48)
Safety evaluation of automotive electronics using Virtual Prototypes: State of the art and research challenges (2014) (47)
Automatic Generation of Complex Properties for Hardware Designs (2008) (47)
Exact sat-based toffoli network synthesis (2007) (47)
Formal Verification of Circuits (2000) (47)
Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic (2010) (47)
Minimization of free BDDs (1999) (47)
Evolutionary algorithms for VLSI CAD (1998) (46)
Verifying SystemC using an intermediate verification language and symbolic simulation (2013) (46)
MORE: an alternative implementation of BDD packages by multi-operand synthesis (1996) (46)
Quality-Driven SystemC Design (2009) (46)
Fast exact minimization of BDD's (2000) (46)
Advanced BDD optimization (2005) (45)
A general and exact routing methodology for Digital Microfluidic Biochips (2015) (45)
Exact routing for digital microfluidic biochips with temporary blockages (2014) (44)
BDD minimization for approximate computing (2016) (44)
Polynomial Formal Verification of Multipliers (1997) (44)
From Truth Tables to Programming Languages: Progress in the Design of Reversible Circuits (2011) (44)
A Basis for Formal Robustness Checking (2008) (44)
Ancilla-free synthesis of large reversible functions using binary decision diagrams (2014) (44)
Hierarchical synthesis of reversible circuits using positive and negative Davio decomposition (2010) (44)
Synthesis of Reversible Functions Beyond Gate Count and Quantum Cost (2010) (44)
Reachability analysis for formal verification of SystemC (2002) (43)
Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions (1995) (43)
Formal verification of word-level specifications (1999) (42)
Test Pattern Generation using Boolean Proof Engines (2009) (42)
Low power optimization technique for BDD mapped circuits (2001) (42)
RevSCA: Using Reverse Engineering to Bring Light into Backward Rewriting for Big and Dirty Multipliers (2019) (41)
Logic Synthesis for RRAM-Based In-Memory Computing (2018) (41)
Exact routing for micro-electrode-dot-array digital microfluidic biochips (2017) (40)
Circuit design from Kronecker Galois field decision diagrams for multiple-valued functions (1997) (39)
Extensible and Configurable RISC-V Based Virtual Prototype (2018) (39)
CRAVE: An advanced constrained random verification environment for SystemC (2012) (39)
Dynamic minimization of OKFDDs (1995) (39)
Exploiting Negative Control Lines in the Optimization of Reversible Circuits (2013) (38)
Symmetry Based Variable Ordering for ROBDDs (1995) (38)
Functional simulation using binary decision diagrams (1997) (38)
Debugging of inconsistent UML/OCL models (2012) (37)
SMT-based stimuli generation in the SystemC Verification library (2009) (37)
Debugging of Toffoli networks (2009) (37)
Efficient synthesis of quantum circuits implementing clifford group operations (2014) (37)
ATPG for Reversible Circuits Using Simulation, Boolean Satisfiability, and Pseudo Boolean Optimization (2011) (37)
On quantum circuits employing roots of the Pauli matrices (2013) (36)
Pseudo Kronecker expressions for symmetric functions (1997) (36)
An MIG-based compiler for programmable logic-in-memory architectures (2016) (36)
PolyCleaner: Clean your Polynomials before Backward Rewriting to verify Million-gate Multipliers (2018) (36)
Precise error determination of approximated components in sequential circuits with model checking (2016) (35)
An improved branch and bound algorithm for exact BDD minimization (2003) (35)
Improving ESOP-Based Synthesis of Reversible Logic Using Evolutionary Algorithms (2011) (35)
RISC-V based virtual prototype: An extensible and configurable platform for the system-level (2020) (34)
On the relation between SAT and BDDs for equivalence checking (2002) (34)
CheckSyC: an efficient property checker for RTL SystemC designs (2005) (34)
Combining ordered best-first search with branch and bound for exact BDD minimization (2004) (34)
Analyzing Functional Coverage in Bounded Model Checking (2008) (34)
Technology Mapping of Reversible Circuits to Clifford+T Quantum Circuits (2016) (33)
Minimizing the number of paths in BDDs: Theory and algorithm (2006) (33)
ParSyC: An Efficient SystemC Parser (2004) (33)
Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines (2012) (33)
Formal Specification Level: Towards verification-driven design based on natural language processing (2012) (32)
Effective Robustness Analysis Using Bounded Model Checking Techniques (2011) (32)
Functional decomposition of MVL functions using multi-valued decision diagrams (1997) (32)
metaSMT: Focus on Your Application not on Solver Integration (2011) (32)
Checkers for SystemC designs (2004) (31)
Window optimization of reversible and quantum circuits (2010) (31)
Efficient Automatic Visualization of SystemC Designs (2003) (31)
Automatic TLM Fault Localization for SystemC (2012) (30)
Managing don't cares in Boolean satisfiability (2004) (30)
An exact method for design exploration of quantum-dot cellular automata (2018) (30)
Increasing the accuracy of SAT-based debugging (2009) (30)
Estimating Functional Coverage in Bounded Model Checking (2007) (29)
Synthesis for testability: circuits derived from ordered Kronecker functional decision diagrams (1995) (29)
On variable ordering and decomposition type choice in OKFDDs (1995) (29)
Scalable One-Pass Synthesis for Digital Microfluidic Biochips (2015) (29)
The system verification methodology for advanced TLM verification (2012) (28)
ACTion: combining logic synthesis and technology mapping for MUX based FPGAs (2000) (28)
Time-resolved detection of diffusion limited temperature gradients inside single isolated burning droplets using Rainbow Refractometry (2016) (28)
Logic Minimization and Testability of 2-SPP Networks (2008) (28)
ESL Design and Verification (2010) (28)
Verifying SystemC Using Intermediate Verification Language and Stateful Symbolic Simulation (2019) (28)
Quantum Circuit Optimization by Hadamard Gate Reduction (2014) (28)
Keynote: Formal specification level: Towards verification-driven design based on natural language processing (2012) (27)
Improving simulation-based verification by means of formal methods (2004) (27)
Synthesizing checkers for on-line verification of System-on-Chip designs (2003) (27)
Evolutionary Algorithms for Embedded System Design (2002) (27)
Verifying Instruction Set Simulators using Coverage-guided Fuzzing* (2019) (26)
Towards Formal Verification of Optimized and Industrial Multipliers (2020) (26)
SyCE: an integrated environment for system design in SystemC (2005) (26)
A Genetic Algorithm for Minimization of Fixed Polarity Reed-Muller Expressions (1995) (26)
Design of experiments in CAD: context and new data sets for ISCAS'99 (1999) (26)
Computing bounds for fault tolerance using formal techniques (2009) (26)
On the representational power of bit-level and word-level decision diagrams (1997) (26)
Equivalence Checking in Multi-level Quantum Systems (2014) (26)
Compiled Symbolic Simulation for SystemC (2016) (26)
Reverse BDD-based synthesis for splitter-free optical circuits (2015) (25)
SyReC: A hardware description language for the specification and synthesis of reversible circuits (2016) (25)
Verification of multi-valued logic networks (1996) (25)
Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits (1999) (25)
A new SAT-based ATPG for generating highly compacted test sets (2012) (25)
As-Robust-As-Possible test generation in the presence of small delay defects using pseudo-Boolean optimization (2011) (25)
Testability of 2-Level AND/EXOR Circuits (1997) (25)
Linear transformations and exact minimization of BDDs (1998) (25)
Efficiency of Multi-Valued Encoding in SAT-based ATPG (2006) (24)
Behavior Driven Development for circuit design and verification (2012) (24)
Multi-objected Optimization in Evolutionary Algorithms Using Satisfiability Classes (1999) (24)
A Novel Approach for Nearest Neighbor Realization of 2D Quantum Circuits (2018) (24)
Priorities in multi-objective optimization for genetic programming (2001) (24)
Equivalence checking using Gröbner bases (2016) (24)
Reducing the Depth of Quantum Circuits Using Additional Circuit Lines (2013) (24)
Transformations amongst the Walsh, Haar, Arithmetic and Reed-Muller Spectral Domains (2001) (23)
Using QBF to increase accuracy of SAT-based debugging (2010) (23)
High Quality Test Pattern Generation and Boolean Satisfiability (2012) (23)
OFDD based minimization of fixed polarity Reed-Muller expressions using hybrid genetic algorithms (1994) (23)
Gatecomp: Equivalence Checking of Digital Circuits in an Industrial Environment (2002) (23)
Project-based learning in student teams in computer science education (2005) (23)
VERIFICATION OF PLC PROGRAMS USING FORMAL PROOF TECHNIQUES (2008) (23)
Dynamic minimization of word-level decision diagrams (1998) (23)
Exact Template Matching Using Boolean Satisfiability (2013) (23)
Analyzing Inconsistencies in UML/OCL Models (2016) (23)
Ground setting properties for an efficient translation of OCL in SMT-based model finding (2016) (23)
Automatic Test Pattern Generation (2006) (23)
OKFDDs versus OBDDs and OFDDs (1995) (23)
Completeness-Driven Development (2012) (23)
A hybrid genetic algorithm for the channel routing problem (1996) (22)
Improved synthesis of Clifford+T quantum functionality (2018) (22)
Requirements Engineering for Cyber-Physical Systems - Challenges in the Context of "Industrie 4.0" (2014) (22)
Optimization-based multiple target test generation for highly compacted test sets (2014) (22)
Incremental Solving Techniques for SAT-based ATPG (2010) (22)
Checking concurrent behavior in UML/OCL models (2015) (22)
Approximation-aware testing for approximate circuits (2018) (22)
PolyAdd: Polynomial Formal Verification of Adder Circuits (2020) (22)
Improving Test Pattern Compactness in SAT-based ATPG (2007) (22)
BiTeS: a BDD based test pattern generator for strong robust path delay faults (1994) (22)
Minimization of the expected path length in BDDs based on local changes (2004) (22)
Decision Diagram Method for Calculation of Pruned Walsh Transform (2001) (22)
Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology - (Invited Paper) (2012) (22)
Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits (2012) (21)
Efficient graph based representation of multi-valued functions with an application to genetic algorithms (1994) (21)
Verifying the structure and behavior in UML/OCL models using satisfiability solvers (2016) (21)
Learning heuristics by genetic algorithms (1995) (21)
How many decomposition types do we need? [decision diagrams] (1995) (21)
Scalable design for field-coupled nanocomputing circuits (2019) (21)
Data extraction from SystemC designs using debug symbols and the SystemC API (2013) (21)
A formal model for embedded brain reading (2013) (21)
An Integrated SystemC Debugging Environment (2007) (21)
Efficient Data Structures and Methodologies for SAT-Based ATPG Providing High Fault Coverage in Industrial Application (2011) (20)
Minimization of BDDs by Evolutionary Algorithms (1997) (20)
Exact Circuit Synthesis (1998) (20)
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics (2010) (20)
Synthesizing multiplier in reversible logic (2010) (20)
Overview of decision diagrams (1997) (20)
Considering nearest neighbor constraints of quantum circuits at the reversible circuit level (2014) (20)
Improved SAT-based Reachability Analysis with Observability Don't Cares (2008) (20)
Early SoC security validation by VP-based static information flow analysis (2017) (20)
Early Concolic Testing of Embedded Binaries with Virtual Prototypes: A RISC-V Case Study* (2019) (20)
Utilizing BDDs for disjoint SOP minimization (2002) (20)
Exact Synthesis of Elementary Quantum Gate Circuits (2009) (20)
Formal Verification on the RT Level Computing One-To-One Design Abstractions by Signal Width Reduction (2001) (20)
Efficient Algorithms for Creation of Linearly-independent Decision Diagrams and their Mapping to Regular Layouts (2002) (19)
Accuracy and Compactness in Decision Diagrams for Quantum Computation (2019) (19)
Verifying SystemC using stateful symbolic simulation (2015) (19)
Approximate hardware generation using symbolic computer algebra employing grobner basis (2018) (19)
Finding good counter-examples to aid design verification (2003) (19)
MDD-based synthesis of multi-valued logic networks (2000) (19)
Crossing Reduction by Windows Optimization (2002) (19)
BDD-Based Synthesis of Reversible Logic (2010) (19)
Lips: An IDE for model driven engineering based on natural language processing (2013) (19)
Experimental studies on SAT-based test pattern generation for industrial circuits (2005) (18)
A guiding coverage metric for formal verification (2012) (18)
Minimizing the number of paths in BDDs (2002) (18)
Formal Modeling and Verification of Cyber-Physical Systems (2015) (18)
Scratch and Google Blockly: How Girls' Programming Skills and Attitudes are Influenced (2019) (18)
OKFDDs — Algorithms, Applications and Extensions (1996) (18)
Multi-Objective BDD Optimization with Evolutionary Algorithms (2015) (18)
Spectral decision diagrams using graph transformations (2001) (18)
BDD circuit optimization for path delay fault testability (2004) (18)
Upper bounds for reversible circuits based on Young subgroups (2014) (17)
Complexity of reversible circuits and their quantum implementations (2016) (17)
BDD Minimization by Linear Transformations (1998) (17)
Debugging sequential circuits using Boolean satisfiability (2004) (17)
AIBA: An Automated Intra-cycle Behavioral Analysis for SystemC-based design exploration (2016) (17)
Automating the translation of assertions using natural language processing techniques (2014) (17)
Recursive bi-partitioning of netlists for large number of partitions (2002) (17)
Synthesis of pseudo Kronecker lattice diagrams (1999) (17)
Fast and Accurate Performance Evaluation for RISC-V using Virtual Prototypes* (2020) (17)
Towards formal verification of real-world SystemC TLM peripheral models - a case study (2016) (17)
Testability properties of local circuit transformations with respect to the robust path-delay-fault model (1994) (17)
A Highly Fault-Efficient SAT-Based ATPG Flow (2012) (17)
Overcoming limitations of the SystemC data introspection (2009) (17)
metaSMT: focus on your application and not on solver integration (2017) (17)
Power consumption in XOR-based circuits (1999) (17)
System level validation using formal techniques (2005) (16)
Endurance management for resistive Logic-In-Memory computing architectures (2017) (16)
Coverage-Driven Stimuli Generation (2012) (16)
Automated Nonintrusive Analysis of Electronic System Level Designs (2020) (16)
Towards analyzing functional coverage in SystemC TLM property checking (2010) (16)
Complete and effective robustness checking by means of interpolation (2012) (16)
Ordered and shared, linearly-independent, variable-pair decision diagrams (1997) (16)
Circuit Line Minimization in the HDL-Based Synthesis of Reversible Logic (2012) (16)
A generic representation of CCSL time constraints for UML/MARTE models (2015) (16)
Simulation graphs for reverse engineering (2015) (16)
Advanced verification by automatic property generation (2009) (16)
System exploration of SystemC designs (2006) (16)
Verification of designs containing black boxes (2000) (16)
Induction-Based Formal Verification of SystemC TLM Designs (2009) (16)
Improvements for constraint solving in the systemc verification library (2007) (16)
Late Breaking Results: Polynomial Formal Verification of Fast Adders (2021) (16)
Towards Specification and Testing of RISC-V ISA Compliance⋆ (2020) (16)
Determining relevant model elements for the verification of UML/OCL specifications (2013) (15)
SBDD variable reordering based on probabilistic and evolutionary algorithms (1999) (15)
Efficient manipulation algorithms for linearly transformed BDDs (1999) (15)
Disjoint Sum of Product Minimization by Evolutionary Algorithms (2004) (15)
A fast untestability proof for SAT-based ATPG (2009) (15)
Heuristic Learning Based on Genetic Programming (2001) (15)
On Optimization-Based ATPG and Its Application for Highly Compacted Test Sets (2016) (15)
Speeding up SAT-Based ATPG Using Dynamic Clause Activation (2009) (15)
Multi-objective BDD optimization for RRAM based circuit design (2016) (15)
On the computational power of linearly transformed BDDs (2000) (15)
Evaluation of static variable ordering heuristics for MDD construction [multi-valued decision diagrams] (2002) (15)
Genetic Programming III: Darwinian Invention and Problem (1999) (15)
Frame conditions in symbolic representations of UML/OCL models (2016) (15)
Generating SystemC Implementations for Clock Constraints Specified in UML/MARTE CCSL (2014) (15)
Designing a RISC CPU in Reversible Logic (2011) (14)
Automated Analysis of Virtual Prototypes at Electronic System Level (2019) (14)
A PLiM Computer for the Internet of Things (2017) (14)
Efficient Cross-Level Testing for Processor Verification: A RISC- V Case-Study (2020) (14)
Smart Homes Programming: Development and Evaluation of an Educational Programming Application for Young Learners (2019) (14)
From biochips to quantum circuits: Computer-aided design for emerging technologies (2016) (14)
Integrating observability don't cares in all-solution SAT solvers (2006) (14)
Visualization of SystemC Designs (2007) (14)
ETDD-based synthesis of term-based FPGAs for incompletely specified Boolean functions (1998) (14)
Minimizing the number of one-paths in BDDs by an evolutionary algorithm (2003) (14)
Look-up table FPGA synthesis from minimized multi-valued pseudo Kronecker expressions (1998) (14)
Edge Verification: Ensuring Correctness under Resource Constraints (2021) (14)
fiction: An Open Source Framework for the Design of Field-coupled Nanocomputing Circuits (2019) (14)
Ternary and quaternary lattice diagrams for linearly-independent logic, multiple-valued logic, and analog synthesis (1997) (14)
Polynomial Formal Verification of Prefix Adders (2021) (14)
On the generation of area-time optimal testable adders (1995) (14)
Augmented sifting of multiple-valued decision diagrams (2003) (14)
Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques (2009) (14)
Polynomial Circuit Verification using BDDs (2021) (14)
Exploring superior structural materials using multi-objective optimization and formal techniques (2016) (14)
A multi-layer detailed routing approach based on evolutionary algorithms (1997) (13)
Robustness Check for Multiple Faults Using Formal Techniques (2009) (13)
On the Expressive Power of OKFDDs (1997) (13)
One Method - All Error-Metrics: A Three-Stage Approach for Error-Metric Evaluation in Approximate Computing (2019) (13)
Towards early validation of firmware-based power management using virtual prototypes: A constrained random approach (2017) (13)
Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation (2016) (13)
Fast and efficient construction of BDDs by reordering based synthesis (1997) (13)
Contradiction analysis for constraint-based random simulation (2008) (13)
An Effective Methodology for Integrating Concolic Testing with SystemC-based Virtual Prototypes (2021) (13)
Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization (2014) (13)
On the relation between simulation-based and SAT-based diagnosis (2006) (13)
Contradiction Analysis for Inconsistent Formal Models (2015) (13)
Exact channel routing using symbolic representation (1999) (13)
FoREnSiC- An Automatic Debugging Environment for C Programs (2012) (13)
Formal Specification Level (2012) (13)
A Synthesis Flow for Sequential Reversible Circuits (2012) (13)
Towards One-Pass Synthesis (2002) (13)
Verifying consistency between activity diagrams and their corresponding OCL contracts (2014) (13)
BDD-Based Synthesis for All-Optical Mach-Zehnder Interferometer Circuits (2015) (13)
Optimizing DD-based synthesis of reversible circuits using negative control lines (2014) (13)
SAT-based ATPG for Path Delay Faults in Sequential Circuits (2007) (12)
On the Difficulty of Inserting Trojans in Reversible Computing Architectures (2017) (12)
Formal Specification Level - Concepts, Methods, and Algorithms (2014) (12)
Fast heuristics for the edge coloring of large graphs (2003) (12)
Combination of lower bounds in exact BDD minimization (2003) (12)
Automatic Protocol Compliance Checking of SystemC TLM-2.0 Simulation Behavior Using Timed Automata (2017) (12)
Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques (2007) (12)
Detection of Hardware Trojans in SystemC HLS Designs via Coverage-guided Fuzzing (2019) (12)
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults (2007) (12)
Ensuring safety and reliability of IP-based system design – A container approach (2015) (12)
Panel: Future SoC verification methodology: UVM evolution or revolution? (2014) (12)
Debugging reversible circuits (2011) (12)
Scalable Simulation-Based Verification of SystemC-Based Virtual Prototypes (2019) (12)
Robust algorithms for high quality Test Pattern Generation using Boolean Satisfiability (2010) (12)
Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability (2008) (12)
Data flow testing for virtual prototypes (2017) (12)
A Cube Pairing Approach for Synthesis of ESOP-Based Reversible Circuit (2014) (12)
Generic implementation of DD packages in MVL (1999) (12)
Incorporating user preferences in many-objective optimization using relation ε-preferred (2015) (12)
ProACt: A Processor for High Performance On-demand Approximate Computing (2017) (12)
Genetic algorithm for minimisation of fixed polarity Reed-Muller expressions (2000) (12)
Security validation of VP-based SoCs using dynamic information flow tracking (2019) (12)
PREASC: Automatic Portion Resilience Evaluation for Approximating SystemC-based Designs Using Regression Analysis Techniques (2020) (12)
Reversible circuit rewriting with simulated annealing (2015) (12)
Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams (2003) (11)
Envisioning self-verification of electronic systems (2015) (11)
Reusing Learned Information in SAT-based ATPG (2007) (11)
Exact Toffoli Network Synthesis of Reversible Logic Using Boolean Satisfiability (2006) (11)
Gates vs. Splitters: Contradictory Optimization Objectives in the Synthesis of Optical Circuits (2016) (11)
A compact and efficient SAT encoding for quantum circuits (2013) (11)
Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression (2017) (11)
Evaluating the Impact of Interconnections in Quantum-Dot Cellular Automata (2018) (11)
Verification-Driven Design Across Abstraction Levels: A Case Study (2015) (11)
Formal System Verification (2018) (11)
BDD based synthesis of symmetric functions with full path-delay fault testability (2003) (11)
Property analysis and design understanding (2009) (11)
Evaluation of Cardinality Constraints on SMT-Based Debugging (2009) (11)
Synchronization of Clocked Field-Coupled Circuits (2018) (11)
Exact Synthesis of Ternary Reversible Functions Using Ternary Toffoli Gates (2017) (11)
Experimental Studies on SAT-Based ATPG for Gate Delay Faults (2007) (11)
Self-verification as the key technology for next generation electronic systems (2014) (11)
Polynomial Word-Level Verification of Arithmetic Circuits (2021) (11)
Resilience Evaluation for Approximating SystemC Designs Using Machine Learning Techniques (2018) (11)
Automated feature localization for dynamically generated SystemC designs (2015) (11)
Towards a generic verification methodology for system models (2013) (11)
Exploration of the Synchronization Constraint in Quantum-dot Cellular Automata (2018) (11)
On the "Q" in QMDDs: Efficient Representation of Quantum Functionality in the QMDD Data-Structure (2013) (11)
Evaluation of SAT like Proof Techniques for Formal Verification of Word Level Circuits (2007) (11)
Placement and Routing for Tile-based Field-coupled Nanocomputing Circuits Is NP-complete (Research Note) (2019) (11)
On local transformations and path delay fault testability (1995) (10)
Testability of SPP Three-Level Logic Networks in Static Fault Models (2006) (10)
Decision diagrams in synthesis-algorithms, applications and extensions (1997) (10)
Automatic equivalence checking for SystemC-TLM 2.0 models against their formal specifications (2017) (10)
Incremental SAT Instance Generation for SAT-based ATPG (2008) (10)
Towards Reverse Engineering Reversible Logic (2017) (10)
Enhancing debugging of multiple missing control errors in reversible logic (2010) (10)
LAYOUT-DRIVEN SYNTHESIS FOR SUBMICRON TECHNOLOGY: MAPPING EXPANSIONS TO REGULAR LATTICES (2000) (10)
Workshop on Microprocessor Test and Verification (2010) (10)
Utilizing don't care states in SAT-based bounded sequential problems (2005) (10)
Non-Clausal SAT and ATPG (2021) (10)
AND/EXOR-based synthesis of testable KFDD-circuits with small depth (1996) (10)
RevSCA-2.0: SCA-Based Formal Verification of Nontrivial Multipliers Using Reverse Engineering and Local Vanishing Removal (2021) (10)
Efficient Minimization of Fully Testable 2-SPP Networks (2006) (10)
Breaking Landauer's Limit\\Using Quantum-dot Cellular Automata (2018) (10)
Advanced Logic Synthesis (2018) (10)
Functional Coverage-Driven Characterization of RF Amplifiers (2019) (10)
Dynamic re-encoding during MDD minimization (2000) (10)
Overcoming the Tradeoff Between Accuracy and Compactness in Decision Diagrams for Quantum Computation (2020) (10)
Combining Symbolic Computer Algebra and Boolean Satisfiability for Automatic Debugging and Fixing of Complex Multipliers (2018) (10)
Fast and Efficient Equivalence Checking based on NAND-BDDs (2001) (10)
Using Word-Level Information in Formal Hardware Verification (2004) (10)
Evolutionary Algorithms in Computer-Aided Design of Integrated Circuits (1999) (10)
Verifying integrity of decision diagrams (1998) (10)
A genetic algorithm for RKRO minimization (1997) (10)
Validating SystemC implementations against their formal specifications (2014) (10)
Exploiting don't cares during data sequencing using genetic algorithms (1999) (10)
Computing walsh, arithmetic, and reed-muller spectral decision diagrams using graph transformations (2002) (10)
On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study (2016) (10)
Property Checking of Quantum Circuits Using Quantum Multiple-Valued Decision Diagrams (2012) (10)
Algorithms for Taylor Expansion Diagrams. (2004) (10)
MuTaTe: an efficient design for testability technique for multiplexor based circuits (2003) (10)
Probabilistic Equivalence Checking Using PartialHaar Spectral Diagrams (1999) (10)
Speeding Up Verification of RTL Designs by Computing One-to-one Abstractions with Reduced Signal Widths (2001) (10)
Instance Generation for SAT-based ATPG (2007) (9)
Fault Detection in Parity Preserving Reversible Circuits (2016) (9)
Analyzing SystemC Designs: SystemC Analysis Approaches for Varying Applications (2015) (9)
Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side* (2020) (9)
New hierarchies of AND/EXOR trees, decision diagrams, lattice diagrams, canonical forms and regular layouts (1997) (9)
Quantitative timing analysis of UML activity diagrams using statistical model checking (2016) (9)
SAT-based ATPG for reversible circuits (2010) (9)
Efficient Simulation-Based Debugging of Reversible Logic (2010) (9)
iTac: Aspect Based Sentiment Analysis using Sentiment Trees and Dictionaries (2014) (9)
Ignore Clocking Constraints: An Alternative Physical Design Methodology for Field-Coupled Nanotechnologies (2019) (9)
Identification of Efficient Clustering Techniques for Test Power Activity on the Layout (2017) (9)
Synthesis of circuits based on all-optical Mach-Zehnder Interferometers using Binary Decision Diagrams (2018) (9)
Safe IP Integration Using Container Modules (2014) (9)
Generating formal system models from natural language descriptions (2012) (9)
Verification of Embedded Binaries using Coverage-guided Fuzzing with SystemC-based Virtual Prototypes (2020) (9)
Automatic Fault Localization for Programmable Logic Controllers (2010) (9)
Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes (2020) (9)
Improved Cube List Based Cube Pairing Approach for Synthesis of ESOP Based Reversible Logic (2014) (9)
A canonical AND/EXOR form that includes both the generalized Reed-Muller forms and Kronecker forms (1997) (9)
Efficient Evolutionary Approaches for the Data Ordering Problem with Inversion (2006) (9)
Efficient Hierarchical System Debugging for Property Checking (2005) (9)
Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs (2010) (9)
Automated Design Understanding of SystemC-Based Virtual Prototypes: Data Extraction, Analysis and Visualization (2020) (9)
Towards lightweight satisfiability solvers for self-verification (2017) (9)
Design Automation Techniques for Approximation Circuits (2018) (9)
Minimal Stimuli Generation in Simulation-Based Verification (2013) (9)
Improving EAs for Sequencing Problems (2000) (9)
Logic Circuit Equivalence Checking Using Haar Spectral Coefficients and Partial BDDs (2002) (9)
Genetic algorithm for data sequencing (1997) (9)
Efficient Graph Coloring by Evolutionary Algorithms (1999) (9)
Automatic refinement checking for formal system models (2014) (9)
A better-than-worst-case robustness measure (2010) (9)
Foreword: Special Issue on Reversible Computation (2012) (9)
Machine Learning-based Prediction of Test Power (2019) (9)
Computer architecture core of knowledge for computer science studies (2015) (9)
Decision diagrams and AND/OR graphs for design automation problems (1997) (9)
Automated Analysis of Virtual Prototypes at the Electronic System Level (2020) (9)
Benefits of illustrations and videos for technical documentations (2015) (9)
Debugging at the Electronic System Level (2010) (9)
Improved minimization methods of pseudo Kronecker expressions for multiple output functions (1998) (9)
From reversible logic to quantum circuits: Logic design for an emerging technology (2016) (9)
Advanced exact synthesis of Clifford+T circuits (2020) (9)
Automatic property generation for the formal verification of bus bridges (2011) (9)
The Spectral Domain (2001) (9)
ParCoSS: Efficient Parallelized Compiled Symbolic Simulation (2016) (9)
Towards a Verification Flow Across Abstraction Levels Verifying Implementations Against Their Formal Specification (2017) (9)
An adaptive prioritized ε-preferred evolutionary algorithm for approximate BDD optimization (2017) (9)
Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis (2013) (8)
Towards fully automated TLM-to-RTL property refinement (2018) (8)
Efficient minimization of multiple-valued decision diagrams for incompletely specified functions (2003) (8)
Towards Self-Explaining Digital Systems: A Design Methodology for the Next Generation (2018) (8)
Scalable fault localization for SystemC TLM designs (2013) (8)
Towards automatic determination of problem bounds for object instantiation in static model verification (2011) (8)
Logic Synthesis for Majority Based In-Memory Computing (2017) (8)
Two Hierarchies Of Generalized Kronecker Trees, Forms, Decision Diagrams, And Regular Layouts (1997) (8)
Manipulation of *BMDs (1998) (8)
Machine learning based test pattern analysis for localizing critical power activity areas (2017) (8)
Near Zero-Energy Computation Using Quantum-Dot Cellular Automata (2018) (8)
Revealing properties of structural materials by combining regression-based algorithms and nano indentation measurements (2017) (8)
Reversible Circuits: IC/IP Piracy Attacks and Countermeasures (2019) (8)
PASSAT 2.0: A multi-functional SAT-based testing framework (2013) (8)
Design Space Exploration in the Mapping of Reversible Circuits to IBM Quantum Computers (2020) (8)
Testbench qualification for SystemC-AMS timed data flow models (2018) (8)
Efficient Construction of QMDDs for Irreversible, Reversible, and Quantum Functions (2017) (8)
Towards One-Pass Synthesis (2002) (8)
Technical Documentation of Software and Hardware in Embedded Systems (2006) (8)
Technische Informatik - eine Einführung (2005) (8)
Building Free Binary Decision Diagrams Using SAT Solvers (2007) (8)
Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking (2008) (8)
Simulation-based equivalence checking between SystemC models at different levels of abstraction (2011) (8)
SAT-Lancer: A Hardware SAT-Solver for Self-Verification (2018) (8)
Polynomial datapath optimization using constraint solving and formal modelling (2010) (8)
Clocks vs. instants relations: Verifying CCSL time constraints in UML/MARTE models (2016) (8)
VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers (2016) (8)
GenMul: Generating Architecturally Complex Multipliers to Challenge Formal Verification Tools (2021) (8)
Dual edge operations in reduced ordered binary decision diagrams (1998) (7)
Exact Synthesis of Biomolecular Protocols for Multiple Sample Pathways on Digital Microfluidic Biochips (2018) (7)
Effect of improved lower bounds in dynamic BDD reordering (2006) (7)
Integrating an SMT-Based ModelFinder into USE (2016) (7)
Better Late Than Never : Verification of Embedded Systems After Deployment (2019) (7)
Efficient realization of control logic in reversible circuits (2011) (7)
Testability of SPP Three-Level Logic Networks (2003) (7)
Towards Reversed Approximate Hardware Design (2018) (7)
Localizing features of ESL models for design understanding (2012) (7)
Power-aware Test Scheduling for IEEE 1687 Networks with Multiple Power Domains (2020) (7)
Graphenbasierte Funktionsdarstellung - Boolesche und Pseudo-Boolesche Funktionen (1998) (7)
Improved Fault Diagnosis for Reversible Circuits (2011) (7)
IC/IP Piracy Assessment of Reversible Logic (2018) (7)
CRAVE 2.0: The Next Generation Constrained Random Stimuli Generator for SystemC (2014) (7)
Combining SWAPs and Remote Toffoli Gates in the Mapping to IBM QX Architectures (2021) (7)
Improved Look-Ahead Approaches for Nearest Neighbor Synthesis of 1D Quantum Circuits (2019) (7)
Towards Formal Verification of Plans for Cognition-Enabled Autonomous Robotic Agents (2019) (7)
On the complexity of design tasks for Digital Microfluidic Biochips (2018) (7)
Through the Looking Glass: Automated Design Understanding of SystemC-Based VPs at the ESL (2022) (7)
Resilience evaluation via symbolic fault injection on intermediate code (2018) (7)
Random pattern fault simulation in multi-valued circuits (1995) (7)
Error Bounded Exact BDD Minimization in Approximate Computing (2017) (7)
Leveraging the Analysis for Invariant Independence in Formal System Models (2015) (7)
Data Flow Testing for SystemC-AMS Timed Data Flow Models (2019) (7)
Using Synthesis Techniques in SAT Solvers (2004) (7)
Improving Coverage of Simulation-Based Verification by Dedicated Stimuli Generation (2014) (7)
Fault Ordering for Automatic Test Pattern Generation of Reversible Circuits (2013) (7)
Lower bound sifting for MDDs (2000) (7)
Testability of circuits derived from functional decision diagrams (1994) (7)
Hardware-Software Co-Visualization: Developing systems in the holodeck (2013) (7)
Vertical IP Protection of the Next-Generation Devices: Quo Vadis? (2021) (7)
Adaptive Branch and Bound Using SAT to Estimate False Crosstalk (2008) (7)
Studies on Integrating SAT-based ATPG in an Industrial Environment (2007) (7)
Towards a methodology for self-verification (2017) (7)
T-depth Optimization for Fault-Tolerant Quantum Circuits (2019) (6)
Level assignment for displaying combinational logic (2001) (6)
Impacts of Creating Smart Everyday Objects on Young Female Students' Programming Skills and Attitudes (2020) (6)
ATLaS: Automatic Detection of Timing-based Information Leakage Flows for SystemC HLS Designs (2021) (6)
Applications of Evolutionary Computing: EvoWorkshops 2007 EvoCOMNET, EvoFIN, EvoIASP, EvoINTERACTION, EvoMUSART, EvoSTOC, and EvoTransLog, Valencia, Spain, ... Computer Science and General Issues) (2007) (6)
Comparative Study by Solving the Test Compaction Problem (2008) (6)
The complexity of error metrics (2018) (6)
Towards Unifying Localization and Explanation for Automated Debugging (2010) (6)
Exact Routing with Search Space Reduction (2003) (6)
Maximizing power state cross coverage in firmware-based power management (2019) (6)
Towards formal verification on the system level (2004) (6)
Determining cases of scenarios to improve coverage in simulation-based verification (2014) (6)
An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization (2015) (6)
Eliminating invariants in UML/OCL models (2012) (6)
Logic Synthesis for In-memory Computing Using Resistive Memories (2018) (6)
Process variations aware robust on-chip bus architecture synthesis for MPSoCs (2008) (6)
Efficient Implementation of Nearest Neighbor Quantum Circuits Using Clustering with Genetic Algorithm (2020) (6)
Determining Application-Specific Knowledge for Improving Robustness of Sequential Circuits (2019) (6)
Selection of efficient re-ordering heuristics for MDD construction (2001) (6)
Relation between OFDDs and FPRMs (1996) (6)
Synthesis of Reversible Circuits Using Decision Diagrams (2012) (6)
Verification for Field-coupled Nanocomputing Circuits (2020) (6)
A genetic algorithm for the construction of small and highly testable OKFDD-circuits (1996) (6)
Synthesis of optical circuits using binary decision diagrams (2017) (6)
Towards Dependability-Aware Design of Hardware Systems Using Extended Program State Machines (2011) (6)
Algorithms for Taylor expansion diagrams [IC design/verification applications] (2004) (6)
Performance driven optimization for MUX based FPGAs (2001) (6)
An Evolutionary Algorithm for Optimization of Pseudo Kronecker Expressions (2010) (6)
Automated and quality-driven requirements engineering (2014) (6)
An Examination of the NCV-|u1 > Quantum Library Based on Minimal Circuits (2015) (6)
Lazy-CSeq-SP: Boosting Sequentialization-Based Verification of Multi-threaded C Programs via Symbolic Pruning of Redundant Schedules (2015) (6)
Look What I Can Do: Acquisition of Programming Skills in the Context of Living Labs (2019) (6)
Grouping heuristics for word-level decision diagrams (1999) (6)
Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library (2016) (6)
A CANONICAL AND/EXOR FORM THAT INCLUDES BOTH THE GENERALIZED REED-MULLER FORMS AND KRONECKER REED-MULLER FORMS (2007) (6)
A method for approximate equivalence checking (2000) (6)
Automated Validation & Verification of UML/OCL Models Using Satisfiability Solvers (2018) (6)
Contradictory antecedent debugging in bounded model checking (2009) (6)
Modeling multi-valued circuits in SystemC* (2003) (6)
Creating hard problem instances in logic synthesis using exact minimization (1999) (6)
A framework for reversible circuit complexity (2014) (6)
HW/SW Co-Verification of a RISC CPU using Bounded Model Checking (2005) (6)
Minimization of BDDs using linear transformations based on evolutionary techniques (1999) (6)
Implementation of read-k-times BDDs on top of standard BDD packages (2001) (6)
Influencing parameters of evolutionary algorithms for sequencing problems (1997) (6)
Hardware/Software Co-Visualization on the Electronic System Level Using SystemC (2016) (6)
Behaviour Driven Development for Tests and Verification (2014) (6)
Towards Line-Aware Realizations of Expressions for HDL-Based Synthesis of Reversible Circuits (2015) (6)
Design Understanding by Automatic Property Generation (2004) (6)
A time optimal robust path-delay-fault self-testable adder (1992) (6)
SAT-based Calculation of Source Code Coverage for BMC (2006) (6)
Automatic debugging of System-on-a-Chip designs (2009) (5)
Applications of Evolutionary Computing, EvoWorkshops 2006: EvoBIO, EvoCOMNET, EvoHOT, EvoIASP, EvoINTERACTION, EvoMUSART, and EvoSTOC, Budapest, Hungary, April 10-12, 2006, Proceedings (2006) (5)
TLM protocol compliance checking at the Electronic System Level (2011) (5)
Multi-objective Synthesis of Quantum Circuits Using Genetic Programming (2018) (5)
On the impact of the synchronization constraint and interconnections in quantum-dot cellular automata (2020) (5)
Evolutionary Algorithms for VLSI CAD [Book Review] (1999) (5)
Debugging of Reversible Circuits Using pDDs (2013) (5)
Combining sequentialization-based verification of multi-threaded C programs with symbolic Partial Order Reduction (2019) (5)
Analyzing dependability measures at the Electronic System Level (2011) (5)
Satis ability Problems for Ordered Functional Decision Diagrams (1996) (5)
Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival (2008) (5)
Specialized Hardware for Implementation of Evolutionary Algorithms (2000) (5)
Verifying Dividers Using Symbolic Computer Algebra and Don't Care Optimization (2021) (5)
Pick the Right Edge Device: Towards Power and Performance Estimation of CUDA-based CNNs on GPGPUs (2021) (5)
Lower bounds for dynamic BDD reordering (2005) (5)
Logic Design Using Memristors: An Emerging Technology (2018) (5)
Variable reordering for shared binary decision diagrams using output probabilities (1999) (5)
Cluster-based Localization of IR-drop in Test Application considering Parasitic Elements (2019) (5)
Evolutionary Synthesis of Multiplexor Circuits under Hardware Constraints (2000) (5)
Guided lightweight Software test qualification for IP integration using Virtual Prototypes (2016) (5)
BioViz: An Interactive Visualization Engine for the Design of Digital Microfluidic Biochips (2017) (5)
Switching activity estimation of finite state machines for low power synthesis (2002) (5)
Reverse Engineering with Simulation Graphs (2015) (5)
Using a two-dimensional fault list for compact Automatic Test Pattern Generation (2009) (5)
Symbolic simulation using decision diagrams (1997) (5)
History-Based Dynamic Minimization During BDD Construction (1999) (5)
Using πDDs in the Design of Reversible Circuits (2012) (5)
Implementation and Visualization of a BDD Package in JAVA (2002) (5)
Optimization of sequential verification by history-based dynamic minimization of BDDs (2000) (5)
Reconfigurable TAP controllers with embedded compression for large test data volume (2017) (5)
Verifying Safety Properties of Robotic Plans Operating in Real-World Environments via Logic-Based Environment Modeling (2020) (5)
Hybrid Architecture for Embedded Test Compression to Process Rejected Test Patterns (2019) (5)
Hardware Project Management - What we Can Learn from the Software Development Process for Hardware Design? (2007) (5)
Multiply-Accumulate Enhanced BDD-Based Logic Synthesis on RRAM Crossbars (2020) (5)
System-Level Verification of Linear and Non-Linear Behaviors of RF Amplifiers using Metamorphic Relations (2021) (5)
Trust is good, control is better: Hardware-based instruction-replacement for reliable processor-IPs (2017) (5)
Acceleration of SAT-Based Iterative Property Checking (2005) (5)
Improved Circuit-to-CNF Transformation for SAT-based ATPG (2008) (5)
Word-level Decision Diagrams (1998) (5)
Computation of spectral information from logic netlists (2000) (5)
Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure (2013) (5)
Exact minimisation of Kronecker expressions for symmetric functions (1996) (5)
Approximate BDD Minimization by Weighted A. (2009) (5)
ComPRIMe: A Compiler for Parallel and Scalable ReRAM-based In-Memory Computing (2019) (5)
Experimental Studies on SMT-based Debugging (2008) (5)
Fault simulation in sequential multi-valued logic networks (1997) (5)
Formal verification meets robustness checking — Techniques and challenges (2010) (5)
Quality Assessment for Requirements based on Natural Language Processing (2014) (5)
On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults (2008) (5)
Optimization-based Test Scheduling for IEEE 1687 Multi-Power Domain Networks Using Boolean Satisfiability (2021) (5)
Satisfiability Problems for OFDDs (1996) (4)
Exact minimization of Kronecker expressions for symmetric functions (1996) (4)
Power Intent from Initial ESL Prototypes: Extracting Power Management Parameters* (2018) (4)
Dedicated synthesis for MZI-based optical circuits based on AND-inverter graphs (2017) (4)
Boosting SystemC-based Testbenches with Modern C++ and Coverage-Driven Generation (2015) (4)
Determining minimal testsets for reversible circuits using Boolean satisfiability (2011) (4)
Polynomial Formal Verification: Ensuring Correctness under Resource Constraints : (Invited Paper) (2022) (4)
Unintrusive aging analysis based on offline learning (2017) (4)
In-Memory Computing: The Integration of Storage and Processing (2019) (4)
On the Construction of Small Fully Testable Circuits with Low Depth (2007) (4)
Reduction of sizes of multi-valued decision diagrams by copy properties (2004) (4)
Co-synthesis of custom on-chip bus and memory for MPSoC architectures (2007) (4)
Semi-formal Cycle-Accurate Temporal Execution Traces Reconstruction (2017) (4)
A fast optimal robust path delay fault testable adder (1996) (4)
GateComp: Equivalence Checking in CVE (2001) (4)
Towards Self-explaining Intelligent Environments (2018) (4)
More than true or false: native support of irregular values in the automatic validation & verification of UML/OCL models (2017) (4)
One Additional Qubit is Enough: Encoded Embeddings for Boolean Components in Quantum Circuits (2019) (4)
Frame conditions in the automatic validation and verification of UML/OCL models: A symbolic formulation of modifies only statements (2017) (4)
Minimally Invasive HW/SW Co-debug Live Visualization on Architecture Level (2021) (4)
Efficient test generation with maximal crosstalk-induced noise using unconstrained aggressor excitation (2010) (4)
Post Synthesis-Optimization of Reversible Circuit using Template Matching (2020) (4)
Towards automatic scenario generation from coverage information (2013) (4)
Unlocking approximation for in-memory computing with Cartesian genetic programming and computer algebra for arithmetic circuits (2022) (4)
Avoiding False Negatives in Formal Verification for Protocol-Driven Blocks (2006) (4)
Mutation-based Compliance Testing for RISC-V (2021) (4)
Generation of optimal universal logic modules (1999) (4)
Design reuse by modularity: a scalable dynamical (re)configurable multiprocessor system (2000) (4)
Utilizing High-Level Information for Formal Hardware Verification (2001) (4)
Formal methods for emerging technologies (2015) (4)
Debugging Design Errors by Using Unsatisfiable Cores (2008) (4)
Technology Mapping for Single Target Gate Based Circuits Using Boolean Functional Decomposition (2015) (4)
Towards Polynomial Formal Verification of Complex Arithmetic Circuits (2022) (4)
Improving the Designs of Nearest Neighbour Quantum Circuits for 1D and 2D Architectures (2020) (4)
Synthesis of Reversible Circuits Using Conventional Hardware Description Languages (2018) (4)
Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL (2007) (4)
SymEx-VP: An open source virtual prototype for OS-agnostic concolic testing of IoT firmware (2022) (4)
OKFDD minimization by genetic algorithms with application to circuit design (1999) (4)
Requirement Phrasing Assistance Using Automatic Quality Assessment (2015) (4)
Effects of cell shapes on the routability of Digital Microfluidic Biochips (2017) (4)
ETDD-based synthesis of two-dimensional cellular arrays for multi-output incompletely specified Boolean functions (1999) (4)
XbNN: Enabling CNNs on Edge Devices by Approximate On-Chip Dot Product Encoding (2021) (4)
Bridging fault testability of BDD circuits (2005) (4)
Boolean function representation and spectral characterization using AND/OR graphs (2000) (4)
Enhancing robustness of sequential circuits using application-specific knowledge and formal methods (2017) (4)
ASCHyRO: Automatic Fault Localization of SystemC HLS Designs Using a Hybrid Accurate Rank Ordering Technique (2020) (4)
Re-Writing HDL Descriptions for Line-Aware Synthesis of Reversible Circuits (2016) (4)
Approximate Memory: Data Storage in the Context of Approximate Computing (2019) (4)
From Requirements and Scenarios to ESL Design in SystemC (2012) (4)
EXOR transform of inputs to design efficient two-level AND/EXOR adders (2000) (4)
Impact of NBTI on Increasing the Susceptibility of FinFET to Radiation (2019) (4)
Timing Arc based logic analysis for false noise reduction (2009) (4)
Change impact analysis for hardware designs from natural language to system level (2016) (4)
Towards verifying determinism of SystemC designs (2014) (4)
Anwendungsbezogene Analyse der Robustheit von Digitalen Schaltungen André Sülflow Stefan Frehse Görschwin Fey (2009) (4)
Manipulation Algorithms for K*BMDs (1997) (4)
The complexity of the inclusion operation on OFDD's (1998) (4)
Combining Machine Learning and Formal Techniques for Small Data Applications - A Framework to Explore New Structural Materials (2020) (4)
On the Exact Minimization of Path-Related Objective Functions for BDDs (2005) (4)
Ordered Kronecker functional decision diagrams und ihre Anwendung (1996) (4)
An integrated approach for combining BDD and SAT provers (2006) (4)
Decision diagram optimization using copy properties (2002) (4)
Quasi-exact BDD minimization using relaxed best-first search (2005) (3)
Exact minimisation of path-related objective functions for binary decision diagrams (2006) (3)
Test generation for (sequential) multi-valued logic networks based on genetic algorithm (1998) (3)
Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow (2008) (3)
Improving Evolutionary Algorithms by Enhancing an Approximative Fitness Function through Prediction Intervals (2021) (3)
An evolutionary approach to reversible logic synthesis using output permutation (2013) (3)
Improving SAT Solving Using Monte Carlo Tree Search-Based Clause Learning (2019) (3)
Depth Optimized Synthesis of Symmetric Boolean Functions (2021) (3)
Identifying a Subset of SystemVerilog Assertions for Efficient Bounded Model Checking (2009) (3)
Minimization of 2-level AND / XOR Expressionsusing Ordered Kronecker Functional Decision Diagrams (2007) (3)
Towards Automatic Hardware Synthesis from Formal Specification to Implementation (2020) (3)
Constraint-Based Pattern Retargeting for Reducing Localized Power Activity During Testing (2018) (3)
Towards an Automatic Approach for Restricting UML/OCL Invariability Clauses (2015) (3)
RVX - A Tool for Concolic Testing of Embedded Binaries Targeting RISC-V Platforms (2020) (3)
Emerging Circuit Technologies: An Overview on the Next Generation of Circuits (2018) (3)
Complete Formal Verification of Multi Core Embedded Systems Using Bounded Model Checking (2006) (3)
Towards Dynamic Execution Environment for System Security Protection Against Hardware Flaws (2018) (3)
Negation and duality in reduced ordered binary decision diagrams (1997) (3)
Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability (2016) (3)
Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm (2016) (3)
Testability of circuits derived from lattice diagrams (2000) (3)
Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen (2010) (3)
Cone of Influence Analysis at the Electronic System Level Using Machine Learning (2013) (3)
Too Much Knowledge Hurts: Acceleration of Genetic Programs for Learning Heuristics (2001) (3)
Natural Language Based Power Domain Partitioning (2018) (3)
ASNet: Introducing Approximate Hardware to High-Level Synthesis of Neural Networks (2020) (3)
VIP-VP: Early Validation of SoCs Information Flow Policies using SystemC-based Virtual Prototypes (2021) (3)
PolyCleaner (2018) (3)
RobuCheck: A Robustness Checker for Digital Circuits (2010) (3)
System Level Verification of Phase-Locked Loop using Metamorphic Relations (2021) (3)
Formal verification of modular multipliers using symbolic computer algebra and boolean satisfiability (2022) (3)
One-pass Synthesis for Field-coupled Nanocomputing Technologies (2021) (3)
Proceedings of the 2008 conference on Applications of evolutionary computing (2008) (3)
An improved heuristic technique for nearest neighbor realization of quantum circuits in 2D architecture (2020) (3)
History-based dynamic BDD minimization (2001) (3)
ToPoliNano and fiction: Design Tools for Field-coupled Nanocomputing (2020) (3)
Formal Verification of SystemC-based Cyber Components (2017) (3)
Verifying next generation electronic systems (2017) (3)
Self-explaining Digital Systems: Technical View, Implementation Aspects, and Completeness (2019) (3)
An Efficient Nearest Neighbor Design for 2D Quantum Circuits (2019) (3)
Towards Increasing Test Compaction Abilities of SAT-based ATPG through Fault Detection Constraints (2012) (3)
BDD-based verification of scalable designs (2003) (3)
GAME-HDL: Implementation of Evolutionary Algorithms Using Hardware Description Languages (2003) (3)
Ed&tc '97 on Cd-rom Fast and Ecient Construction of Bdds by Reordering Based Synthesis (1997) (3)
(ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-Based Countermeasures on FPGAs (2019) (3)
Domain-driven Correlation-aware Recombination and Mutation Operators for Complex Real-world Applications (2021) (3)
Efficient Techniques to Strongly Enhance the Virtual Prototype Based Design Flow (2020) (3)
Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging (2022) (3)
Approximate Hardware Generation Using Formal Techniques (2018) (3)
Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^{m}) in SystemC (2007) (3)
Multi-output timed Shannon circuits (2002) (3)
Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level (2021) (3)
FormED : A Formal Environment for Debugging (2009) (3)
Efficient Functional Diagnosis for Synchronous Sequential Circuits Based on And/or Graphs (1997) (3)
SAT-Hard: A Learning-Based Hardware SAT-Solver (2019) (3)
On the implementation of an efficient performance driven generator for conditional-sum-adders (1993) (3)
Efficient dynamic minimization of word-level DDs based on lower bound computation (2000) (3)
Optimal symmetry detection for OKFDDs (2000) (3)
A genetic algorithm for decomposition type choice in OKFDDs (1995) (3)
Minimization of ordered pseudo Kronecker decision diagrams (2000) (3)
ATPG Based on Boolean Satisfiability (2012) (3)
Placement and routing optimization for circuits derived from BDDs (2004) (3)
Toward Optical Probing Resistant Circuits: A Comparison of Logic Styles and Circuit Design Techniques (2022) (3)
Tabular Techniques for MV Logic (2001) (3)
In-Memory Computing (2019) (3)
Bail on Balancing: An Alternative Approach to the Physical Design of Field-Coupled Nanocomputing Circuits (2020) (3)
Minimization of OKFDDs by Genetic Algorithms (1996) (3)
Ensuring Correctness of Next Generation Devices: From Reconfigurable to Self-Learning Systems (2019) (3)
Analyzing Frame Conditions in UML/OCL Models - Consistency Equivalence and Independence (2018) (3)
Early Validation of SoCs Security Architecture Against Timing Flows Using SystemC-based VPs (2021) (3)
Towards Dialog Systems for Assisted Natural Language Processing in the Design of Embedded Systems ( Invited Paper ) (2012) (3)
On the application of local circuit transformations with special emphasis on path delay fault testability (1995) (3)
MODELING AND FORMAL VERIFICATION OF COUNTING HEADS FOR RAILWAYS (2008) (3)
Toward RISC-V CSR Compliance Testing (2021) (3)
OR-Inverter Graphs for the Synthesis of Optical Circuits (2017) (3)
Polynomial Formal Veri cation of Multipliers (1996) (3)
Formal Techniques (2021) (2)
A Hardware-based Evolutionary Algorithm with Multi-Objective Optimization Operators for On-Chip Transient Fault Detection (2022) (2)
Generating and checking control logic in the HDL-based design of reversible circuits (2016) (2)
Minimization of Word-Level Decision Diagrams (2002) (2)
Polynomial Formal Veriﬁcation of Arithmetic Circuits (2022) (2)
Nearest Neighbor Mapping of Quantum Circuits to Two-Dimensional Hexagonal Qubit Architecture (2022) (2)
Early Error Detection (2010) (2)
Effect of Negative Control Lines on the Exact Synthesis of Reversible Circuits (2013) (2)
Synchronized Debugging across Different Abstraction Levels in System Design ? (2013) (2)
A Logic for Cardinality Constraints (Extended Abstract) (2014) (2)
Polynomial Formal Verification of Area-efficient and Fast Adders (2021) (2)
GREEDY IIP: partitioning large graphs by greedy iterative improvement (2001) (2)
Formal Verification on the Word Level using SAT-like Proof Techniques (2007) (2)
Combining SWAPs and Remote CNOT Gates for Quantum Circuit Transformation (2021) (2)
Automated Detection of Spatial Memory Safety Violations for Constrained Devices (2022) (2)
Initial Ideas for Automatic Design and Verification of Control Logic in Reversible HDLs - Work in Progress Report (2016) (2)
Evaluation of (power) side-channels in cryptographic implementations (2019) (2)
RevVis: Visualization of Structures and Properties in Reversible Circuits (2014) (2)
Measurement and Evaluation of Calorimetric Descriptors for the Suitability for Evolutionary High-Throughput Material Development (2019) (2)
Exact BDD Minimization for Path-Related Objective Functions (2005) (2)
Template-based mapping of reversible circuits to IBM quantum computers (2022) (2)
Efficient Design-Flow for Counting Heads (2006) (2)
ReCoFused partial reconfiguration for secure moving-target countermeasures on FPGAs (2020) (2)
Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing (2021) (2)
Grammar-based program generation based on model finding (2013) (2)
A Codeword-based Compactor for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks (2021) (2)
Application III: Design Space Exploration (2020) (2)
Applications of Evolutionary Computing: Evoworkshops: EvoBIO, EvoCOMNET, EvoHot, EvoIASP, EvoMUSART, and EvoSTOC (Lecture Notes in Computer Science) (2005) (2)
Design Automation for Field-Coupled Nanotechnologies (2020) (2)
Automatic Fault Localization for SystemC TLM Designs (2010) (2)
Atomic distributions in crystal structures solved by Boolean satisfiability techniques (2016) (2)
Experimental Studies on Test Pattern Generation for BDD Circuits (2004) (2)
Verification of Embedded Systems Using Modeling and Implementation Languages (2012) (2)
Robustness and usability in modern design flows (2010) (2)
Adaptive simulation with Virtual Prototypes in an open-source RISC-V evaluation platform (2021) (2)
Design Modification for Polynomial Formal Verification (2022) (2)
Generic Implementation of Multi-Valued Logic Decision Diagram Packages (2005) (2)
Design for Testability, Debug and Reliability (2021) (2)
SAT-based Automatic Test Pattern Generation (2008) (2)
Reliability Improvements for Multiprocessor Systems by Health-Aware Task Scheduling (2018) (2)
Towards Proving TLM Properties with Local Variables ∗ (2011) (2)
Synthesis of Asymptotically Optimal Adders for Multiple-Valued Logic (2021) (2)
Documentation Driven Software Development for Embedded Systems (2007) (2)
Stuck-At-Fault Testability of SPP Three-Level Logic Forms (2003) (2)
Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion∗ (2021) (2)
Self-Explaining Digital Systems - Some Technical Steps (2019) (2)
Efficient (Non-)Reachability Analysis of Counterexamples (2004) (2)
MetaSMT: a unified interface to SMT-LIB2 (2014) (2)
PREASC (2020) (2)
Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs (2008) (2)
Advanced Environment Modeling and Interaction in an Open Source RISC-V Virtual Prototype (2022) (2)
Introduction to the Special Issue on Design Automation for Quantum Computing (2022) (2)
Equivalence Checking of System-Level and SPICE-Level Models of Linear Analog Filters (2022) (2)
Towards Fully Automatic Synthesis of Embedded Software (2010) (2)
ML-based Power Estimation of Convolutional Neural Networks on GPGPUs (2022) (2)
Parallel Computing of Graph-based Functions in ReRAM (2022) (2)
Work-in-Progress: Early Power Estimation of CUDA-based CNNs on GPGPUs (2021) (2)
Early Performance Estimation of Embedded Software on RISC-V Processor using Linear Regression (2022) (2)
An ant colony based mapping of quantum circuits to nearest neighbor architectures (2021) (2)
Towards Generation of a Programmable Power Management Unit at the Electronic System Level (2020) (2)
Synthesis for Logic-in-Memory Computing Using RRAM (2019) (2)
Quality Assessment of RFET-based Logic Locking Protection Mechanisms using Formal Methods (2022) (2)
Recurrence Relations Revisited: Scalable Verification of Bit Level Multiplier Circuits (2015) (2)
Structural heuristics for SAT-based ATPG (2009) (2)
Formal Verification of Approximate Sequential Circuits (2018) (2)
SELF-PRACTICING OF LOGIC CIRCUITS THROUGH MOBILE DEVICES: LECTURERS’ AND STUDENTS’ PERCEPTIONS (2017) (2)
A Hybrid Embedded Multichannel Test Compression Architecture for Low-Pin Count Test Environments in Safety-Critical Systems (2019) (2)
An improved gate library for logic synthesis of optical circuits (2016) (2)
On the sensitivity of BDDs with respect to path-related objective functions (2006) (2)
Äquivalenzvergleich digitaler Schaltungen im industriellen Umfeld (Equivalence Checking of Digital Circuits in an Industrial Environment) (2001) (2)
Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime (2020) (2)
Early Verification of ISA Extension Specifications using Deep Reinforcement Learning (2020) (2)
Coverage of OCL Operation Specifications and Invariants (2015) (2)
Robust Tests for Transition Faults with Long Propagation Paths Using Boolean Satisfiability (2008) (2)
Towards VHDL-Based Design of Reversible Circuits - Work in Progress Report (2017) (2)
Minimization of Transitions by Complementation and Resequencing using Evolutionary Algorithms (2003) (2)
Systematic RISC-V based Firmware Design⋆ (2019) (2)
Exploration of Sequential Depth by Evolutionary Algorithms (2003) (2)
Code is Ethics — Formal Techniques for a Better World (2019) (2)
Behavior Driven Development for Tests and Verification (2015) (2)
Yise - a novel framework for boolean networks using y-inverter graphs (2017) (2)
Incorporating User Preferences in Many-Objective Optimization using Relation Epsilon-Preferred (2018) (2)
Seroepidemiologische Studie zur Überwachung der Diphtherie-Immunität und Diphtherie-Schutz-impfung im Freistaat Sachsen 1996 (1998) (2)
Formale Verifikation von LTL-Formeln für SystemC-Beschreibungen (2003) (2)
Effiziente Erfüllbarkeitsalgorithmen für die Generierung von TestmusternEfficient Satisfiability Solving Algorithms for Test Pattern Generation (2009) (2)
Formale Methoden für Alle (2014) (2)
Verbesserte SAT basierte Fehlerdiagnose durch Widerspruchanalyse (2007) (2)
Verbesserung der Fehlersuche in inkonsistenten formalen Modellen (Erweiterte Zusammenfassung) (2015) (2)
RevSCA (2019) (2)
Formaler Nachweis der Fehlertoleranz von Schaltkreisen (2008) (2)
Evolutionary algorithm approach for symbolic FSM traversals (2001) (2)
Polynomial Formal Verification of Approximate Adders (2022) (2)
A Memory-Upscaled Boolean Satisﬁability Solver for Complex On-Chip Self-Veriﬁcation Tasks (2022) (1)
Unified HW/SW Coverage: A Novel Metric to Boost Coverage-guided Fuzzing for Virtual Prototype based HW/SW Co-Verification (2022) (1)
ProACt: Hardware Architecture for Cross-Layer Approximate Computing (2018) (1)
RISC-V Processor Veriﬁcation with Coverage-guided Aging * (2022) (1)
Method for Construction of Recursive Algorithms for Reed- Muller-Fourier Polarity Matrices Calculation (2004) (1)
Model-Based Specification and Refinement for Cyber-Physical Systems (2016) (1)
Automatic Methods for the Refinement of System Models: From the Specification to the Implementation (2016) (1)
Towards Quantification and Visualization of the Effects of Concretization During Concolic Testing (2022) (1)
The Scale4Edge RISC-V Ecosystem (2022) (1)
Modeling for Explainability: Ethical Decision-Making in Automated Resource Allocation (2021) (1)
In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes (2021) (1)
Building Fast Multi Agent Systems Using Hardware Design Languages for High-Throughput Systems (2018) (1)
The SyReC hardware description language: Enabling scalable synthesis of reversible circuits (2013) (1)
Automatic Design of Microfluidic Devices: An Overview of Platforms and Corresponding Design Tasks (2019) (1)
Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing (2022) (1)
Enhanced Virtual Prototyping for Heterogeneous Systems (1)
Choosing the right technique for the right restriction – a domain-speciﬁc approach for enforcing search-space restrictions in evolutionary algorithms (2022) (1)
Equivalence Checking of System-Level and SPICE-Level Models of Linear Circuits (2022) (1)
Published at Workshop on Post Binary Ultra-Large Scale Integration (ULSI‘96), Santiago de Compostela A Note on Symbolic Simulation using Decision Diagrams (2007) (1)
Nano Security: From Nano-Electronics to Secure Systems (2021) (1)
Technische Dokumentation von Soft- und Hardware in Eingebetteten Systemen (Technical Documentation of Soft- and Hardware in Embedded Systems) (2007) (1)
IMAGIN: Library of IMPLY and MAGIC NOR-Based Approximate Adders for In-Memory Computing (2022) (1)
Isolating Failure Causes (2010) (1)
Decision diagrams for the design of reversible and quantum circuits (2018) (1)
Exploiting reversibility in the complete simulation of reversible circuits (2013) (1)
Error Diagnosis in Sequential Multi-Valued Logic Networks (2007) (1)
Funktionale Abdeckungsanalyse von C-Programmen (2014) (1)
Visualized SystemC Debugging (2007) (1)
Towards a model-based verification methodology for Complex Swarm Systems (Invited paper) (2016) (1)
Improving the Quality of Bounded Model Checking by Means of Coverage Estimation (2007) (1)
System Level Veriﬁcation of Analog/Mixed-Signal Systems using Metamorphic Relations (2022) (1)
Debugging Contradictory Constraints in Constraint-Based Random Simulation (2008) (1)
Using games for benchmarking and representing the complete solution space using symbolic techniques (2003) (1)
CoMIC: Complementary Memristor based in-memory computing in 3D architecture (2022) (1)
ALF: a fitness-based artificial life form for evolving large-scale neural networks (2021) (1)
Checking integrity during dynamic reordering in decision diagrams (1999) (1)
Integer Overflow Detection in Hardware Designs at the Specification Level (2020) (1)
Reversible computation (2015) (1)
Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking (2008) (1)
Virtual Prototype driven Design, Implementation and Evaluation of RISC-V Instruction Set Extensions (2022) (1)
Preserving Design Hierarchy Information for Polynomial Formal Verification (2022) (1)
On Timing-Aware ATPG using Pseudo-Boolean Optimization (2011) (1)
Technische Dokumentation von Soft- und Hardware-Systemen: Die vergessene Welt (2006) (1)
Adapting mutation and recombination operators to range-aware relations in real-world application data (2022) (1)
Formale Verifikation des Befehlssatzes eines SystemC modellierten Mikroprozessors (2005) (1)
VLSI CAD and the integration of evolutionary techniques (1999) (1)
Probabilistic IP verification (1999) (1)
Generation of Verified Programs for In-Memory Computing (2022) (1)
Notations and Definitions (1998) (1)
Property-Driven Timestamps Encoding for Timeprints-Based Tracing and Monitoring (2019) (1)
Modeling and proving functional completeness in formal verification of counting heads (2008) (1)
Enhanced Embedded Test Compression Technique For Processing Incompressible Test Patterns (2019) (1)
Disziplinübergreifendes Modell zur Ausbildung von Forschungsdatenmanagement und Data Science Kompetenzen: „Data Train – Training in Research Data Management and Data Science“ (2021) (1)
Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challenges (2021) (1)
Minimization of OPKFDDs using genetic algorithms (2001) (1)
Generierung von OCL-Ausdrücken aus natürlichsprachlichen Beschreibungen (2013) (1)
Development of Consistent Formal Models (2015) (1)
Early power estimation of CUDA-based CNNs on GPGPUs: work-in-progress (2021) (1)
Exakte BDD Minimierung mit Fehlerschranke für den Einsatz im Approximate Computing (2017) (1)
UMLAUT: Synthesis of Natural Language from Constrained UML Models (2018) (1)
Embedding of Irreversible Functions (2010) (1)
Power-aware test scheduling framework for IEEE 1687 multi-power domain networks using formal techniques (2022) (1)
Formale Verifikation des Befehlssatzes eines SystemC Mikroprozessors (2005) (1)
Decision diagram based minimization of pseudo Kronecker expressions (2000) (1)
Automated Debugging-Aware Visualization Technique for SystemC HLS Designs (2021) (1)
Proving Completeness of Properties in Formal Verification of Counting Heads for Railways (2007) (1)
System-Level Verification (2010) (1)
Self-Explanation in Systems of Systems (2022) (1)
Verification Runtime Analysis: Get the Most Out of Partial Verification (2020) (1)
Report on Reasoning Engines and Dynamic Techniques (2011) (1)
Coverage-Directed Stimuli Generation for Characterization of RF Amplifiers (2020) (1)
An Automated Approach for Generating and Checking Control Logic for Reversible Hardware Description Language-Based Designs (2017) (1)
Circuits and Testing (2012) (1)
MircoRV32: an open source RISC-V cross-level platform for education and research (2021) (1)
HotAging — Impact of Power Dissipation on Hardware Degradation (2019) (1)
Intelligent Umgeben: Ausgewählte Einblicke in 10 Jahre Bremen Ambient Assisted Living Lab (2020) (1)
A Framework for Quasi-exact Optimization Using Relaxed Best-First Search (2006) (1)
Testing integrated circuits (2014) (1)
Towards Automated Refinement of TLM Properties to RTL (2018) (1)
Automatic Design of Microfluidic Devices (2018) (1)
Text statt C++: Automatisierung des Systementwurfs mit Hilfe natürlicher Sprachverarbeitung (2013) (1)
Test Scheduling Optimization Model for IEEE 1687 Multi-Power Domain Networks Using Boolean Satisfiability (2021) (1)
Verification and evaluation of site occupancies using Boolean satisfiability techniques (2013) (1)
Finding Optimal Implementations of Non-native CNOT Gates Using SAT (2021) (1)
A Two-Stage SAT-based ATPG Approach with Reduced Switching Activity (2009) (1)
An ILP-based Global Optimum Test Scheduler for IEEE 1687 Multi-Power Domain Networks (2022) (1)
Polynomial-Time Formal Verification of Adder Circuits for Multiple-Valued Logic (2022) (1)
Das Bremen Ambient Assisted Living Lab und darüber hinaus - Intelligente Umgebungen, smarte Services und Künstliche Intelligenz in der Medizin für den Menschen (2022) (1)
A Formal Interpretation of UML/OCL (2018) (1)
Efficient machine learning through evolving combined deep neural networks (2020) (1)
Pin-Aware Routing and Extensions (2018) (1)
Divider Verification Using Symbolic Computer Algebra and Delayed Don't Care Optimization (2022) (1)
Polynomial Formal Verification of Approximate Functions (2022) (1)
Verzahnung von Data Stewardship und Data Science – Wege und Perspektiven (2021) (1)
Extensions to the Reversible Hardware Description Language SyReC (2017) (1)
LiM-HDL: HDL-Based Synthesis for In-Memory Computing (2022) (1)
An effective fault ordering heuristic for SAT-based dynamic test compaction techniques (2014) (1)
FAMCroNA: Fault Analysis in Memristive Crossbars for Neuromorphic Applications (2022) (1)
(Quasi-) linear path delay fault tests for adders (1997) (1)
RISC-V AMS VP: An Open Source Evaluation Platform for Cyber-Physical Systems (2021) (1)
Simulation-based Verification of SystemC-based VPs at the ESL (2022) (1)
Reversible Computation An Alternative Computation Paradigm for Low Power Applications (2015) (1)
A Codeword-based Compaction Technique for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks (2018) (1)
VisSAT: Visualization of SAT Solver Internals for Computer Aided Hardware Verification (2014) (1)
Controlling the memory during manipulation of word-level decision diagrams (2005) (1)
Low Power Optimization Techniques for BDD Mapped Finite State Machines (2002) (1)
Clustering-Guided SMT(LRA) Learning (2020) (1)
Symbolic Simulation of Algorithms Specified in HDL (2002) (1)
Generation and Validation of Frame Conditions in Formal Models (2018) (1)
Exact Routing for MicroElectrode-Dot-Array Digital Microfluidic Biochips (2016) (1)
Towards a Model-Based Verification Methodology for Complex Swarm Systems (2016) (1)
Law-based Verication for Complex Swarm Systems (2012) (1)
Application of a hardware synthesis technique for database query optimization (2001) (1)
Logic Synthesis for Hybrid CMOS-ReRAM Sequential Circuits (2019) (1)
Performance Aspects of Correctness-oriented Synthesis Flows (2021) (1)
SAT-based Key Determination Attack for Improving the Quality Assessment of Logic Locking Mechanisms (2022) (1)
Information Storage: A Multidisciplinary Perspective (2020) (1)
Temporal Tracing of On-Chip Signals using Timeprints (2019) (1)
Symbolic Error Metric Determination for Approximate Computing (2016) (1)
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory (2019) (1)
Formal Analysis Techniques : A Basis for High-Quality Designs ( Invited Talk ) (2011) (1)
Minimization of Decision Diagrams: Classical Methods (1998) (1)
An Approach to Reversible Logic Synthesis Using Input and Output Permutations (2014) (1)
SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification (2022) (0)
An Open-Source RISC-V Evaluation Platform (2020) (0)
Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen in SystemC (An Approach for Formal Verification of Circuits in SystemC) (2003) (0)
The Boolean Domain (2001) (0)
Unlocking Sneak Path Analysis in Memristor Based Logic Design Styles (2022) (0)
Formal verification: current use and future perspectives (2002) (0)
Computer Aided Design and Test: BDDs vs. SAT (2001) (0)
Parallel simulation and verification [Session 5] (2014) (0)
Implementation of WLDDs (2000) (0)
Clustering-Guided SMT($\mathcal {L\!R\!A}$) Learning (2020) (0)
Minimization of the ExpectedPath Length in BDDsBasedon Local Changes (2003) (0)
09461 Abstracts Collection - Algorithms and Applications for Next Generation SAT Solvers (2009) (0)
Minimization of DDs (2000) (0)
IP3 Interactive Presentations (2019) (0)
Session details: Tutorial: Polynomial Formal Verification: Ensuring Correctness under Resource Constraints (2022) (0)
Verification for Autonomous Underwater Systems (2019) (0)
ANN-based Performance Estimation of Embedded Software for RISC-V Processors (2022) (0)
SELFIE – Self-Verification of Electronic Systems (2019) (0)
Languages, Design Methods, and Tools for Electronic System Design: Selected Contributions from FDL 2015 (2016) (0)
Multiple-Valued Logic (2009) (0)
Feed-Forward learning algorithm for resistive memories (2022) (0)
Enhanced Reliability Using Formal Techniques (2021) (0)
A Genetic Algorithm for the Minimization of OPKFDDs (2002) (0)
Symbolic Fault Injection for Plan-based Robotics (2022) (0)
Lower Bounds in Exact BDDMinimization (2003) (0)
Virtual Prototype based Analysis of Neural Network Cache Behavior for Tiny Edge Device (2022) (0)
Synthesis of Reversible Logic (2010) (0)
Optimization and Complexity Analysis on the Mapping Level (2016) (0)
. Formal Verification (2003) (0)
A Class of Polynomially Verifiable Circuits of Logarithmic Depth (2023) (0)
Impact of sneak paths on in-memory logic design in memristive crossbars (2023) (0)
Fuzzing Embedded Binaries leveraging SystemC-based Virtual Prototypes? (2020) (0)
Polynomial Formal Verification of General Tree-Like Circuits (2022) (0)
A Tight Lower Bound for Dynamic BDD Reordering (2004) (0)
A Case Study: Two-Level AND/EXOR Minimization (1998) (0)
W 06 The 2 nd International Workshop on Optical / Photonic Interconnects for Computing Systems ( OPTICS Workshop ) (2019) (0)
Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - a RISC-V Case Study (2023) (0)
Towards Lightweight Satisfiability Solvers for Self-Verification ( Invited Paper ) (2017) (0)
A Symbolic Formulation for Models (2018) (0)
SWORD v 0 . 2 – Module-based SAT Solving (2008) (0)
BioViz: An Interactive Visualization Engine for Microfluidic Biochips (2016) (0)
Behaviour Driven Development for Hardware Design (2018) (0)
Technology Dependent Synthesis (2002) (0)
BDD Optimization and Approximation: A Multi-criteria Approach (2019) (0)
Computation of Spectral Coefficients (2001) (0)
A Multi-Layer Detailed Routing Approach based onEvolutionary (1997) (0)
Evaluation of crystal structures with partial occupancies using Boolean satisfiability techniques in STRUPLOX (2019) (0)
Sympathy-MV: Fast exact minimization of fixed polarity multi-valued linear expressions (1997) (0)
cucumber-verilog: Behavior Driven Development for Circuit Design and Verification (2014) (0)
Hardware / Software Co-Visualization on the Electronic System Level using SystemC ( Embedded Tutorial ) (2016) (0)
Können wir uns in einer Welt voller Technik noch erholen? (2021) (0)
EDDY (2023) (0)
Introduction (2019) (0)
Wie sage ich es meinem Computer (2017) (0)
Alles ist logisch (2017) (0)
Der h2-lndex: Zur vermessenen Vermessung der wissenschaftlichen Welt (2014) (0)
Wie lernen wir richtig? (2021) (0)
KI-gestützte Optimierung repetitiver Prozesse – Eine Kodierungstechnik für repetitive Prozesse in der evolutionären Optimierung (2023) (0)
Optimizations and Complexity Analysis on the Reversible Level (2016) (0)
Conclusion (2020) (0)
Polynomial Formal Veriﬁcation of Approximate Adders (2022) (0)
Routing (2018) (0)
Introduction (2018) (0)
Methoden Und Beschrei Bungssprachen Zur Modellierung Und Verifikation Von Schaltungen Und Systemen Session: Verilikation 1 10 a Re-use Methodology Lor Soc Protocol Compliance Verilication Session: Verifikation 3 12 Using Implications for Optimizing State Set Representations of Linear Hybrid 13 Symbo (2009) (0)
Introduction (2021) (0)
Bin ich selbst ein Nerd? (2021) (0)
Multi-Objective Optimization in EvolutionaryAlgorithms Using Satis ability (1999) (0)
Weitere Ansätze mit Decision Diagrams (1998) (0)
Preliminaries (2020) (0)
Introduction (2018) (0)
Wie sicher brauchen wir die Welt? (2021) (0)
ATLaS (2021) (0)
Können Computer besser denken als Menschen? (2021) (0)
Einfluss von Zellformen auf das Routing von Digital Microfluidic Biochips (2017) (0)
Validation of Firmware-Based Power Management using Virtual Prototypes (2020) (0)
Fehlereffektsimulation mittels virtueller Prototypen (2015) (0)
Wohin entwickelt sich die Technologie? (2021) (0)
Ist die Welt heute noch zu verstehen? (2021) (0)
Background (2020) (0)
Conclusion (2020) (0)
Introduction (2020) (0)
Introduction (2020) (0)
Darstellungsgröße von Decision Diagrams (1998) (0)
Zu guter Letzt... (2021) (0)
Applications of Evolutionary Computing: EvoWorkshops 2006: EvoBIO, EvoCOMNET, EvoHOT, EvoIASP, EvoINTERACTION, EvoMUSART, and EvoSTOC, Budapest, Hungary, ... (Lecture Notes in Computer Science) (2006) (0)
3D Visualization of Symbolic Execution Traces (2022) (0)
Background (2018) (0)
Preliminaries (2018) (0)
Ausblick und weitere Anwendungen (1998) (0)
Von der (Rechen-)Aufgabe zum Schaltplan (2017) (0)
Background (2019) (0)
0 und 1 ist nicht genug (2017) (0)
Wie abhängig sind wir von der modernen Technik? (2021) (0)
Noch analog oder lebst Du schon? (2021) (0)
Conclusions (2019) (0)
ALF (2021) (0)
Wie kommunizieren wir miteinander? (2021) (0)
Wohin die Reise geht: aktuelle Entwicklungen und visionäre Konzepte (2017) (0)
Fast and Exact is Doable: Polynomial Algorithms in Test and Verification (2022) (0)
MircoRV32 (0)
Pin Assignment (2018) (0)
Integrating Debugging and Coverage Analysis (2013) (0)
MARADIV: Library of MAGIC based Approximate Restoring Array Divider Benchmark Circuits for In-Memory Computing Using Memristors (2023) (0)
One-Pass Synthesis (2021) (0)
High-Level Debugging and Exploration (2010) (0)
EXACT MINIMIZATION (0)
Change Management using CHIMPANC (2016) (0)
Towards System-level Assertions for Heterogeneous Systems (cid:63) (2022) (0)
A method for validation of simulation results of a system, and based on it equivalence comparison of digital circuits (2001) (0)
Integrated Circuits (2021) (0)
Combining Various Meta-Models for the Generation of Control Structures in Hardware (2012) (0)
Learning about the Design (2010) (0)
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes: Preface (2007) (0)
Optimizations and Complexity Analysis on the Quantum Level (2016) (0)
Formal Verification and Debugging (2010) (0)
NLP-Assisted Model Generation (2015) (0)
EDDY: A Multi-Core BDD Package With Dynamic Memory Management and Reduced Fragmentation (2023) (0)
Incorporating user preferences in many-objective optimization using relation ε-preferred (2014) (0)
Acknowledgments to Reviewers (1998) (0)
Change Management for Hardware Designers From Natural Language to Hardware Designs (2015) (0)
ICCAD 2019 Executive Committee (2019) (0)
Embedded Compression Architecture for Test Access Ports (2021) (0)
Synthesis Techniques for Approximation Circuits (2018) (0)
Characteristics of Problem Instances (1998) (0)
Integration into Industrial Flow (2009) (0)
fiction: A Holistic Open-Source Framework (2021) (0)
Simulation-Based Debugging of Formal Environment Models* (2022) (0)
Improved Circuit-to-CNF Conversion (2009) (0)
Definition of the Diagnostic Model (2011) (0)
Coverage-Guided Testing for Scalable Virtual Prototype Verification (2020) (0)
Unlocking High Resolution Arithmetic Operations within Memristive Crossbars for Error Tolerant Applications (2022) (0)
Exact Placement and Routing (2021) (0)
Specification-based Symbolic Execution for Stateful Network Protocol Implementations in the IoT (2023) (0)
Algorithmen für Decision Diagrams (1998) (0)
Design and Synthesis of Reversible Circuits using Hardware Description Languages (2015) (0)
Verification of Embedded Software Binaries using Virtual Prototypes (2020) (0)
Re-utilizing Verification Results of UML/OCL Models (2018) (0)
Design Understanding Methodology (2020) (0)
Keynotes: Towards Self-Explaining Digital Systems: A Design Methodology for the Next Generation (2018) (0)
Embedded Multichannel Test Compression for Low-Pin Count Test (2021) (0)
TERNARY AND QUATERNARY LATTICE DIAGRAMS FOR SYNTHESIS LINEARLY-INDEPENDENT LOGIC, MULTIPLE-VALUED LOGIC, AND ANALOG (1997) (0)
Minimization Using Symmetries (1998) (0)
Verification of Vertical Refinement (2017) (0)
Extraction of a Relation for Vertical Refinement (2017) (0)
Negation and Duality in Reduced Ordered Binary Decision st (1997) (0)
A Formal Repair Environment for Simple C Version 1 . 0 (2013) (0)
Towards Neural Hardware Search: Power Estimation of CNNs for GPGPUs with Dynamic Frequency Scaling (2022) (0)
Mapping Quantum Circuits to 2-Dimensional Quantum Architectures (2022) (0)
Combining sequentialization-based verification of multi-threaded C programs with symbolic Partial Order Reduction (2019) (0)
Conclusion and Outlook (2021) (0)
Session details: Formal methods for hardware and software verification (2008) (0)
Interactive Visualization of ESL Designs (2015) (0)
SAT-Based ATPG (2009) (0)
Learning Heuristics by Evolutionary Algorithmswith Variable Size RepresentationNicole (1997) (0)
SWORD v 1 . 0 (2009) (0)
Published at Reed-muller 97, Oxford Reordering Based Synthesis (1997) (0)
Logic Design using Memristors : An Emerging Technology ( Embedded Tutorial ) (2018) (0)
Early SoCs Information Flow Policies Validation using SystemC-based Virtual Prototypes at the ESL (2022) (0)
Post-Production Test Strategies for Approximation Circuits (2018) (0)
Error Metric Computation for Approximate Combinational Circuits (2018) (0)
Genetic Algorithm for the Construction of Small and Highly (2007) (0)
Path Delay Fault Model (2012) (0)
Scalable Placement and Routing (2021) (0)
Bit-level Decision Diagrams (1998) (0)
Verification of Dynamic Aspects (2015) (0)
SISL: Concolic Testing of Structured Binary Input Formats via Partial Speci(cid:28)cation ⋆ (2022) (0)
Applications of EAs (1998) (0)
Status on Reasoning Engines and Dynamic Techniques (2010) (0)
metaSMT: focus on your application and not on solver integration (2016) (0)
Introduction to the Special Issue on Reversible Computation (2014) (0)
Circuit-Based Dynamic Learning (2012) (0)
Conclusions and Outlook (2018) (0)
Automated Equivalence Checking Method for Majority based In-Memory Computing on ReRAM Crossbars (2023) (0)
Circuits Derived from Decision Diagrams (2002) (0)
Theoretical Groundwork (2021) (0)
Verification of Static Aspects (2015) (0)
On the Generation of Area-Time (1995) (0)
SPECifIC — A New Design Flow for Cyber-Physical Systems (2017) (0)
Verification of HDLs (2000) (0)
Application II: Security Validation (2020) (0)
Mapping Quantum Circuits to 2-D Quantum Architectures (2022) (0)
Lower Bound Proof for the Size of BDDs representing a Shifted Addition (2022) (0)
Classical Synthesis Approaches (2002) (0)
Safety First: About the Detection of Arithmetic Overflows in Hardware Design Specifications (2020) (0)
Applications of Evolutionary ComputationEvoApplications 2011: EvoCOMNET, EvoFIN, EvoHOT, EvoMUSART, EvoSTIM, and EvoTRANSLOG, Torino, Italy, April 27-29, 2011, Proceedings, Part II (2011) (0)
Decision Diagram Based Minimization of Pseudo KroneckerExpressionsPer Lindgren (2007) (0)
Reconfigurable TAP Controllers with Embedded Compression (2021) (0)
Algorithms and Data Structures (2008) (0)
Block-Level Verification (2010) (0)
Application I: Verification (2020) (0)
UTILIZING BDDS FOR DISJOINT SOP MINIMIZATION Görschwin Fey (2002) (0)
Coverage-Guided Fuzzing for Plan-Based Robotics (2023) (0)
Dynamic Clause Activation (2012) (0)
Theoretical Aspects of WLDDs (2000) (0)
Program Committee DSD 2014 (2014) (0)
Proceedings of the 3rd European conference on Applications of Evolutionary Computing (2005) (0)
System-level Design Methods for Deep Learning on Heterogeneous Architectures (2021) (0)
Formal Verification of Abstract SystemC Models (2009) (0)
Conclusion and Future Work (2018) (0)
Reversible Computation (2012) (0)
Verification of Horizontal Refinement (2017) (0)
Reviewers List (2008) (0)
Fast and Exact is Doable: Polynomial Algorithms in Test and Veriﬁcation (2022) (0)
FORMAL VERIFICATION OF CIRCUITS PDF, EPUB, EBOOK (2021) (0)
One-Pass Design (2018) (0)
Layout Driven Synthesis (2002) (0)
The MicroRV32 framework: An accessible and configurable open source RISC-V cross-level platform for education and research (2022) (0)
Enhanced Virtual Prototyping (2021) (0)
ReCoFused partial reconfiguration for secure moving-target countermeasures on FPGAs (2020) (0)
Analyzing and Simulating Time Descriptions from UML/MARTE CCSL (2015) (0)
Non-Linear Waveforms for Quick Trace Navigation (2017) (0)
Considering nearest neighbor constraints of quantum circuits at the reversible circuit level (2013) (0)
Register-Transfer Level Correspondence Analysis (2020) (0)
Verifying Next Generation Electronic Systems ( Invited Paper ) (2017) (0)
SAT-based Exact Synthesis of Ternary Reversible Circuits using a Functionally Complete Gate Library (2022) (0)
Monitoring the Effects of Static Variable Orders on the Construction of BDDs (2022) (0)
Compilation and Wear Leveling for Programmable Logic-in-Memory Architecture (2019) (0)
Finite State Automata Design using 1T1R ReRAM Crossbar (2023) (0)
Improved Lookahead Approaches for Nearest Neighbor Synthesis of 1 D Quantum Circuits (2018) (0)
SWORD - Module-based SAT Solving (2009) (0)
XIVL Program C + + Program Instrumented XIVL Program Scheduler SMT Layer Native Binary Dependency Relation Callstacks Global Env (2016) (0)
One-pass Synthesis for Digital Microfluidic Biochips: A Survey (2020) (0)
7 OKFDDS-ALGORITHMS , APPLICATIONS AND EXTENSIONS (0)
Chapter 12 – Processor Verification (2007) (0)
Synthese reversibler LogikSynthesizing Reversible Logic (2010) (0)
Using density of training data to improve evolutionary algorithms with approximative fitness functions (2022) (0)
Modular and Reconfigurable System Design for Underwater Vehicles (2019) (0)
Top-Level Verification (2010) (0)
Reducing Instance Sizes with Ground Setting Properties (2018) (0)
Exact Synthesis of Reversible Logic (2010) (0)
Design Modiﬁcation for Polynomial Formal Veriﬁcation (2022) (0)
Polynomial Formal Veriﬁcation of Approximate Functions (2022) (0)
COMMUNITY ROAD SAFETY COUNCIL RESOURCE PACKAGE (1990) (0)
Optimization SAT-Based Retargeting for Embedded Compression (2021) (0)
Challenges in Model Refinement (2017) (0)
Advanced Embedded System Modeling and Simulation in an Open Source RISC-V Virtual Prototype (2022) (0)
High Quality ATPG for Transition Faults (2012) (0)
Alternative Minimization Concepts (1998) (0)
Formal Verification of SystemC-Based Designs using Symbolic Simulation (2020) (0)
Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study (2022) (0)

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