Ruby Bei-loh Lee
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Ruby Bei-loh Leecomputer-science Degrees
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Ruby Bei-loh Lee's Degrees
- PhD Computer Science Carnegie Mellon University
- Masters Computer Science Carnegie Mellon University
- Bachelors Computer Science National Taiwan University
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(Suggest an Edit or Addition)Ruby Bei-loh Lee's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- Last-Level Cache Side-Channel Attacks are Practical (2015) (865)
- New cache designs for thwarting software cache-based side channel attacks (2007) (560)
- Security as a new dimension in embedded system design (2004) (432)
- Distributed Denial of Service: Taxonomies of Attacks, Tools, and Countermeasures (2004) (376)
- Subword parallelism with MAX-2 (1996) (372)
- CATalyst: Defeating last-level cache side channel attacks in cloud computing (2016) (325)
- Eliminating the hypervisor attack surface for a more secure cloud (2011) (302)
- NoHype: virtualized cloud infrastructure without the virtualization (2010) (291)
- Covert and Side Channels Due to Processor Architecture (2006) (270)
- A novel cache architecture with enhanced performance and security (2008) (265)
- Architecture for protecting critical secrets in microprocessors (2005) (219)
- Accelerating multimedia with enhanced microprocessors (1995) (211)
- Random Fill Cache Architecture (2014) (202)
- Characterizing hypervisor vulnerabilities in cloud computing servers (2013) (198)
- CloudRadar: A Real-Time Side-Channel Attack Detection System in Clouds (2016) (182)
- Scalable architectural support for trusted software (2010) (176)
- Bit permutation instructions for accelerating software cryptography (2000) (148)
- Precision architecture (1989) (142)
- Efficient permutation instructions for fast software cryptography (2001) (134)
- Model inversion attacks against collaborative inference (2019) (130)
- Architectural support for hypervisor-secure virtualization (2012) (124)
- Enlisting Hardware Architecture to Thwart Malicious Code Injection (2004) (114)
- Machine Learning Based DDoS Attack Detection from Source Side in Cloud (2017) (108)
- Multi-sensor authentication to improve smartphone security (2015) (107)
- Hardware-rooted trust for secure key management and transient trust (2007) (95)
- Hardware Mechanisms for Memory Authentication: A Survey of Existing Techniques and Engines (2009) (92)
- Geust Editorial: Media processing: a new design target (1996) (90)
- Mapping the Intel Last-Level Cache (2015) (86)
- TEC-Tree: A Low-Cost, Parallelizable Tree for Efficient Defense Against Memory Replay Attacks (2007) (79)
- Newcache: Secure Cache Architecture Thwarting Cache Side-Channel Attacks (2016) (76)
- Taxonomies of Distributed Denial of Service Networks, Attacks, Tools, and Countermeasures (2003) (72)
- Remote Denial of Service Attacks and Countermeasures (2001) (69)
- A software-hardware architecture for self-protecting data (2012) (68)
- Implicit Sensor-based Authentication of Smartphone Users with Smartwatch (2016) (63)
- Privacy-preserving Machine Learning through Data Obfuscation (2018) (63)
- Runtime execution monitoring (REM) to detect and prevent malicious code execution (2004) (60)
- Implicit Smartphone User Authentication with Sensors and Contextual Machine Learning (2017) (60)
- A comparison of hardware prefetching techniques for multimedia benchmarks (1996) (57)
- Workload characterization of elliptic curve cryptography and other network security algorithms for constrained environments (2002) (55)
- Fast subword permutation instructions using omega and flip network stages (2000) (52)
- On-chip lookup tables for fast symmetric-key encryption (2005) (49)
- New models of cache architectures characterizing information leakage from cache side channels (2014) (47)
- Time Series Segmentation through Automatic Feature Learning (2018) (45)
- Hardware and software cache prefetching techniques for MPEG benchmarks (2000) (45)
- Accountability in hosted virtual networks (2009) (43)
- Secure Pick Up: Implicit Authentication When You Start Using the Smartphone (2017) (42)
- New Constructive Approach to Covert Channel Modeling and Channel Capacity Estimation (2005) (42)
- 64-bit and multimedia extensions in the PA-RISC 2.0 architecture (1996) (41)
- CloudMonatt: An architecture for security health monitoring and attestation of virtual machines in cloud computing (2015) (41)
- Architectural enhancements for fast subword permutations with repetitions in cryptographic applications (2001) (40)
- Sensitive-Sample Fingerprinting of Deep Neural Networks (2019) (40)
- Fast subword permutation instructions based on butterfly network (1999) (40)
- National Cyber Leap Year Summit 2009 Co-Chairs ’ Report (2009) (39)
- Algorithmic and architectural enhancements for real-time MPEG-1 decoding on a general purpose RISC workstation (1995) (38)
- Disruptive prefetching: impact on side-channel attacks and cache designs (2015) (37)
- Arbitrary bit permutations in one or two cycles (2003) (37)
- Subword permutation instructions for two-dimensional multimedia processing in MicroSIMD architectures (2000) (36)
- A Case for Hardware Protection of Guest VMs from Compromised Hypervisors in Cloud Computing (2011) (35)
- Side channel vulnerability metrics: the promise and the pitfalls (2013) (34)
- Realtime MPEG video via software decompression on a PA-RISC processor (1995) (34)
- Tempest: a substrate for portable parallel programs (1995) (33)
- DoS Attacks on Your Memory in Cloud (2017) (31)
- Early Detection of All-Zero Coefficients in H.263 (1997) (31)
- On permutation operations in cipher design (2004) (30)
- Security testing of a secure cache design (2013) (30)
- Protecting cryptographic keys and computations via virtual secure coprocessing (2005) (28)
- Attacking and Protecting Data Privacy in Edge–Cloud Collaborative Inference Systems (2021) (28)
- Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis (2007) (28)
- Efficiency of microSIMD architectures and index-mapped data for media processors (1998) (28)
- A New Basis for Shifters in General-Purpose Processors for Existing and Advanced Bit Manipulations (2009) (27)
- Capacity estimation of non-synchronous covert channels (2005) (25)
- Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity Microprocessors (2008) (25)
- Performance enhancement of H.263 encoder based on zero coefficient prediction (1997) (25)
- Bit permutation instructions: architecture, implementation, and cryptographic properties (2004) (24)
- Secure Key Management Architecture Against Sensor-Node Fabrication Attacks (2007) (24)
- PLX: a fully subword-parallel instruction set architecture for fast scalable multimedia processing (2002) (23)
- Leveraging Hardware Transactional Memory for Cache Side-Channel Defenses (2018) (22)
- Performance impact of data compression on virtual private network transactions (2000) (22)
- Implicit Authentication for Smartphone Security (2015) (22)
- A Framework for Realizing Security on Demand in Cloud Computing (2013) (22)
- Fast parallel table lookups to accelerate symmetric-key cryptography (2005) (22)
- Maya: A Novel Block Encryption Function (2009) (21)
- Re-examining Probabilistic Versus Deterministic Key Management (2007) (21)
- Subword sorting with versatile permutation instructions (2002) (21)
- Evaluating instruction set extensions for fast arithmetic on binary finite fields (2004) (19)
- Mutual Anonymous Communications: A New Covert Channel Based on Splitting Tree MAC (2007) (19)
- Performance impact of addressing modes on encryption algorithms (2001) (19)
- Fast Bit Compression and Expansion with Parallel Extract and Parallel Deposit Instructions (2006) (19)
- How a processor can permute n bits in O(1) cycles (2002) (19)
- Monitoring and Attestation of Virtual Machine Security Health in Cloud Computing (2016) (18)
- Memory DoS Attacks in Multi-tenant Clouds: Severity and Mitigation (2016) (18)
- Processor accelerator for AES (2010) (18)
- Refining instruction set architecture for high-performance multimedia processing in constrained environments (2002) (17)
- Security Basics for Computer Architects (2013) (17)
- Accelerating the Whirlpool Hash Function Using Parallel Table Lookup and Fast Cyclical Permutation (2008) (17)
- Sensor-Based Implicit Authentication of Smartphone Users (2017) (16)
- PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing (2005) (16)
- Mapping of application software to the multimedia instructions of general-purpose microprocessors (1997) (16)
- Architectural techniques for accelerating subword permutations with repetitions (2003) (16)
- Multimedia instructions in ia-64 (2001) (16)
- Hardware-Assisted Application-Level Access Control (2009) (16)
- Cryptography Efficient Permutation Instructions for Fast Software (2001) (15)
- Impact of configurability and extensibility on IPSec protocol execution on embedded processors (2006) (15)
- Blind De-anonymization Attacks using Social Networks (2017) (15)
- An automated method for software controlled cache prefetching (1998) (14)
- The Reduced Address Space (RAS) for Application Memory Authentication (2008) (14)
- Scalable security architecture for trusted software (2010) (14)
- Integration of butterfly and inverse butterfly nets in embedded processors: Effects on power saving (2012) (14)
- VerIDeep: Verifying Integrity of Deep Neural Networks through Sensitive-Sample Fingerprinting (2018) (14)
- Improving performance for software MPEG players (1996) (14)
- Physical attack protection with human-secure virtualization in data centers (2012) (13)
- Analyzing Cache Side Channels Using Deep Neural Networks (2018) (13)
- BitDeposit: Deterring Attacks and Abuses of Cloud Computing Services through Economic Measures (2013) (12)
- Stability and Benefits of Suboptimal Utility Maximization (2011) (12)
- Satisfiability-based Framework for Enabling Side-channel Attacks on Cryptographic Software (2006) (11)
- PAX : A Datapath-Scalable Minimalist Cryptographic Processor For Mobile Environments (2003) (11)
- Host-Based Dos Attacks and Defense in the Cloud (2017) (11)
- Bit matrix multiplication in commodity processors (2008) (11)
- Rapid single-chip secure processor prototyping on the OpenSPARC FPGA platform (2011) (10)
- Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution (2007) (10)
- Record-Replay Architecture as a General Security Framework (2018) (10)
- Butterfly and Inverse Butterfly nets integration on Altera NIOS-II embedded processor (2010) (10)
- Performing Advanced Bit Manipulations Efficiently in General-Purpose Processors (2007) (10)
- Can randomized mapping secure instruction caches from side-channel attacks? (2015) (10)
- 3 Multimedia Instructions in Microprocessors for Native Signal Processing (2001) (10)
- A framework for testing hardware-software security architectures (2010) (10)
- A Traitor Tracing Scheme Based on RSA for Fast Decryption (2005) (9)
- Rethinking Computers for Cybersecurity (2015) (9)
- A hardware-based technique for efficient implicit information flow tracking (2016) (9)
- Cyber defenses for physical attacks and insider threats in cloud computing (2014) (9)
- Design, Implementation and Verification of Cloud Architecture for Monitoring a Virtual Machine's Security Health (2018) (9)
- Cost-effective multiplication with enhanced adders for multimedia applications (2000) (9)
- Securing the Dissemination of Emergency Response Data with an Integrated Hardware-Software Architecture (2009) (9)
- PLX FP: an efficient floating-point instruction set for 3D graphics (2004) (8)
- General-purpose FPGA platform for efficient encryption and hashing (2010) (8)
- Alternative application-specific processor architectures for fast arbitrary bit permutations (2008) (7)
- Hardware-enhanced access control for cloud computing (2012) (6)
- Real-time MPEG-1 software decoding on HP workstations (1995) (6)
- Inferring Smartphone Users' Handwritten Patterns by using Motion Sensors (2018) (6)
- Forward-Secure Content Distribution to Reconfigurable Hardware (2008) (6)
- Hardware enhanced security (2012) (5)
- Key Management in Sensor Networks (2011) (5)
- Hardware-Enhanced Security for Cloud Computing (2014) (5)
- Scope of DDoS Countermeasures : Taxonomy of Proposed Solutions and Design Goals for Real-World Deployment (5)
- Challenges in the Design of Security-Aware Processors (2003) (5)
- Reuse of High Precision Arithmetic Hardware to Perform Multiple Low Precision Calculations (1994) (5)
- How Bad is Suboptimal Rate Allocation? (2008) (5)
- Quantification of De-anonymization Risks in Social Networks (2017) (4)
- EFFICIENT TESTING OF RISC MICROPROCESSORS. (1986) (4)
- ISA Support for Fingerprinting and Erasure Codes (2007) (4)
- Multi-Path Key Establishment against REM Attacks in Wireless Ad Hoc Networks (2009) (4)
- Security verification of hardware-enabled attestation protocols (2012) (4)
- Performance Scaling of Cryptography Operations in Servers and Mobile Clients (2004) (4)
- Computer Arithmetic-A Processor Architect's Perspective (2001) (4)
- Single-Cycle Bit Permutations with MOMR Execution (2005) (4)
- A 32kB secure cache memory with dynamic replacement mapping in 65nm bulk CMOS (2015) (3)
- Architecture for data-centric security (2012) (3)
- 1 Instruction Set Architecture for Multimedia Signal Processing (3)
- Validating Word-Oriented Processors for Bit and Multi-word Operations (2004) (3)
- Achieving subword parallelism by software reuse of the floating-point data path (1997) (3)
- Framework for Design Validation of Security Architectures (2008) (3)
- Cloud Server Benchmark Suite for Evaluating New Hardware Architectures (2017) (3)
- PAX : A Cryptographic Processor with Parallel Table Lookup and Wordsize Scalability (2007) (3)
- An evaluation of video fidelity metrics (1997) (3)
- Improving cyber security (2013) (3)
- Advanced Bit Manipulation Instruction Set Architecture (2006) (3)
- Instruction set architecture for accelerating cryptographic processing in wireless computing devices (2005) (3)
- Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy (2013) (2)
- Permutation operations in block ciphers (2005) (2)
- Security basics (2014) (2)
- Micro's top picks from microarchitecture conferences (2003) (2)
- How to Quantify Graph De-anonymization Risks (2017) (2)
- Tuning instruction customisation for reconfigurable system-on-chip (2009) (2)
- Effectiveness of the MAX-2 Multimedia Extensions for PA-RISC 2.0 Processors (2013) (2)
- Tantra: A Fast PRNG Algorithm and its Implementation (2009) (2)
- Performance Bounds for Parallel Processors. (1976) (2)
- FOR FAST SCALABLE MULTIMEDIA PROCESSING (2002) (1)
- Virtualization of a Processor-based Crypto-Protection Mechanism and Integration within a Separation Kernel Architecture (2006) (1)
- Practical and Scalable Security Verification of Secure Architectures (2018) (1)
- SP Reference Manual Addendum - Secure Stacks for TSMs and Emulation of SP Interrupt Protection (2009) (1)
- University research in hardware security (2014) (1)
- Building Technologies that Help Cyber-Defense: Hardware-enabled Trust (2012) (1)
- Cloud Server Benchmarks for Performance Evaluation of New Hardware Architecture (2016) (1)
- CloudShelter: Protecting Virtual Machines' Memory Resource Availability in Clouds (2017) (1)
- SecureCore for Trustworthy Commodity Computing and Communications (2011) (1)
- Adding 3D graphics support to PLX (2003) (1)
- Architectural techniques for enabling secure cryptographic processing (2005) (1)
- Hardware implementation of SP module with PAX cryptoprocessor (2008) (0)
- Method for realizing erasable command on computer (1991) (0)
- Impact of Dynamic Binary Translators on Security (2008) (0)
- On Secure Key Management in Mobile Ad Hoc Networks (2008) (0)
- Proceedings of the Fourth Workshop on Hardware and Architectural Support for Security and Privacy (2015) (0)
- Floating-point MicroSIMD Architecture for Fast Geometry Transform (2002) (0)
- A Framework for Testing Hardware-Software (2010) (0)
- VLSI in Computers & Processors International Conference on Computer Design (2001) (0)
- SecureCore East (Poster) (2005) (0)
- Message from the program organizers (2014) (0)
- HotChips security tutorial (2014) (0)
- Multi-path Key Establishment under Byzantine Attacks in Wireless Ad Hoc Networks (2008) (0)
- High-speed digital signal decoding method (1994) (0)
- Data Center Protection with Cyber-Physical Defenses (2013) (0)
- A New Design of Cache Memory in Computers that Improves Performance and Security (2014) (0)
- A Non-Copyable Disk (NCdisk) Concept, Architecture, Security Protocol, and Business Analysis (2008) (0)
- Improving Performance for MPEG Players. (1996) (0)
- Proceedings of the Third Workshop on Hardware and Architectural Support for Security and Privacy (2014) (0)
- Method for efficiently dealing with positive and negative overflow generated as result of arithmetical operation through hardware (1994) (0)
- SecureCore West (Poster) (2008) (0)
- Random Fill Cache Architecture (Preprint) (2014) (0)
- OPTIMAL PROGRAM CONTROL STRUCTURES BASED ON THE CONCEPT OF DECISION ENTROPY (0)
- Processor Architecture for Trustworthy Computers (2005) (0)
- Circuit and method for parallel addition and averaging (1994) (0)
- New design methodologies and circuits needed for parallel VLSI supercomputers (1986) (0)
- Securing the use of sensitive data on remote devices using a hardware-software architecture (2010) (0)
- Design, Implementation and Verification of Cloud Architecture for Monitoring a Virtual Machines Security Health (2018) (0)
- Message from HASP 2012 Organizers (2012) (0)
- 3 Instructions in Microprocessors for Native Signal Processing (2002) (0)
- An Architecture for Security Health Monitoring and Attestation in Cloud Computing (2016) (0)
- Chapter 23 Key Management in Sensor Networks (2011) (0)
- Circuit and method for parallel shift and addition (1994) (0)
- Stability and Benefits of Suboptimal (2011) (0)
- Special Section on Secure Computer Architectures (2018) (0)
- Speculative Execution Attacks and Hardware Defenses (2021) (0)
- Implementation Complexity for Achieving Bit Permutations in One or Two Cycles in Superscalar Processors (2004) (0)
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