Sam Naffziger

Q: What Schools Are Affiliated With Sam Naffziger

Sam Naffziger is affiliated with the following schools: California Institute of Technology, Stanford University

Sam Naffziger's AcademicInfluence.com Rankings

Sam Naffziger

Engineering

#8252

World Rank

#9757

Historical Rank

Electrical Engineering

#2728

World Rank

#2868

Historical Rank

Applied Physics

#3485

World Rank

#3586

Historical Rank

engineering Degrees

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Engineering

Sam Naffziger's Degrees

Bachelors Electrical Engineering Stanford University
Masters Electrical Engineering Stanford University
PhD Electrical Engineering Stanford University

Why Is Sam Naffziger Influential?

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According to Wikipedia, Samuel Naffziger is an American electrical engineer who has been employed at Advanced Micro Devices in Fort Collins, Colorado since 2006. He was named a Fellow of the Institute of Electrical and Electronics Engineers in 2014 for his leadership in the development of power management and low-power processor technologies. He is also the Senior Vice President and Product Technology Architect at AMD.

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Sam Naffziger's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Power and temperature control on a 90-nm Itanium family processor (2006) (303)
Scaling, power, and the future of CMOS (2005) (228)
The implementation of the Itanium 2 microprocessor (2002) (219)
The implementation of a 2-core, multi-threaded itanium family processor (2006) (217)
Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation (2003) (187)
A 90-nm variable frequency clock system for a power-managed itanium architecture processor (2006) (147)
A 32nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm2 at 81% efficiency (2010) (114)
Clock distribution on a dual-core, multi-threaded Itanium/sup /spl reg//-family processor (2005) (94)
The implementation of the next-generation 64b itanium microprocessor (2002) (83)
Power and temperature control on a 90nm Itanium/sup /spl reg//-family processor (2005) (70)
‘Zeppelin’: An SoC for multichip architectures (2018) (67)
Statistical clock skew modeling with data delay variations (2001) (67)
5.6 Adaptive clocking system for improved power efficiency in a 28nm x86-64 microprocessor (2014) (63)
Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor (2012) (61)
The implementation of a 2-core multi-threaded Itanium/spl reg/-family processor (2005) (57)
An x86-64 core implemented in 32nm SOI CMOS (2010) (56)
Design solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU (2011) (53)
A sub-nanosecond 0.5 /spl mu/m 64 b adder design (1996) (43)
2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products (2020) (41)
A 90nm variable-frequency clock system for a power-managed Itanium/sup /spl reg//-family processor (2005) (41)
Pioneering Chiplet Technology and Design for the AMD EPYC™ and Ryzen™ Processor Families : Industrial Product (2021) (37)
Clock distribution on a dual-core, multi-threaded Itanium/spl reg/ family microprocessor (2005) (36)
Design of the Two-Core x86-64 AMD “Bulldozer” Module in 32 nm SOI CMOS (2012) (33)
Steamroller Module and Adaptive Clocking System in 28 nm CMOS (2015) (29)
An x86-64 Core in 32 nm SOI CMOS (2011) (28)
Adaptive Techniques for Dynamic Processor Optimization (2008) (25)
A quad-issue out-of-order RISC CPU (1996) (23)
High-Performance Processors in a Power-Limited World (2006) (22)
Carrizo: A High Performance, Energy Efficient 28 nm APU (2016) (21)
Multi-chip technologies to unleash computing performance gains over the next decade (2017) (20)
4.2 Increasing the performance of a 28nm x86-64 microprocessor through system power management (2016) (20)
The implementation of the next-generation 64 b Itanium/sup TM/ microprocessor (2002) (18)
4.8 A 28nm x86 APU optimized for power and area efficiency (2015) (14)
SE2 when processors hit the power wall (or "when the CPU hits the fan") (2005) (13)
Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice (2008) (13)
Zen: An Energy-Efficient High-Performance $\times $ 86 Core (2018) (12)
The implementation of a 2-core, multi-threaded Itanium/spl reg/ family processor (2005) (12)
Design and implementation of soft-edge flip-flops for x86-64 AMD microprocessor modules (2012) (8)
3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU (2022) (8)
Technology impacts from the new wave of architectures for media-rich workloads (2011) (7)
Adaptive Voltage Frequency Scaling Using Critical Path Accumulator Implemented in 28nm CPU (2016) (7)
Understanding Chiplets Today to Anticipate Future Integration Opportunities and Limits (2021) (7)
“Zeppelin”: An SoC for Multichip Architectures (2019) (7)
AMD ’ s Commitment to Accelerating Energy Efficiency (2015) (6)
Energy-Efficient Graphics and Multimedia in 28-nm Carrizo Accelerated Processing Unit (2016) (6)
Microprocessors of the future: Commodity or engine growth? (2009) (5)
8.4 Radeon RX 5700 Series: The AMD 7nm Energy-Efficient High-Performance GPUs (2020) (5)
Bristol Ridge: A 28-nm $\times$ 86 Performance-Enhanced Microprocessor Through System Power Management (2017) (4)
AMD SOC power management: Improving performance/watt using run-time feedback (2014) (3)
Multi-Threaded Itanium®-Family Processor (2005) (3)
Hot Chips 25 (2014) (2)
A New Era of Tailored Computing (2021) (2)
Resonant clock design for a power-efficient high-volume x86–64 microprocessor (2012) (1)
Hot Chips 26 [Guest editors' introduction] (2015) (1)
Un dispositif de compensation de couplage parasite pour circuits VLSI (1998) (0)
Inregrated circuit having dynamically adjustable clock signal frequency (2002) (0)
System and method for dynamically changing a clock signal (2004) (0)
SRAM cell with einzelem read port and two ports for writing (1998) (0)
Cache control using queues to buffer requests and data (2003) (0)
This forum is intended for circuit designers and engineering students looking to understand the latest design techniques in multiple-domain clock and power management for high-performance processors and low power systems-on-chip (SoC). (2009) (0)
Welcome program chairs (2014) (0)
A system and method of synchronizing a plurality of clock variable frequency generators (2004) (0)
Unified Power Frequency Model Framework (2016) (0)
Chapter 2 Technological Boundaries of Voltage and Frequency Scaling for Power Performance Tuning (2008) (0)
SRAM cell with single reading gate and two gates for writing (1998) (0)
Maintaining the performance of an integrated circuit (2006) (0)
System and method for measuring a current (2004) (0)
Products and processes for dynamically changing a clock signal (2004) (0)
Method for measuring processor energy demand has integrated circuit and system combines (2004) (0)
SE1: What Technologies Will Shape the Future of Computing? (2021) (0)
An apparatus for compensating for parasitic coupling for VLSI circuits (1998) (0)
An adjustable terminating resistance and matching current shunt (2002) (0)
Method and system for calibrating a voltage controlled oscillator (VCO) (2004) (0)
Correction to "statistical clock skew modeling with data delay variations" (2003) (0)
1.1 Innovation For the Next Decade of Compute Efficiency (2023) (0)
Central processing unit having a plurality of clock zones and operating procedures (2004) (0)

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Other Resources About Sam Naffziger

en.wikipedia.org

What Schools Are Affiliated With Sam Naffziger?

Sam Naffziger is affiliated with the following schools:

Sam Naffziger's Academic­Influence.com Rankings

Sam Naffziger's Degrees

Why Is Sam Naffziger Influential?

Sam Naffziger's Published Works

Published Works

Other Resources About Sam Naffziger

What Schools Are Affiliated With Sam Naffziger?

Sam Naffziger's AcademicInfluence.com Rankings