Sanjay Banerjee
#94,432
Most Influential Person Now
American engineer
Sanjay Banerjee's AcademicInfluence.com Rankings
Sanjay Banerjeeengineering Degrees
Engineering
#2866
World Rank
#3855
Historical Rank
Electrical Engineering
#1307
World Rank
#1398
Historical Rank
Applied Physics
#3498
World Rank
#3601
Historical Rank
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Engineering
Sanjay Banerjee's Degrees
- Bachelors Electrical Engineering Stanford University
- Masters Electrical Engineering Stanford University
- PhD Electrical Engineering Stanford University
Why Is Sanjay Banerjee Influential?
(Suggest an Edit or Addition)According to Wikipedia, Sanjay Banerjee is an American engineer at the University of Texas at Austin, director of Microelectronics Research Center, and director of the Southwest Academy of Nanoelectronics — one of three such centers in the United States funded by the Semiconductor Research Corporation to develop a replacement for MOSFETs as part of their Nanoelectronics Research Initiative .
Sanjay Banerjee's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- Anomalous leakage current in LPCVD PolySilicon MOSFET's (1985) (271)
- Bilayer PseudoSpin Field-Effect Transistor (BiSFET): A Proposed New Logic Device (2009) (186)
- Characteristics and Three-Dimensional Integration of MOSFET's in Small-Grain LPCVD Polycrystalline Silicon (1985) (159)
- Understanding the effects of wave function penetration on the inversion layer capacitance of NMOSFETs (2001) (61)
- Metal-germanium-metal photodetectors on heteroepitaxial Ge-on-Si with amorphous Ge Schottky barrier enhancement layers (2004) (60)
- Ultrathin Al/sub 2/O/sub 3/ and HfO/sub 2/ gate dielectrics on surface-nitrided Ge (2004) (59)
- A trench transistor cross-point DRAM cell (1985) (47)
- 21-GHz-Bandwidth Germanium-on-Silicon Photodiode Using Thin SiGe Buffer Layers (2006) (45)
- Protein-Mediated Nanocrystal Assembly for Flash Memory Fabrication (2007) (40)
- Mobility enhancement in surface channel SiGe PMOSFETs with HfO2 gate dielectrics (2003) (40)
- Interfacial defect states in HfO/sub 2/ and ZrO/sub 2/ nMOS capacitors (2002) (37)
- MC simulation of strained-Si MOSFET with full-band structure and quantum correction (2004) (37)
- Improved Ge Surface Passivation With Ultrathin $ \hbox{SiO}_{X}$ Enabling High-Mobility Surface Channel pMOSFETs Featuring a HfSiO/WN Gate Stack (2007) (35)
- Bilayer Pseudospin Field-Effect Transistor: Applications to Boolean Logic (2010) (35)
- A deep submicron Si/sub 1-x/Ge/sub x//Si vertical PMOSFET fabricated by Ge ion implantation (1998) (33)
- Physically based quantum-mechanical compact model of MOS devices substrate-injected tunneling current through ultrathin (EOT /spl sim/ 1 nm) SiO/sub 2/ and high-/spl kappa/ gate stacks (2006) (29)
- Effectiveness of SiGe Buffer Layers in Reducing Dark Currents of Ge-on-Si Photodetectors (2007) (28)
- Fabrication of Ni Nanocrystal Flash Memories Using a Polymeric Self-Assembly Approach (2007) (28)
- A convergence scheme for over-erased flash EEPROM's using substrate-bias-enhanced hot electron injection (1995) (27)
- A physically based compact gate C-V model for ultrathin (EOT /spl sim/1 nm and below) gate dielectric MOS devices (2005) (27)
- Substrate-current-induced hot electron (SCIHE) injection: a new convergence scheme for flash memory (1995) (25)
- Improved performance of SiGe nanocrystal memory with VARIOT tunnel barrier (2006) (25)
- Characteristics and three-dimensional integration of MOSFET's in small-grain LPCVD polycrystalline Silicon (1985) (24)
- Core-Shell Germanium–Silicon Nanocrystal Floating Gate for Nonvolatile Memory Applications (2008) (22)
- Vertical Flash Memory Cell With Nanocrystal Floating Gate for Ultradense Integration and Good Retention (2007) (22)
- Improved hot-electron reliability in strained-Si nMOS (2004) (20)
- Fabrication of Self-Aligned Enhancement-Mode $ \hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}$ MOSFETs With $ \hbox{TaN/HfO}_{2}\hbox{/AlN}$ Gate Stack (2008) (20)
- System-in-a-package integration of SAW RF Rx filter stacked on a transceiver chip (2005) (20)
- Source-side barrier effects with very high-K dielectrics in 50 nm Si MOSFETs (1999) (20)
- Novel SiGeC channel heterojunction PMOSFET (1996) (19)
- Monte Carlo study of Germanium n- and pMOSFETs (2005) (18)
- Vth variation and strain control of high Ge% thin SiGe channels by millisecond anneal realizing high performance pMOSFET beyond 16nm node (2006) (18)
- Hole Mobility and Thermal Velocity Enhancement for Uniaxial Stress in Si up to 4 GPa (2007) (17)
- Demonstration of $L_{g} \sim \hbox{55}\ \hbox{nm}$ pMOSFETs With $\hbox{Si/Si}_{0.25}\hbox{Ge}_{0.75}/\hbox{Si}$ Channels, High $I_{\rm on}/I_{\rm off}\ (≫ \hbox{5} \times \hbox{10}^{4})$ , and Controlled Short Channel Effects (SCEs) (2008) (16)
- Trench capacitor leakage in Mbit DRAMs (1984) (16)
- Metal-germanium-metal photodetectors on heteroepitaxial Ge-on-Si with amorphous Ge Schottky barrier enhancement layers (2003) (14)
- Performance Analysis of Germanium Nanowire Tunneling Field Effect Transistors (2008) (14)
- Ballistic to Diffusive Crossover in III–V Nanowire Transistors (2007) (13)
- Nanocrystal flash memory fabricated with protein-mediated assembly (2005) (13)
- Role of Metal–Semiconductor Contact in Nanowire Field-Effect Transistors (2010) (13)
- Mechanisms for low on-state current of Ge (SiGe) nMOSFETs: A comparative study on gate stack, resistance, and orientation-dependent effective masses (2006) (12)
- The origin of secondary electron gate current: a multiple-stage Monte Carlo study for scaled, low-power flash memory (1998) (10)
- Enhanced secondary electron injection in novel SiGe flash memory devices (2000) (10)
- Simulation of quantum and scattering effects along the channel of ultra-scaled Si-based MOSFETs (2002) (9)
- Trench capacitor design issues in VLSI DRAM cells (1986) (9)
- Boron retarded diffusion in the presence of indium or germanium (2002) (8)
- Flicker-Noise Improvement in 100-nm $L_{g}\ \hbox{Si}_{0.50}\hbox{Ge}_{0.50}$ Strained Quantum-Well Transistors Using Ultrathin Si Cap Layer (2010) (8)
- A multilevel approach toward quadrupling the density of flash memory (1998) (7)
- Trigate FET Device Characteristics Improvement Using a Hydrogen Anneal Process With a Novel Hard Mask Approach (2007) (7)
- On strain and scattering in deeply-scaled n-channel MOSFETs: A quantum-corrected semiclassical Monte Carlo analysis (2008) (7)
- Electron transport properties in novel orthorhombically-strained silicon material explored by the Monte Carlo method (2000) (6)
- Congenital heart disease in the ESC EORP Registry of Pregnancy and Cardiac disease (ROPAC) (2021) (6)
- BC high-/spl kappa//metal gate Ge/C alloy pMOSFETs fabricated directly on Si (100) substrates (2006) (6)
- Negative Differential Resistance in Buried-Channel $\hbox{Ge}_{x} \hbox{C}_{1 - x}$ pMOSFETs (2009) (5)
- Compact model of MOSFET electron tunneling current through ultra-thin SiO/sub 2/ and high-k gate stacks (2003) (5)
- Scaling Properties of $\hbox{Ge}$ –$\hbox{Si}_{x}\hbox{Ge}_{1 - x}$ Core–Shell Nanowire Field-Effect Transistors (2009) (5)
- Monte Carlo study of remote Coulomb and remote surface roughness scattering in nanoscale Ge PMOSFETs with ultrathin high-k dielectrics (2006) (5)
- Planar Be-implanted GaAs junction formation using swept-line electron beam annealing (1983) (5)
- Trench transistor DRAM cell (1986) (5)
- Polysilicon transistors in VLSI MOS memories (1984) (5)
- A sixteen level scheme enabling 64 Mbit flash memory using 16 Mbit technology (1996) (5)
- Thin germanium–carbon layers deposited directly on silicon for metal–oxide–semiconductor devices (2006) (5)
- Enhanced CHISEL programming in flash memory devices with SiGe buried layer (2004) (4)
- Enhanced hot-electron performance of strained Si NMOS over unstrained Si (2004) (4)
- A Program for Device Model Parameter Extraction from Gate Capacitance and Current of Ultrathin$hboxSiO_2$and High-$kappa$Gate Stacks (2006) (4)
- Monte Carlo study of strained GermaniumNanoscale bulk pMOSFETs (2006) (4)
- Enhancement of drain current in vertical SiGe/Si PMOS transistors using novel CMOS technology (1997) (4)
- Indium out-diffusion from silicon during rapid thermal annealing (2003) (4)
- Modeling high k gate current from p-type Si inversion layers (2000) (3)
- VB-5 comparison of accumulation and inversion mode LPCVD polysilicon MOSFET characteristics for memory applications (1984) (3)
- A novel sidewall strained-Si channel nMOSFET (1999) (3)
- Asymmetry in Gate Capacitance–Voltage$(C$–$V)$Behavior of Ultrathin Metal Gate MOSFETs With$hboxHfO_2$Gate Dielectrics (2006) (3)
- SiGe and Si PMOSFET's characteristics with ZrO/sub 2/ gate dielectric (2000) (2)
- Fabrication of a novel vertical pMOSFET with enhanced drive current and reduced short-channel effects and floating body effects (2001) (2)
- MOS capacitors on epitaxial Ge-Si/sub 1-x/Ge/sub x/ with high-/spl kappa/ dielectrics using RPCVD (2004) (2)
- Graphene field-effect transistors using large-area monolayer graphene grown by chemical vapor deposition on Co thin films (2011) (2)
- Quantum effects along the channel of ultra-scaled Si-based MOSFETs? (2000) (2)
- Two-dimensional bandgap engineering in a novel Si-SiGe pMOSFET with enhanced device performance and scalability (2000) (2)
- Comparison of Tri-gate FET Characteristics for Various Hydrogen Annealing Process Conditions (2006) (2)
- Two-level Voltage-controlled magnetization switch using a ferromagnetic semiconductor resonant-tunneling diode (2006) (2)
- Monte carlo study of germanium N- and P- MOSFETs (2005) (2)
- A new and accurate quantum mechanical compact model for NMOS gate capacitance (2001) (2)
- Scattering in a nano-scale MOSFET: a quantum transport analysis (2003) (2)
- Boron retarded diffusion in the presence of indium or germanium (2002) (2)
- Protein-Assembled Nanocrystal-Based Vertical Flash Memory Devices with Al2O3 Integration (2009) (2)
- 3X hole mobility enhancement in epitaxially grown SiGe PMOSFETs on (110) Si substrates with high k / metal gate for hybrid orientation technology (2007) (2)
- Trench capacitor leakage in high-density DRAM's (1984) (1)
- Thin Germanium-Carbon Layers on Silicon for Metal-Oxide-Semiconductor Devices (2006) (1)
- Planar junctions in silicon on oxide grown using lateral epitaxy by seeded solidification (1985) (1)
- A Novel Low-Cost Trigate Process Suitable for Embedded CMOS 1T-1C Pseudo-SRAM Application (2009) (1)
- Interdigitated photodiode fabricated on high quality Ge on Si with thin SiGe buffer layers (2006) (1)
- Junction Passivation for Direct Silicon Bond Hybrid Orientation Technology (2007) (1)
- Flash Memory Fabricated with Protein-Mediated PbSe Nanocrystal Assembly as Floating Gate (2007) (1)
- D-band frequency memristor switch based on monolayer boron nitride (2022) (1)
- Transmission through the band-gap states in Schottky-barrier carbon nanotube transistors (2006) (1)
- Rapid thermal annealing for H passivation of polysilicon MOSFETs from Si/sub 3/N/sub 4/ overcoat (1989) (1)
- Bandgap engineering in deep submicron vertical pMOSFETs (2000) (1)
- Vacancy At Si-SiO2 Interface: Ab-Initio Study (2006) (1)
- Integration of SAW RF Rx filter stacked on a transceiver chip in a QFN package (2004) (1)
- Drive current enhancement in high-K/metal gate germanium-carbide pMOSFETs fabricated directly on Si substrates (2005) (0)
- Ab initio calculation of As-vacancy deactivation and interstitial-mediated As diffusion in strained Si (2006) (0)
- Monte Carlo simulation of consecutive implants into SiO/sub 2/ capped Si (2002) (0)
- Centimeter-Scale MoS2 on Solid Electrolyte Substrate by Sulfurization of Molybdenum Thin Film (2021) (0)
- Vertical Flash memory devices with Protein-assembled Nanocrystal floating gate and A12O3 control oxide (2008) (0)
- A novel sidewall strained-Si channel nMOSFET (1999) (0)
- Impact of metal contact depth on device performance in back-gated semiconductor nanowire field effect transistors (2008) (0)
- A path-sum Monte Carlo approach for many-electron systems within a tight-binding basis (2012) (0)
- SiGe cantilever channel gate-all-around (GAA) fully depleted (FD) PMOSFET with high-κ and metal gate (2007) (0)
- Bridging the gap between classical and quantum transport in nanoscale MOSFETs: Schrodinger equation Monte Carlo-2D (2003) (0)
- Monte Carlo simulation of ion implantation (3-dimensional) and defect modeling during implantation process (2001) (0)
- High Mobility Strained Ge MOSFETs with high-k gate dielectric on Si (2005) (0)
- Complex band structure-based non-equilibrium Green's function (NEGF) transport studies for ultra-scaled carbon nanotube (CNT) transistors [CNTFETs] (2004) (0)
- Core-shell germanium-silicon nanoparticle structure for high κ nonvolatile memory applications (2007) (0)
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Sanjay Banerjee is affiliated with the following schools:
