Scott Mahlke

Q: What Schools Are Affiliated With Scott Mahlke

Scott Mahlke is affiliated with the following schools: University of Michigan, Stanford University

Scott Mahlke's AcademicInfluence.com Rankings

Scott Mahlke

Engineering

#7059

World Rank

#8419

Historical Rank

Electrical Engineering

#2169

World Rank

#2275

Historical Rank

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Engineering

Scott Mahlke's Degrees

PhD Electrical Engineering Stanford University
Masters Electrical Engineering Stanford University

Why Is Scott Mahlke Influential?

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According to Wikipedia, Scott Mahlke from the University of Michigan, Ann Arbor, MI was named Fellow of the Institute of Electrical and Electronics Engineers in 2015 for contributions to compiler code generation and automatic processor customization.

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Scott Mahlke's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Effective Compiler Support For Predicated Execution Using The Hyperblock (1992) (656)
COMET: Code Offload by Migrating Execution Transparently (2012) (417)
The superblock: An effective technique for VLIW and superscalar compilation (1993) (371)
Scalpel: Customizing DNN pruning to the underlying hardware parallelism (2017) (313)
Shoestring: probabilistic soft error reliability on the cheap (2010) (274)
SAGE: Self-tuning approximation for graphics engines (2013) (266)
SODA: A Low-power Architecture For Software Radio (2006) (259)
IMPACT: an architectural framework for multiple-instruction-issue processors (1991) (246)
Using profile information to assist classic code optimizations (1991) (242)
Orchestrating the execution of stream programs on multicore platforms (2008) (234)
Processor acceleration through automated instruction set customization (2003) (229)
Paraprox: pattern-based approximation for data parallel applications (2014) (208)
BulletProof: a defect-tolerant CMP switch architecture (2006) (207)
A comparison of full and partial predicated execution support for ILP processors (1995) (200)
Edge-centric modulo scheduling for coarse-grained reconfigurable architectures (2008) (192)
Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization (2004) (190)
IMPACT: an architectural framework for multiple-instruction-issue processors (1991) (188)
Profile‐guided automatic inline expansion for C programs (1992) (178)
Trimaran: An Infrastructure for Research in Instruction-Level Parallelism (2004) (178)
An architecture framework for transparent instruction set customization in embedded processors (2005) (167)
Gadara: Dynamic Deadlock Avoidance for Multithreaded Programs (2008) (159)
Chimera: Collaborative Preemption for Multitasking on a Shared GPU (2015) (156)
Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures (2007) (149)
Composite Cores: Pushing Heterogeneity Into a Core (2012) (148)
High-level synthesis of nonprogrammable hardware accelerators (2000) (147)
AnySP: Anytime Anywhere Anyway Signal Processing (2009) (144)
PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators (2002) (139)
Integrated predicated and speculative execution in the IMPACT EPIC architecture (1998) (137)
Rumba: An online quality management system for approximate computing (2015) (134)
The theory of deadlock avoidance via discrete control (2009) (132)
Dynamic memory disambiguation using the memory conflict buffer (1994) (131)
Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory (2009) (121)
Sentinel scheduling: a model for compiler-controlled speculative execution (1992) (121)
Transparent CPU-GPU collaboration for data-parallel kernels on heterogeneous systems (2013) (120)
Characterizing the impact of predicated execution on branch prediction (1994) (120)
Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications (2007) (117)
Flextream: Adaptive Compilation of Streaming Applications for Heterogeneous Architectures (2009) (117)
Automated custom instruction generation for domain-specific processor acceleration (2005) (113)
VEAL: Virtualized Execution Accelerator for Loops (2008) (112)
Data access microarchitectures for superscalar processors with compiler-assisted data prefetching (1991) (110)
From SODA to scotch: The evolution of a wireless baseband processor (2008) (108)
Uncovering hidden loop level parallelism in sequential applications (2008) (106)
Bundled execution of recurring traces for energy-efficient general purpose processing (2011) (106)
Polymorphic Pipeline Array: A flexible multicore accelerator with virtualized execution for mobile multimedia applications (2009) (106)
Bitwidth cognizant architecture synthesis of custom hardwareaccelerators (2001) (102)
In-Memory Data Parallel Processor (2018) (101)
Self-calibrating Online Wearout Detection (2007) (101)
Cost-efficient soft error protection for embedded microprocessors (2006) (99)
Memory-centric system interconnect design with hybrid memory cubes (2013) (97)
A framework for balancing control flow and predication (1997) (97)
Reverse If-Conversion (1993) (95)
Superblock formation using static program analysis (1993) (93)
SODA: A High-Performance DSP Architecture for Software-Defined Radio (2007) (93)
Sponge: portable stream programming on graphics engines (2011) (90)
The StageNet fabric for constructing resilient multicore systems (2008) (87)
ZerehCache: Armoring cache architectures in high defect density technologies (2009) (86)
Sentinel scheduling: a model for compiler-controlled speculative execution (1993) (85)
Optimus: efficient realization of streaming applications on FPGAs (2008) (84)
Modulo graph embedding: mapping applications onto coarse-grained reconfigurable architectures (2006) (83)
Bridging the computation gap between programmable processors and hardwired accelerators (2009) (81)
Mascar: Speeding up GPU warps by reducing memory pitstops (2015) (80)
Archipelago: A polymorphic cache design for enabling robust near-threshold operation (2011) (76)
Region-based hierarchical operation partitioning for multicluster processors (2003) (75)
Compiler technology for future microprocessors (1995) (73)
Reliable Systems on Unreliable Fabrics (2008) (73)
Input responsiveness: using canary inputs to dynamically steer approximation (2016) (71)
Accelerating Mobile Applications through Flip-Flop Replication (2015) (70)
Dynamic Resource Management for Efficient Utilization of Multitasking GPUs (2017) (70)
Exploiting instruction level parallelism in the presence of conditional branches (1997) (65)
CGRA express: accelerating execution using dynamic operation fusion (2009) (65)
Scalable subgraph mapping for acyclic computation accelerators (2006) (63)
Duality Cache for Data Parallel Acceleration (2019) (62)
Equalizer: Dynamic Tuning of GPU Resources for Efficient Execution (2014) (62)
The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors (1995) (62)
Encore: Low-cost, fine-grained transient fault recovery (2011) (61)
DeftNN: Addressing Bottlenecks for DNN Execution on GPUs via Synapse Vector Elimination and Near-compute Data Fission (2017) (61)
APOGEE: Adaptive prefetching on GPUs for energy efficiency (2013) (54)
Compiler managed dynamic instruction placement in a low-power code cache (2005) (53)
Harnessing Soft Computations for Low-Budget Fault Tolerance (2014) (53)
Recurrence cycle aware modulo scheduling for coarse-grained reconfigurable architectures (2009) (52)
Stream Compilation for Real-Time Embedded Multicore Systems (2009) (51)
Compiler code transformations for superscalar-based high-performance systems (1992) (50)
Liquid SIMD: Abstracting SIMD Hardware using Lightweight Dynamic Mapping (2007) (50)
Eliminating Concurrency Bugs with Control Engineering (2009) (49)
Trace based phase prediction for tightly-coupled heterogeneous cores (2013) (49)
Achieving high levels of instruction-level parallelism with reduced hardware complexity (1997) (48)
Mobile supercomputers (2004) (48)
Runtime asynchronous fault tolerance via speculation (2012) (48)
Process variation in near-threshold wide SIMD architectures (2012) (48)
Automatic speculative DOALL for clusters (2012) (47)
Dynamic parallelization of JavaScript applications using an ultra-lightweight speculation mechanism (2011) (47)
Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors (2010) (46)
Scaling Performance via Self-Tuning Approximation for Graphics Engines (2014) (45)
Sentinel scheduling for VLIW and superscalar processors (1992) (44)
Heterogeneous microarchitectures trump voltage scaling for low-power cores (2014) (44)
Scalpel (2017) (43)
Concise loads and stores: The case for an asymmetric compute-memory architecture for approximation (2016) (41)
Design and Implementation of Turbo Decoders for Software Defined Radio (2006) (41)
Software Defined Radio - A High Performance Embedded Challenge (2005) (40)
Adaptive input-aware compilation for graphics engines (2012) (40)
Concurrency bugs in multithreaded software: modeling and analysis using Petri nets (2013) (39)
Exploring the design space of LUT-based transparent accelerators (2005) (39)
Eliminating Concurrency Bugs in Multithreaded Software: A New Approach Based on Discrete-Event Control (2013) (39)
The Next Generation Challenge for Software Defined Radio (2007) (38)
Automatic and efficient evaluation of memory hierarchies for embedded systems (1999) (38)
VAST: The illusion of a large memory space for GPUs (2014) (38)
Register Connection: A New Approach To Adding Registers Into Instruction Set Architectures (1993) (38)
Compiler synthesized dynamic branch prediction (1996) (37)
Cost sensitive modulo scheduling in a loop accelerator synthesis system (2005) (37)
StageNet: A Reconfigurable Fabric for Constructing Dependable CMPs (2011) (37)
Efficient soft error protection for commodity embedded microprocessors using profile information (2012) (36)
WarpPool: Sharing requests with inter-warp coalescing for throughput processors (2015) (36)
Gadara nets: Modeling and analyzing lock allocation for deadlock avoidance in multithreaded software (2009) (35)
MacroSS: macro-SIMDization of streaming applications (2010) (35)
Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats (2000) (35)
A distributed control path architecture for VLIW processors (2005) (34)
Architectural optimizations for low-power, real-time speech recognition (2003) (34)
Multicore compilation strategies and challenges (2009) (34)
The program decision logic approach to predicated execution (1999) (33)
Comparing static and dynamic code scheduling for multiple-instruction-issue processors (1991) (33)
Three Architecutral Models for Compiler-Controlled Speculative Execution (1995) (33)
SKMD: Single Kernel on Multiple Devices for Transparent CPU-GPU Collaboration (2015) (33)
WiBench: An open source kernel suite for benchmarking wireless systems (2013) (31)
A Microarchitectural Analysis of Soft Error Propagation in a Production-Level Embedded Microprocessor (2005) (31)
SPEX: A Programming Language for Software Defined Radio (2006) (31)
Speculative execution exception recovery using write-back suppression (1993) (31)
SIMD defragmenter: efficient ILP realization on data-parallel architectures (2012) (31)
When less is more (LIMO):controlled parallelism forimproved efficiency (2012) (30)
RegLess: Just-in-Time Operand Staging for GPUs (2017) (30)
Optimal Liveness-Enforcing Control for a Class of Petri Nets Arising in Multithreaded Software (2013) (30)
Low cost control flow protection using abstract control signatures (2013) (30)
Diet SODA: A power-efficient processor for digital cameras (2010) (30)
Systematic register bypass customization for application-specific processors (2003) (30)
Online Timing Analysis for Wearout Detection (2006) (28)
Dynamically accelerating client-side web applications through decoupled execution (2011) (28)
Partitioning variables across register windows to reduce spill code in a low-power processor (2005) (28)
Scalar program performance on multiple-instruction-issue processors with a limited number of registers (1992) (28)
Control CPR: a branch height reduction optimization for EPIC architectures (1999) (27)
Modulo scheduling for highly customized datapaths to increase hardware reusability (2008) (27)
Orchestrating Multiple Data-Parallel Kernels on Multiple Devices (2015) (27)
Automatically generating custom instruction set extensions (2002) (27)
Enabling ultra low voltage system operation by tolerating on-chip cache failures (2009) (26)
Compiler-managed partitioned data caches for low power (2007) (26)
Paragon: collaborative speculative loop execution on GPU and CPU (2012) (26)
Design And Implementation Of A Portable Global Code Optimizer (1991) (25)
Prodigy: Improving the Memory Latency of Data-Indirect Irregular Workloads Using Hardware-Software Co-Design (2021) (25)
Streamroller:: automatic synthesis of prescribed throughput accelerator pipelines (2006) (25)
Adaptive online testing for efficient hard fault detection (2009) (25)
Mobile Supercomputers for the Next-Generation Cell Phone (2010) (25)
Using Profile Information to Assist Advaced Compiler Optimization and Scheduling (1992) (25)
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture (2002) (24)
Quality Control for Approximate Accelerators by Error Prediction (2016) (24)
Hierarchical coarse-grained stream compilation for software defined radio (2007) (24)
Libra: Tailoring SIMD Execution Using Heterogeneous Hardware and Dynamic Configurability (2012) (24)
An Efficient Architecture For Loop Based Data Preloading (1992) (24)
Supervisory control of software execution for failure avoidance: Experience from the Gadara project (2010) (24)
Increasing hardware efficiency with multifunction loop accelerators (2006) (23)
Accelerating asynchronous programs through Event Sneak Peek (2015) (22)
Compiler-directed data partitioning for muiticluster processors (2006) (22)
DynaMOS: Dynamic schedule migration for heterogeneous cores (2015) (22)
Necromancer: enhancing system throughput by animating dead cores (2010) (22)
The application of supervisory control to deadlock avoidance in concurrent software (2008) (22)
Increasing the number of effective registers in a low-power processor using a windowed register file (2003) (22)
Tango (2015) (21)
StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems (2008) (21)
EFetch: Optimizing instruction fetch for event-driven web applications (2014) (21)
Three Superblock Scheduling Models for Superscalar and Superpipelined Processors (1991) (21)
PEPSC: A Power-Efficient Processor for Scientific Computing (2011) (20)
Olay : Combat the Signs of Aging with Introspective Reliability Management (2008) (20)
Erasing Core Boundaries for Robust and Configurable Performance (2010) (20)
Instant profiling: Instrumentation sampling for profiling datacenter applications (2013) (20)
Tolerating data access latency with register preloading (1992) (19)
Predicate-aware scheduling: a technique for reducing resource constraints (2003) (19)
StageWeb: Interweaving pipeline stages into a wearout and variation tolerant CMP fabric (2010) (17)
D2MA: Accelerating coarse-grained data transfer for GPUs (2014) (16)
Efficient performance scaling of future CGRAs for mobile applications (2012) (16)
DVFS in loop accelerators using BLADES (2008) (15)
Practical lock/unlock pairing for concurrent programs (2013) (15)
A System Solution for High-Performance, Low Power SDR (2005) (15)
Architecting an LTE base station with graphics processing units (2013) (14)
Analyzing the scalability of SIMD for the next generation software defined radio (2008) (14)
Exploiting Narrow Accelerators with Data-Centric Subgraph Mapping (2007) (14)
Illusionist: Transforming lightweight cores into aggressive cores on demand (2013) (13)
Reliability: Fallacy or Reality? (2007) (13)
Insights into the Memory Demands of Speech Recognition Algorithms (2002) (13)
Tolerating First Level Memory Access Latency in High-Performance Systems (1992) (13)
Assessing SEU Vulnerability via Circuit-Level Timing Analysis (2005) (13)
Synthesis of maximally-permissive liveness-enforcing control policies for Gadara petri nets (2010) (13)
Using Graphics Processing Units in an LTE Base Station (2015) (13)
CPU-GPU Collaboration for Output Quality Monitoring (2014) (12)
Sculptor: Flexible Approximation with Selective Dynamic Loop Perforation (2018) (12)
Mighty-morphing power-SIMD (2010) (12)
A Customized Processor for Energy Efficient Scientific Computing (2012) (12)
AVGuardian: Detecting and Mitigating Publish-Subscribe Overprivilege for Autonomous Vehicle Systems (2020) (12)
Sentinel Scheduling with Recovery Blocks (1995) (11)
BugMD: Automatic Mismatch Diagnosis for Bug triaging (2016) (11)
Rethinking Numerical Representations for Deep Neural Networks (2017) (11)
The Partial Reverse If-Conversion Framework for Balancing Control Flow and Predication (1999) (11)
Exploring Fine-Grained Heterogeneity with Composite Cores (2016) (11)
MEDICS: Ultra-portable processing for medical image reconstruction (2010) (11)
A parameterized dataflow language extension for embedded streaming systems (2008) (10)
Architecting a reliable CMP switch architecture (2007) (10)
The Effect of Compiler Optimizations on Available Parallelism in Scalar Programs (1991) (10)
ELF: maximizing memory-level parallelism for GPUs with coordinated warp and fetch scheduling (2015) (10)
Deadlock-avoidance control of multithreaded software: An efficient siphon-based algorithm for Gadara petri nets (2011) (10)
Customizing wide-SIMD architectures for H.264 (2009) (10)
Automatic Design of Application Specific Instruction Set Extensions Through Dataflow Graph Exploration (2003) (10)
FLASH: foresighted latency-aware scheduling heuristic for processors with customized datapaths (2004) (9)
Analyzing the Next Generation Software Defined Radio for Future Architectures (2011) (9)
Mirage Cores: The Illusion of Many Out-of-order Cores Using In-order Hardware (2017) (9)
Profile-assisted instruction scheduling (1994) (9)
Tango: Accelerating Mobile Applications through Flip-Flop Replication (2015) (8)
Power-efficient medical image processing using PUMA (2009) (8)
Maximally permissive deadlock avoidance for multithreaded computer programs (Extended abstract) (2009) (7)
Automatic synthesis of customized local memories for multicluster application accelerators (2004) (7)
Probabilistic predicate-aware modulo scheduling (2004) (7)
A Systematic Framework to Identify Violations of Scenario-dependent Driving Rules in Autonomous Vehicle Software (2021) (7)
Efficient execution of augmented reality applications on mobile programmable accelerators (2013) (6)
PolygraphMR: Enhancing the Reliability and Dependability of CNNs (2020) (6)
SKMD (2015) (6)
A dataflow-centric approach to design low power control paths in CGRAs (2009) (6)
Maximizing Spare Utilization by Virtually Reorganizing Faulty Cache Lines (2011) (6)
Parallelization techniques for implementing trellis algorithms on graphics processors (2013) (5)
Compiler-directed Synthesis of Multifunction Loop Accelerators (5)
StageNet : A Reconfigurable CMP Fabric for Resilient Systems (2007) (5)
A study of the effects of compiler-controlled speculation on instruction and data caches (1995) (5)
SRTuner: Effective Compiler Optimization Customization by Exposing Synergistic Relations (2022) (5)
Memory System Design Space Exploration for Low-Power, Real-Time Speech Recognition (2004) (5)
Memory system design space exploration for low-power, real-time speech recognition (2004) (5)
Fine Grain Cache Partitioning Using Per-Instruction Working Blocks (2015) (4)
Architectural and compiler mechanisms for accelerating single thread applications on multicore processors (2008) (4)
TF-Net (2019) (4)
A bypass first policy for energy-efficient last level caches (2016) (4)
Low-cost prediction-based fault protection strategy (2020) (4)
Leveraging GPUs using cooperative loop speculation (2014) (4)
Path Sensitive Signatures for Control Flow Error Detection (2020) (4)
In-memory Data Flow Processor (2017) (4)
Instant Proﬁling: Instrumentation Sampling for Proﬁling Datacenter Applications (2013) (4)
A Programmable Vector Coprocessor Architecture for Wireless Applications (2004) (4)
CoreGenesis: erasing core boundaries for robust and configurable performance (2010) (4)
Reducing Control Power in CGRAs with Token Flow (2009) (3)
Characterization of Unnecessary Computations in Web Applications (2019) (3)
Parade: A versatile parallel architecture for accelerating pulse train clustering (2009) (3)
Multi-objective Exploration for Practical Optimization Decisions in Binary Translation (2019) (3)
SIEVE: Speculative Inference on the Edge with Versatile Exportation (2020) (3)
Dynamic acceleration of multithreaded program critical paths in near-threshold systems (2012) (3)
Embracing heterogeneity with dynamic core boosting (2014) (3)
Extracting Statistical Loop-Level Parallelism using Hardware-Assisted Recovery (2007) (3)
SCULPTOR (2018) (2)
Low-Power Scientific Computing (2009) (2)
Putting Faulty Cores to Work (2010) (2)
Low Cost Transient Fault Protection Using Loop Output Prediction (2018) (2)
Scratch That (But Cache This): A Hybrid Register Cache/Scratchpad for GPUs (2018) (2)
Bitwidth Sensitive Code Generation in a Custom Embedded Accelerator Design System (2001) (2)
Embedded tutorial — Compilation techniques for CGRAs: Exploring all parallelization approaches (2010) (2)
Code and data partitioning for fine-grain parallelism (2007) (1)
Hardware/software mechanisms for increasing resource utilization on vliw/epic processors (2004) (1)
Cost-Sensitive Operation Partitioning for Synthesizing Custom Multicluster Datapath Architectures (1)
Message from the Program Chairs (2018) (1)
A Systematic Framework to Identify Violations of Scenario-dependent Driving Rules in Autonomous Vehicle Software (2021) (1)
Resource recycling: putting idle resources to work on a composable accelerator (2010) (1)
Approximating with Input Level Granularity (2015) (1)
Concurrency bugs in multithreaded software: modeling and analysis using Petri nets (2012) (0)
Colony of NPUs : Scaling the Efficiency of Neural Accelerators (2015) (0)
Sentinel Scheduling: A Model for Compiler-Controlled Execution Speculative (1993) (0)
An ultra low power SIMD processor for wireless devices (2010) (0)
Automatic Feature Isolation in Network Protocol Software Implementations (2020) (0)
Loner: utilizing the CPU vector datapath to process scalar integer data (2022) (0)
Reliability: Is it fortune or fallacy? (2007) (0)
Session details: New compiler optimizations (2011) (0)
Iterative Modulo Scheduling (2018) (0)
About the Author 4 Future Directions (2007) (0)
AS CHIP ARCHITECTS AND MANUFACTURERS PLUMB EVER-SMALLER PROCESS TECHNOLOGIES, NEW SPECIES OF FAULTS ARE COMPROMISING DEVICE RELIABILITY. (2007) (0)
COVER FE ATURE ELIMINATING CONCURRENCY BUGS WITH CONTROL ENGINEERING (0)
Session details: Compiler managed caches and memories (2010) (0)
AVMaestro: A Centralized Policy Enforcement Framework for Safe Autonomous-driving Environments (2022) (0)
Using Graphics Processing Units in an LTE Base Station (2014) (0)
ZerehCache: ArmoringCacheArchitecturesinHighDefect DensityTechnologies (2009) (0)
CPU-GPU Collaboration for Output Quality Monitoring Mehrzad Samadi and (2014) (0)
Program committee (2018) (0)
POSTER: Pairing Up CNNs for High Throughput Deep Learning (2019) (0)
Reducing the Cost of Protection against Soft Errors using Profile-Based Analysis (2012) (0)
Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2004, Washington DC, USA, September 22 - 25, 2004 (2004) (0)
Message from the Program Co-Chairs (2004) (0)
Message from the General Chairs (2007) (0)
Design in the Late-and Post-Silicon Eras (2008) (0)
SoftFusion: A Low-Cost Approach to Enhance Reliability of Object Detection Applications (2022) (0)
An Automatic System for Application-Specific Instruction Format Design and Code Generation for VLIW and EPIC processors (2002) (0)
Multi-Layer In-Memory Processing (2022) (0)
Baseband Processing Architectures for SDR (2009) (0)
Adaptive Cache Partitioning on a Composite Core (2015) (0)
Session details: Exploration, profiling and tuning of embedded systems (2008) (0)
Front matters (2013) (0)
for Reliable and High-Performance ComputingUniversity of IllinoisUrbana , IL 61801 (1992) (0)

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