Sharad Malik
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Engineering Computer Science
Sharad Malik's Degrees
- PhD Electrical Engineering Stanford University
- Masters Electrical Engineering Stanford University
Why Is Sharad Malik Influential?
(Suggest an Edit or Addition)Sharad Malik's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- Chaff: engineering an efficient SAT solver (2001) (3704)
- Power Analysis Of Embedded Software: A First Step Towards Software Power Minimization (1994) (1138)
- Efficient conflict driven learning in a Boolean satisfiability solver (2001) (893)
- Orion: a power-performance simulator for interconnection networks (2002) (822)
- System-Level Design: Orthogonalization of Concerns and Platform-Based Design (2001) (794)
- Performance Analysis of Embedded Software Using Implicit Path Enumeration (1995) (655)
- Instruction level power analysis and optimization of software (1996) (589)
- Logic verification using binary decision diagrams in a logic synthesis environment (1988) (520)
- Evaluating the security of logic encryption algorithms (2015) (503)
- Conflict-Driven Clause Learning SAT Solvers (2021) (473)
- Addressing the system-on-a-chip interconnect woes through communication-based design (2001) (405)
- Power-driven design of router microarchitectures in on-chip networks (2003) (401)
- The Quest for Efficient Boolean Satisfiability Solvers (2002) (354)
- Validating SAT solvers using an independent resolution-based checker: practical implementations and other applications (2003) (331)
- Algorithms for discrete function manipulation (1990) (307)
- Cache miss equations: a compiler framework for analyzing and tuning memory behavior (1999) (300)
- A Survey of Optimization Techniques Targeting Low Power VLSI Circuits (1995) (296)
- Power analysis and minimization techniques for embedded DSP software (1997) (289)
- On Solving the Partial MAX-SAT Problem (2006) (273)
- Cache modeling for real-time software: beyond direct mapped instruction caches (1996) (252)
- Efficient microarchitecture modeling and path analysis for real-time software (1995) (234)
- Conflict driven learning in a quantified Boolean satisfiability solver (2002) (225)
- Cache miss equations: an analytical representation of cache misses (1997) (224)
- Retiming and resynthesis: optimizing sequential networks with combinational techniques (1990) (222)
- Analysis of cyclic combinational circuits (1993) (206)
- Guarded evaluation: pushing power management to logic synthesis/design (1995) (203)
- Boolean satisfiability from theoretical hardness to practical success (2009) (196)
- Zchaff2004: An Efficient SAT Solver (2004) (177)
- Cha : Engineering an e cient SAT solver (2001) (170)
- Technology Mapping for Low Power (1993) (165)
- Compile-time dynamic voltage scaling settings: opportunities and limits (2003) (156)
- A power model for routers: modeling Alpha 21364 and InfiniBand routers (2002) (153)
- Performance estimation of embedded software with instruction cache modeling (1995) (150)
- Towards a Symmetric Treatment of Satisfaction and Conflicts in Quantified Boolean Formula Evaluation (2002) (141)
- From ASIC to ASIP: the next design discontinuity (2002) (141)
- Precise miss analysis for program transformations with caches of arbitrary associativity (1998) (132)
- Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver (2002) (126)
- Static Timing Analysis Of Embedded Software (1997) (125)
- Statistical timing analysis of combinational logic circuits (1993) (109)
- Reverse Engineering Digital Circuits Using Structural and Functional Analyses (2014) (109)
- Flexible and formal modeling of microprocessors with application to retargetable simulation (2003) (107)
- A technology-aware and energy-oriented topology exploration for on-chip networks (2005) (106)
- Performance analysis of real-time embedded software (1997) (105)
- Computation of floating mode delay in combinational circuits: theory and algorithms (1993) (97)
- Fast functional simulation using branching programs (1995) (97)
- Declarative Infrastructure Configuration Synthesis and Debugging (2008) (96)
- Memory bank and register allocation in software synthesis for ASIPs (1995) (96)
- Performance estimation of embedded software with instruction cache modeling (1999) (93)
- Accelerating Boolean satisfiability with configurable hardware (1998) (87)
- Certified timing verification and the transition delay of a logic circuit (1992) (85)
- Is redundancy necessary to reduce delay? (1990) (85)
- Boolean Satisfiability Solvers and Their Applications in Model Checking (2015) (84)
- Reverse engineering digital circuits using functional analysis (2013) (81)
- Permutation and phase independent Boolean comparison (1993) (80)
- Optimal code generation for embedded memory non-homogeneous register architectures (1995) (80)
- WordRev: Finding word-level structures in a sea of bit-level gates (2013) (80)
- Malware detection using machine learning based analysis of virtual memory access patterns (2017) (77)
- A hierarchical modeling framework for on-chip communication architectures [SOC] (2002) (75)
- Delay computation in combinational logic circuits: theory and algorithms (1991) (73)
- Constrained Sampling and Counting: Universal Hashing Meets SAT Solving (2015) (71)
- Power analysis and low-power scheduling techniques for embedded DSP software (1995) (66)
- Hardware Trojan detection for gate-level ICs using signal correlation based clustering (2015) (65)
- On computing minimal independent support and its applications to sampling and counting (2015) (64)
- Simultaneous reference allocation in code generation for dual data memory bank ASIPs (2000) (63)
- Limits of Using Signatures for Permutation Independent Boolean Comparison (1995) (63)
- Post-silicon fault localisation using maximum satisfiability and backbones (2011) (60)
- Using reconfigurable computing techniques to accelerate problems in the CAD domain: a case study with Boolean satisfiability (1998) (59)
- Code Generation and Optimization Techniques for Embedded Digital Signal Processors (1996) (58)
- Partition-based decision heuristics for image computation using SAT and BDDs (2001) (58)
- Using configurable computing to accelerate Boolean satisfiability (1999) (58)
- Exact memory size estimation for array computations without loop unrolling (1999) (55)
- Retargetable static timing analysis for embedded software (2001) (54)
- Using register-transfer paths in code generation for heterogeneous memory-register architectures (1996) (53)
- A formal concurrency model based architecture description language for synthesis of software development tools (2004) (53)
- Cache Performance of SAT Solvers: a Case Study for Efficient Implementation of Algorithms (2003) (51)
- Processor evaluation in an embedded systems design environment (2000) (51)
- Complementary use of runtime validation and model checking (2005) (50)
- Searching for truth: techniques for satisfiability of boolean formulas (2003) (49)
- Abstractions for model checking SDN controllers (2013) (49)
- Managing dynamic reconfiguration overhead in systems-on-a-chip design using reconfigurable datapaths and optimized interconnection networks (2001) (48)
- Incremental CAD (2000) (47)
- Intraprogram dynamic voltage scaling: Bounding opportunities with analytic modeling (2004) (46)
- Template-based circuit understanding (2014) (46)
- Computation of floating mode delay in combinational circuits: practice and implementation (1993) (46)
- Instruction set design and optimizations for address computation in DSP architectures (1996) (45)
- Developing Architectural Platforms: A Disciplined Approach (2002) (45)
- Toward Formalizing A Validation Methodology Using Simulation Coverage (1997) (45)
- An assertion language for debugging SDN applications (2014) (45)
- Solving Boolean Satisfiability with Dynamic Hardware Configurations (1998) (44)
- Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications (1994) (44)
- The Liberty Simulation Environment: A deliberate approach to high-level system modeling (2006) (43)
- Solving the Minimum-Cost Satisfiability Problem Using SAT Based Branch-and-Bound Search (2006) (43)
- Bounds on power savings using runtime dynamic voltage scaling: an exact algorithm and a linear-time heuristic approximation (2005) (42)
- Modeling and integration of peripheral devices in embedded systems (2003) (42)
- Morpheus: A Vulnerability-Tolerant Secure Architecture Based on Ensembles of Moving Target Defenses with Churn (2019) (40)
- A Comparative Study of 2QBF Algorithms (2004) (40)
- Runtime validation of memory ordering using constraint graph checking (2008) (40)
- Verifying information flow properties of firmware using symbolic execution (2016) (39)
- Code optimization libraries for retargetable compilation for embedded digital signal processors (1998) (39)
- Statistical timing analysis of combinational circuits (1992) (38)
- Engineering a (super?) efficient sat solver (2001) (38)
- Extracting Logic Circuit Structure from Conjunctive Normal Form Descriptions (2007) (37)
- Validating the result of a quantified Boolean formula (QBF) solver: theory and practice (2005) (37)
- The case for retiming with explicit reset circuitry (1996) (36)
- Extracting small unsatis able cores from unsatis able boolean formulas (2003) (36)
- Exact memory size estimation for array computations (2000) (36)
- Performance analysis of embedded software using implicit path enumeration (1995) (36)
- Dynamic power management for microprocessors: a case study (1997) (35)
- Challenges and Solutions for Late- and Post-Silicon Design (2008) (35)
- The design of dynamically reconfigurable datapath coprocessors (2004) (35)
- Exploiting operation level parallelism through dynamically reconfigurable datapaths (2002) (34)
- Architecture Description Languages for Retargetable Compilation (2007) (34)
- An Adaptable Rule Placement for Software-Defined Networks (2014) (33)
- Logic Verification Using BDDs in a Logic Synthesis Environ-ment (1988) (32)
- MIS-MV: optimization of multi-level logic with multiple-values inputs (1990) (32)
- Handling irregular ILP within conventional VLIW schedulers using artificial resource constraints (2000) (32)
- Predictive analysis for detecting serializability violations through Trace Segmentation (2011) (32)
- Challenges in code generation for embedded processors (1994) (31)
- Event suppression: improving the efficiency of timing simulation for synchronous digital circuits (1994) (31)
- Considering circuit observability don't cares in CNF satisfiability (2005) (31)
- Verification and synthesis of firewalls using SAT and QBF (2012) (31)
- Accelerating Boolean satisfiability through application specific processing (2001) (30)
- Extracting useful computation from error-prone processors for streaming applications (2013) (30)
- Datapath merging and interconnection sharing for reconfigurable architectures (2002) (29)
- SAT-based techniques for determining backbones for post-silicon fault localisation (2011) (29)
- Functional timing analysis using ATPG (1993) (28)
- B L F-M V An Interchange Format for Design Verification and Synthesis (1991) (28)
- Exploiting multicycle false paths in the performance optimization of sequential logic circuits (1992) (27)
- Efficient behavior-driven runtime dynamic voltage scaling policies (2005) (27)
- Modeling and description of embedded processors for the development of software tools (2004) (27)
- Optimal Live Range Merge for Address Register Allocation in Embedded Programs (2001) (26)
- Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis (1993) (26)
- Synthesizing operating system based device drivers in embedded systems (2003) (26)
- All-SAT Using Minimal Blocking Clauses (2014) (25)
- Automated cache optimizations using CME driven diagnosis (2000) (25)
- Template-based synthesis of instruction-level abstractions for SoC verification (2015) (25)
- Symbolic minimization of multilevel logic and the input encoding problem (1992) (25)
- SAT Based Verification of Network Data Planes (2013) (24)
- Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification (2018) (24)
- Performance optimization of pipelined circuits (1990) (24)
- Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation (2004) (24)
- Runtime checking of serializability in software transactional memory (2010) (24)
- Automated synthesis of efficient binary decoders for retargetable software toolkits (2003) (24)
- Verification of asynchronous interface circuits with bounded wire delays (1992) (24)
- Verification of Computer Switching Networks: An Overview (2012) (23)
- Statistical Delay Modeling in Logic Design and Synthesis (1994) (22)
- Using Complete-1-Distinguishability for FSM equivalence checking (2001) (22)
- Towards a symmetric treatment of satisfaction and conflicts in QBF (2002) (21)
- Code generation for fixed-point DSPs (1998) (21)
- Performance Analysis of Embedded Systems (1996) (21)
- Formal Security Verification of Concurrent Firmware in SoCs using Instruction-Level Abstraction for Hardware* (2018) (20)
- A disciplined approach to the development of platform architectures (2002) (20)
- Lemma Learning in SMT on Linear Constraints (2006) (20)
- Towards symmetric treatment of con?icts and satisfaction in quanti-fied Boolean satisfiability solv (2002) (20)
- Statistical timing optimization of combinational logic circuits (1993) (20)
- Analysis of Search Based Algorithms for Satisfiability of Quantified Boolean Formulas Arising from Circuit State Space Diameter Problems (2004) (19)
- Combinational logic optimization techniques in sequential logic synthesis (1991) (18)
- Technology mapping for low power in logic synthesis (1996) (18)
- Propositional SAT Solving (2018) (17)
- SAT and ATPG: algorithms for Boolean decision problems (2001) (16)
- CommGuard: Mitigating Communication Errors in Error-Prone Parallel Execution (2015) (16)
- A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism (2001) (16)
- Application of BDDs in Boolean matching techniques for formal logic combinational verification (2001) (16)
- Fast Interpolating BMC (2015) (15)
- EPROF: An energy/performance/reliability optimization framework for streaming applications (2012) (15)
- Verification Driven Formal Architecture and Microarchitecture Modeling (2007) (14)
- Exploiting multi-cycle false paths in the performance optimization of sequential circuits (1992) (14)
- Automated firmware testing using firmware-hardware interaction patterns (2014) (14)
- Instruction level power analysis (1996) (14)
- Lazy Self-composition for Security Verification (2018) (14)
- Optimization of embedded DSP programs using post-pass data-flow analysis (1997) (13)
- Runtime Validation of Transactional Memory Systems (2008) (13)
- Silicon fault diagnosis using sequence interpolation with backbones (2014) (13)
- Matching architecture to application via configurable processors: a case study with boolean satisfiability problem (2001) (12)
- New Features of the SAT ’ 04 versions of zChaff Zhaohui (2004) (12)
- Predicting Serializability Violations: SMT-Based Search vs. DPOR-Based Search (2011) (12)
- Delay abstraction in combinational logic circuits (1995) (12)
- Retiming and Resynthesis: Optimizing Sequential Networks with (1990) (12)
- Using a communication architecture specification in an application-driven retargetable prototyping platform for multiprocessing (2004) (12)
- Invited: Specification and modeling for Systems-on-Chip security verification (2016) (11)
- Microarchitecture modeling for design-space exploration (2004) (11)
- Template-Based Parameterized Synthesis of Uniform Instruction-Level Abstractions for SoC Verification (2018) (11)
- Power analysis of the intel 486dx2 (1994) (11)
- Cache modeling and path analysis for real-time software (1996) (11)
- Retargetable Very Long Instuction Word Compiler Framework for Digital Signal Processors. (2002) (11)
- Retiming and Resynthesis: Optimizing Sequential Circuits Using Combinational Techniques (1991) (10)
- Boolean Satisfiability Solvers: Techniques and Extensions (2012) (10)
- Establishing latch correspondence for sequential circuits using distinguishing signatures (1997) (10)
- Parallel assertions for debugging parallel programs (2011) (10)
- Synthesizing Environment Invariants for Modular Hardware Verification (2020) (10)
- Exploiting Retiming in a Guided Simulation Based Validation Methodology (1999) (10)
- Asynchronous circuit design for VLSI signal processing (1994) (10)
- Achieving Structural and Composable Modeling of Complex Systems (2004) (9)
- A Study of Architecture Description Languages from a Model-based Perspective (2005) (9)
- Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor (1999) (8)
- Test generation for cyclic combinational circuits (1995) (8)
- Instruction-Level Abstraction (ILA) (2018) (8)
- Modeling Firmware as Service Functions and Its Application to Test Generation (2013) (8)
- Design Tools for Application Specific Embedded Processors (2002) (8)
- Analysis of Search Based Algorithms for Satisfiability of Propositional and Quantified Boolean Formulas Arising from Circuit State Space Diameter Problems (2004) (8)
- IC3 - Flipping the E in ICE (2017) (8)
- Retargatable static software timing analysis (2001) (7)
- Cache modeling for real-time software (1997) (7)
- Computer Aided Verification, 20th International Conference, CAV 2008, Princeton, NJ, USA, July 7-14, 2008, Proceedings (2008) (7)
- A Formal Instruction-level GPU Model for Scalable Verification (2018) (7)
- Cinderella: A Retargetable Environment for Performance Analysis of Real-Time Software (1997) (7)
- Reduction of Resolution Refutations and Interpolants via Subsumption (2014) (7)
- ILA-MCM: Integrating Memory Consistency Models with Instruction-Level Abstractions for Heterogeneous System-on-Chip Verification (2018) (7)
- Model checking unbounded concurrent lists (2013) (6)
- Symmetry Reduction in SAT-Based Model Checking (2005) (6)
- Detecting hardware trojans: a tale of two techniques (2015) (6)
- Error-tolerant processors: Formal specification and verification (2015) (6)
- Efficient predictive analysis for detecting nondeterminism in multi-threaded programs (2012) (6)
- Reverse Engineering Digital ICs through Geometric Embedding of Circuit Graphs (2018) (6)
- Implementing Boolean Satisfiability in Configurable Hardware (1997) (6)
- Specification and synthesis of hardware checkpointing and rollback mechanisms (2012) (6)
- A synthesis-based test generation and compaction algorithm for multifaults (1991) (6)
- Towards eliminating configuration errors in cyber infrastructure (2011) (6)
- Automating Hazard Checking in Transaction-Level Microarchitecture Models (2007) (6)
- A Retargetable Compilation Methodology for Embedded Digital Signal Processors Using a Machine-Dependent Code Optimization Library (1999) (5)
- Wolverine: Battling Bugs with Interpolants - (Competition Contribution) (2012) (5)
- Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation (2006) (5)
- A Disciplined Approach to the Development of Architectural Platforms (2002) (5)
- ILAng: A Modeling and Verification Platform for SoCs Using Instruction-Level Abstractions (2019) (5)
- Syntax-Guided Synthesis for Lemma Generation in Hardware Model Checking (2021) (5)
- In-Band Update for Network Routing Policy Migration (2014) (5)
- Coverage-Based Trace Signal Selection for Fault Localisation in Post-silicon Validation (2012) (5)
- Solving Quantified Boolean Formulas with Circuit Observability Don't Cares (2006) (5)
- Software tools for modeling and simulation of on-chip communication architectures (2005) (5)
- Solving Boolean Satissability with Dynamic Hardware Conngurations (1998) (5)
- Engineering a Highly E cient SAT Solver (2001) (4)
- Using Recon gurable Computing Techniques to Accelerate Problems in the CAD Domain : A Case Study with Boolean Satis ability (1998) (4)
- Prediction of interconnect delay in logic synthesis (1995) (4)
- A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs (2007) (4)
- COMBINING MULTI-LEVEL DECOMPOSITION AND TOPOLOGICAL PARTITIONING FOR PLAS. (1987) (4)
- Completeness bounds and sequentialization for model checking of interacting firmware and hardware (2015) (4)
- Guest Editors' Introduction: Exploring Synergies for Design Verification (2004) (4)
- Solving linear arithmetic with SAT-based model checking (2017) (4)
- zChaff SAT Solver (2006) (4)
- Using complete-1-distinguishability for FSM equivalence checking (1996) (4)
- Supporting RTL flow compatibility in a microarchitecture-level design framework (2009) (3)
- Revealing Cluster Hierarchy in Gate-level ICs Using Block Diagrams and Cluster Estimates of Circuit Embeddings (2019) (3)
- Formal security verification of concurrent firmware in SoCs using instruction-level abstraction for hardware (2018) (3)
- Chaff: A Fast SAT Solver for EDA Applications (2001) (3)
- Parameterized Model Checking of Fine Grained Concurrency (2012) (3)
- Using Flow Specifications of Parameterized Cache Coherence Protocols for Verifying Deadlock Freedom (2014) (3)
- Proceedings of the 20th international conference on Computer Aided Verification (2008) (3)
- Register Allocation for Indirect Addressing in Loops Register Allocation for Indirect Addressing in Loops (1998) (3)
- Optimizing dynamic trace signal selection using machine learning and linear programming (2015) (2)
- Leveraging Processor Modeling and Verification for General Hardware Modules (2021) (2)
- A Case for Runtime Validation of Hardware (2005) (2)
- Permutation and phase independent boolean matching (1993) (2)
- Parallel Streaming Computation on Error-Prone Processors (2014) (2)
- Formal Methods in System Design: Preface (2009) (2)
- passert: A Tool for Debugging Parallel Programs (2012) (2)
- Implicit enumeration techniques applied to asynchronous circuit verification (1993) (2)
- Exploiting Circuit Reconvergence through Static Learning in CNF SAT Solvers (2008) (2)
- Sparse Matrix to Matrix Multiplication: A Representation and Architecture for Acceleration (2019) (2)
- Runtime Verification: A Computer Architecture Perspective (2011) (2)
- Paged Absolute Addressing Mode Optimizations for Embedded Digital Signal Processors Using Post-pass Data-flow Analysis (1999) (2)
- Evaluating matrix representations for error-tolerant computing (2017) (2)
- Generating Architecture-Level Abstractions from RTL Designs for Processors and Accelerators Part I: Determining Architectural State Variables (2021) (1)
- Utility of transaction-level hardware models in refinement checking (2010) (1)
- Using the IMPACT VLIW compiler framework to implement a compiler for a fixed point DSP (2001) (1)
- Software-driven Security Attacks: From Vulnerability Sources to Durable Hardware Defenses (2021) (1)
- Embedded systems education (panel session) (abstract only) (2000) (1)
- Boolean Satisfiability: Creating Solvers Optimized for Specific Problem Instances (2008) (1)
- MADL—An ADL Based on a Formal and Flexible Concurrency Model (2008) (1)
- Specification and encoding of transaction interaction properties (2011) (1)
- Parallel Assertions for Architectures with Weak Memory Models (2012) (1)
- Automatic Generation of Architecture-Level Models from RTL Designs for Processors and Accelerators (2022) (1)
- Understanding the Dynamic Behavior of Modern DPLL SAT Solvers through Visual Analysis (2006) (1)
- Timing Analysis of Combinational Logic Circuits (1993) (1)
- Boolean Satisfiability: Solvers and Extensions (2014) (1)
- Conflict driven learning in a QBF (2002) (1)
- Assertions for debugging parallel programs (2013) (1)
- Performing estimation of embed-ded software within instruction cache modeling (1995) (1)
- MemFlow: Memory-driven data scheduling with datapath co-design in accelerators for large-scale inference applications (2018) (1)
- Post-Silicon Fault Localization with Satisfiability Solvers (2018) (1)
- Hardware Verification: Techniques, Methodology and Solutions (2008) (1)
- Vulnerability-Tolerant Secure Architectures (2018) (1)
- Proceedings of the 14th Conference on Formal Methods in Computer-Aided Design (2014) (1)
- Program Path Analysis (1999) (0)
- Compositional Verification Using a Formal Component and Interface Specification (2022) (0)
- Embedded systems education (panel abstract). (2000) (0)
- Building AVerification TestPlan: Trading BruteForceForFinesse (2006) (0)
- 8-760 Fall'01 Vlsi Cad Paper Review 2 1.0 Intent 2.0 Objectives (0)
- A Retargetable Timing Analysis Tool — Cinderella (1999) (0)
- Specialized Accelerators and Compiler Flows: Replacing Accelerator APIs with a Formal Software/Hardware Interface (2022) (0)
- Software Performance Evaluation (1999) (0)
- From DSLs to Accelerator-Rich Platform Implementations: Addressing the Mapping Gap (2021) (0)
- Usage-Based RTL Subsetting for Hardware Accelerators (2022) (0)
- CNNFlow: Memory-Driven Data Flow Optimization for Convolutional Neural Networks (2022) (0)
- A Tool for Debugging Parallel Programs (2012) (0)
- PPU (2017) (0)
- Effective abstraction for response proof of communication fabrics (2014) (0)
- Facilitating Reuse in Hardware Models with Enhanced Type Inference (2004) (0)
- Related Work in Timing Analysis for Embedded Software (1999) (0)
- Report on NSF Workshop on Symbolic Computation for Constraint Satisfaction November 14 , 2008 (2008) (0)
- Preface (2009) (0)
- Trace-based Analysis of Memory Corruption Malware Attacks (2017) (0)
- Modeling Operation and Microarchitecture Concurrency Retargetable Simulation for Communication Architectures wit pplication to (2004) (0)
- Augmenting SAT Solvers for Network Configuration/Planning (2006) (0)
- Solving Constraints over Bit-Vectors with SAT-based Model Checking (2017) (0)
- Symbolic Minimization of Multilevel Logic and the (1992) (0)
- New frontiers in logic synthesis: a report on IWLS 89 (1990) (0)
- 3 Transaction Interaction Patterns and Test Generation : Previous Work 2 . 3 . 1 Avoiding All Interleavings (2014) (0)
- Verifying Security Properties in Modern SoCs Using Instruction-Level Abstractions (2017) (0)
- Model checking unbounded concurrent lists (2015) (0)
- 33 . 1 Chaff : Engineering an (2004) (0)
- Retargetable Very Long Instuction Word Compiler Framework for Digital Signal Processors (2002) (0)
- ZCha 2004: An e cient SAT solver (2004) (0)
- Register Transfer Level Synthesis: From Theory to Practice (1996) (0)
- Unified tools for SoC embedded systems: mission critical, mission impossible or mission irrelevant? (2002) (0)
- MemFlow: Memory-Driven Data Scheduling With Datapath Co-Design in Accelerators for Large-Scale Inference Applications (2020) (0)
- Optimizing and bounding software-controlled dynamic voltage/frequency scaling: analysis for uniprocessors and multiprocessors (2006) (0)
- Conflict Driven Learning in a Quantified Booleain (2002) (0)
- PPU: A Control Error-Tolerant Processor for Streaming Applications with Formal Guarantees (2017) (0)
- SpFlow: Memory-Driven Data Flow Optimization for Sparse Matrix-Matrix Multiplication (2019) (0)
- Embedded Software Implementation Tools for Fully Programmable Application Specific Systems (2001) (0)
- Encoding Symbolic Inputs for Multi-Level Logic Implementation (2015) (0)
- CAD Techniques for Embedded System Design (1999) (0)
- Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models (2022) (0)
- Dependable Multithreaded Processing Using Runtime Validation (2006) (0)
- Statistical Information Processing Extending the Limits of Approximate Computing ∗ (2015) (0)
- A Multiple-level Logic Optimization System. Ieee Transactions on Com- Karon] Kevin Karplus. Using If-then-else Dags for Multi-levellogic Minimization. Ieee Trans- Actions on Computer-aided Design of Integrated Circuits and Systems, in Preparation. Km90] Kevin Karplus and Dipen Moitra. Using Dominato (1989) (0)
- On computing minimal independent support and its applications to sampling and counting (2015) (0)
- The Gigascale Systems Research Center (GSRC) - Addressing the Information-System Platform Design Challenges for the Late- and Post- (2010) (0)
- Code Generation for Dual-load-execute Architectures Code Generation for Dual-load-execute Architectures (1997) (0)
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What Schools Are Affiliated With Sharad Malik?
Sharad Malik is affiliated with the following schools:
