Shekhar Y. Borkar
#163,681
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Shekhar Y. Borkar's AcademicInfluence.com Rankings
Shekhar Y. Borkarengineering Degrees
Engineering
#7155
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#8518
Historical Rank
Electrical Engineering
#2208
World Rank
#2314
Historical Rank
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Engineering
Shekhar Y. Borkar's Degrees
- PhD Electrical Engineering Stanford University
- Masters Electrical Engineering Stanford University
Why Is Shekhar Y. Borkar Influential?
(Suggest an Edit or Addition)Shekhar Y. Borkar's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- Parameter variations and impact on circuits and microarchitecture (2003) (1526)
- Designing reliable systems from unreliable components: the challenges of transistor variability and degradation (2005) (1416)
- Design challenges of technology scaling (1999) (1247)
- An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS (2008) (739)
- A 5-GHz Mesh Interconnect for a Teraflops Processor (2007) (695)
- Area-efficient linear regulator with ultra-fast load regulation (2005) (532)
- The future of microprocessors (2011) (477)
- Scaling of stack effect and its application for leakage reduction (2001) (409)
- A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling (2011) (408)
- iWarp: an integrated solution to high-speed parallel computing (1988) (397)
- Thousand Core ChipsA Technology Perspective (2007) (376)
- Technology and design challenges for low power and high performance (1999) (363)
- A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package (2005) (317)
- Dynamic-sleep transistor and body bias for active leakage power control of microprocessors (2003) (316)
- Design and reliability challenges in nanometer technologies (2004) (237)
- Platform 2015: Intel ® Processor and Platform Evolution for the Next Decade (2005) (236)
- A sub-130-nm conditional keeper technique (2002) (227)
- Supporting systolic and memory communication in iWarp (1990) (215)
- A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS (2012) (212)
- Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs (2001) (198)
- Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors (2001) (185)
- Forward body bias for microprocessors in 130nm technology generation and beyond (2002) (177)
- Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-/spl mu/m to 90-nm generation (2003) (173)
- Microarchitecture and Design Challenges for Gigascale Integration (2004) (160)
- Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-/spl mu/m CMOS (2004) (156)
- Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor (2011) (139)
- Scaling trends of cosmic ray induced soft errors in static latches beyond 0.18 /spl mu/ (2001) (137)
- Design perspectives on 22nm CMOS and beyond (2009) (136)
- A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS (2004) (135)
- Sub-90 nm technologies-challenges and opportunities for CAD (2002) (134)
- Circuit techniques for dynamic variation tolerance (2009) (133)
- A 4 GHz 130 nm address generation unit with 32-bit sparse-tree adder core (2002) (128)
- Life is CMOS: why chase the life after? (2002) (127)
- Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's (1999) (122)
- Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors (2002) (110)
- High-performance and low-power challenges for sub-70 nm microprocessor circuits (2002) (107)
- Runnemede: An architecture for Ubiquitous High-Performance Computing (2013) (102)
- DOE Advanced Scientific Computing Advisory Subcommittee (ASCAC) Report: Top Ten Exascale Research Challenges (2014) (101)
- 3D integration for energy efficient system design (2006) (100)
- Electronics beyond nano-scale CMOS (2006) (99)
- A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS (2005) (94)
- Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swapped-body biasing technique (2004) (93)
- A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits (2006) (93)
- Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process (2003) (91)
- A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS (2009) (86)
- The Exascale challenge (2010) (81)
- Selective node engineering for chip-level soft error rate improvement [in CMOS] (2002) (78)
- A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file (2002) (78)
- Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS (2002) (78)
- 2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology (2009) (76)
- Thousand-Core Chips [Roundtable] (2008) (76)
- Technology and design challenges for low power and high performance [microprocessors] (1999) (72)
- Dual-VT SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.13 μm technology generation (2000) (67)
- Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor (2010) (62)
- Exascale Computing - A Fact or a Fiction? (2013) (59)
- A 900 Mb/s bidirectional signaling scheme (1995) (55)
- Circuit techniques for subthreshold leakage avoidance, control and tolerance (2004) (52)
- Role of Interconnects in the Future of Computing (2013) (51)
- Microprocessors in the Era of Terascale Integration (2007) (51)
- A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS (2014) (50)
- A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS (2009) (47)
- Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache (2002) (47)
- Variation Tolerance in a Multichannel Carbon-Nanotube Transistor for High-Speed Digital Circuits (2009) (46)
- Self calibrating circuit design for variation tolerant VLSI systems (2005) (44)
- A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS (2012) (42)
- Low power design challenges for the decade (invited talk) (2001) (41)
- Dual supply voltage clocking for 5 GHz 130 nm integer execution core (2002) (40)
- A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS (2010) (40)
- A 320mV 56μW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS (2008) (39)
- A transition-encoded dynamic bus technique for high-performance interconnects (2002) (38)
- A conditional keeper technique for sub-0.13/spl mu/ wide dynamic gates (2001) (38)
- A 25 GHz 32 b integer-execution core in 130 nm dual-V/sub T/ CMOS (2002) (37)
- A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme (2003) (36)
- Tackling variability and reliability challenges (2006) (35)
- Low power and high performance design challenges in future technologies (2000) (35)
- Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies (2003) (35)
- Future of interconnect fabric: a contrarian view (2010) (31)
- Full-chip subthreshold leakage power prediction model for sub-0 . 18 m CMOS (2002) (31)
- Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process (2003) (30)
- Statistical design for variation tolerance: key to continued Moore's law (2004) (30)
- On the Role of Co-design in High Performance Computing (2012) (29)
- 2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process (2008) (28)
- Getting Gigascale Chips (2003) (25)
- A 1.9 Gb/s 358 mW 16–256 State Reconfigurable Viterbi Accelerator in 90 nm CMOS (2008) (23)
- Bitline leakage equalization for sub-100nm caches (2003) (23)
- A 300mV 494GOPS/W reconfigurable dual-supply 4-Way SIMD vector processing accelerator in 45nm CMOS (2009) (22)
- A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOS (2010) (22)
- Teraflops prototype processor with 80 cores (2007) (21)
- A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS (2012) (21)
- A 6.5 GHz 130 nm single-ended dynamic ALU and instruction-scheduler loop (2002) (21)
- A 4GHz 300mW 64b integer execution ALU with dual supply voltages in 90nm CMOS (2004) (19)
- How to stop interconnects from hindering the future of computing! (2013) (18)
- An 8.8GHz 198mW 16x64b 1R/1W variationtolerant register file in 65nm CMOS (2006) (18)
- 16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS (2014) (18)
- Exponential Challenges, Exponential Rewards - The future of Moore's Law (2004) (18)
- A low-leakage dynamic multi-ported register file in 0.13mm CMOS (2001) (18)
- Impact of body bias on alpha- and neutron-induced soft error rates of flip-flops (2004) (16)
- On-die CMOS leakage current sensor for measuring process variation in sub-90nm generations (2005) (16)
- A 64-state 2GHz 500Mbps 40mW Viterbi accelerator in 90nm CMOS (2004) (15)
- An area-efficient, integrated, linear regulator with ultra-fast load regulation (2004) (15)
- Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS (2014) (14)
- Design challenges for 22nm CMOS and beyond (2009) (13)
- VLSI Design Challenges for Gigascale Integration (2005) (12)
- Comparative performance, leakage power and switching power of circuits in 150 nm PD-SOI and bulk technologies including impact of SOI history effect (2001) (12)
- Planar 1T-cell DRAM with MOS storage capacitors in a 130nm logic technology for high density microprocessors caches (2002) (11)
- A 6.5GHz 54mW 64-bit Parity-Checking Adder for 65nm Fault-Tolerant Microprocessor Execution Cores (2007) (11)
- A 110GOPS/W 16b multiplier and reconfigurable PLA loop in 90nm CMOS (2005) (10)
- Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration (2011) (10)
- A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems (2004) (10)
- 3D integration technology for energy efficient system design (2010) (9)
- A 2.9Tb/s 8W 64-core circuit-switched network-on-chip in 45nm CMOS (2008) (9)
- A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS (2012) (8)
- An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS (2005) (8)
- A 0.13um 6GHz 256x32b Leakage-tolerant Register File (2001) (8)
- Dual-V/sub T/ SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.13 /spl mu/m technology generation (2000) (8)
- Power management and delivery for high-performance microprocessors (2013) (7)
- Tomorrow's analog: just dead or just different? (2006) (7)
- Comparative delay, noise and energy of high-performance domino adders with stack node preconditioning (SNP) (2000) (7)
- A burn-in tolerant dynamic circuit technique (2002) (7)
- A 233MHz, 80-87% efficient, integrated, 4-phase DC-DC converter in 90nm CMOS (2004) (6)
- A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOS (2012) (5)
- An ultra-dense irradiation test structure with a NAND/NOR readout chain for characterizing soft error rates of 14nm combinational logic circuits (2017) (5)
- Achieving energy efficiency by HW/SW co-design (2013) (5)
- Statistical characterization of radiation-induced pulse waveforms and flip-flop soft errors in 14nm tri-gate CMOS using a back-sampling chain (BSC) technique (2017) (5)
- Extreme Energy Efficiency by Near Threshold Voltage Operation (2016) (4)
- A low-leakage dynamic multi-ported register file in 0.13 /spl mu/m CMOS (2001) (4)
- Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections (2011) (4)
- Theory of Multi-tube Carbon Nanotube Transistors for High Speed Variation-Tolerant Circuits (2008) (4)
- The semiconductor industry in 2025. (2010) (4)
- Traleika Glacier: A hardware-software co-designed approach to exascale computing (2017) (4)
- EP2: The semiconductor industry in 2025 (2010) (4)
- Resiliency for many-core system on a chip (2014) (3)
- A 0.13 /spl mu/m 6 GHz 256/spl times/32b leakage-tolerant register file (2001) (3)
- A 1.9Gb/s 358mW 16-to-256 State Reconfigurable Viterbi Accelerator in 90nm CMOS (2007) (3)
- Introduction to panel discussion Probabilistic & statistical design - the wave of the future (2006) (3)
- Nanometer design: place your bets (2003) (3)
- A low-swing single-ended L1 cache bus technique for sub-90nm technologies (2004) (3)
- Advanced circuit techniques for high-performance microprocessor and low-power DSPs (2004) (2)
- Probabilistic amp; Statistical Design - the Wave of the Future (2006) (2)
- Fault Management Workshop Final Report, August 13, 2012 (2012) (2)
- 2010 International Symposium on VLSI Design, Automation and Test (2010) (2)
- Feasibility of current measurements in sub 0.25-micron VLSIs (2000) (2)
- Future of on-chip interconnection architectures (2007) (2)
- Instruction-Scheduler Loop (2002) (1)
- 3DICs for tera-scale computing: a case study (2011) (1)
- Custom is from Venus and synthesis from Mars (2008) (1)
- Want to be a bug buster? Technical perpective (2010) (1)
- High performance design with advanced features in 22nm and beyond (2010) (1)
- Full-chip sub-threshold leakage power prediction model for sub-0.18 /spl mu/m CMOS (2002) (1)
- Is statistical timing statistically significant? (2004) (0)
- Centip3De demonstrates more than Moore…: technical perspective (2013) (0)
- Low Power Pulsed Flip-Flop using Self Driven Pass Transistor Logic (2020) (0)
- Circuits evening panel discussion 1: Is university circuit design research and education keeping up with industry needs? (2015) (0)
- Session 18 overview: Innovative circuits in emerging technologies: Technology directions subcommittee (2012) (0)
- Technical Perspective Want to be a Bug Buster (2010) (0)
- Energy-efficient Management of Reconfigurable Computers 2.1 Overview (2016) (0)
- 2015 Salishan Final Program (2015) (0)
- EP3: Empowering the killer SoC applications of 2020 (2013) (0)
- Panel: Is Nanometer Design Under Control? (2001) (0)
- Is nanometer design under control? (panel session) (2001) (0)
- Design of Efficient Low Power Stable 4-Bit Memory Cell (2020) (0)
- Leakage control and tolerance challenges for sub-0.1μm microprocessor circuits (2001) (0)
- Statistical characterization of radiation-induced pulse waveforms and flip-flop soft errors in 14nm tri-gate CMOS using a back-sampling chain (BSC) technique (2017) (0)
- Wednesday Keynote Address (2005) (0)
- Scaling Theory Frequency-scaling Trends (performance) (1999) (0)
- Tomorrow's Analog: JustDeadorJustDifferent? (2006) (0)
- Traileka Glacier X-Stack. Final Scientific/Technical Report (2015) (0)
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