Sorin Coțofană

Q: What Schools Are Affiliated With Sorin Coțofană

Sorin Coțofană is affiliated with the following schools: Politehnica University of Bucharest, Delft University of Technology, University of Bucharest

Sorin Coțofană's AcademicInfluence.com Rankings

Sorin Coțofană

Engineering

#7602

World Rank

#8991

Historical Rank

engineering Degrees

Sorin Coțofană

Computer Science

#10311

World Rank

#10820

Historical Rank

Computer Engineering

#156

World Rank

#158

Historical Rank

Database

#8296

World Rank

#8670

Historical Rank

computer-science Degrees

Download Badge

Engineering
Computer Science

Sorin Coțofană's Degrees

Bachelors Computer Engineering Politehnica University of Bucharest
Masters Computer Engineering Politehnica University of Bucharest
PhD Computer Engineering Politehnica University of Bucharest

Why Is Sorin Coțofană Influential?

(Suggest an Edit or Addition)

According to Wikipedia, Sorin Coțofană is a Quantum & Computer engineering Professor at Delft University of Technology. He was named a Fellow of the Institute of Electrical and Electronics Engineers in 2017 for contributions to nanocomputing architectures and paradigms.

(See a Problem?)

Sorin Coțofană's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Introduction to spin wave computing (2020) (116)
The 2021 Magnonics Roadmap (2021) (114)
A linear threshold gate implementation in single electron technology (2001) (113)
A sum of absolute differences implementation in FPGA hardware (2002) (82)
Single electron encoded latches and flip-flops (2004) (82)
The MOLEN ρμ-coded processor (2001) (80)
The MOLEN rho-mu-Coded Processor (2001) (75)
A unified aging model of NBTI and HCI degradation towards lifetime reliability management for nanoscale MOSFET circuits (2011) (67)
Addition related arithmetic operations via controlled transport of charge (2005) (59)
A magnonic directional coupler for integrated magnonic half-adders (2019) (56)
2-1 Additions and Related Arithmetic Operations with Threshold Logic (1996) (46)
Static buffered SET based logic gates (2002) (44)
Field-Programmable Custom Computing Machines - A Taxonomy - (2002) (42)
Statistical reliability analysis of NBTI impact on FinFET SRAMs and mitigation technique using independent-gate devices (2012) (36)
Advances in Magnetics Roadmap on Spin-Wave Computing (2021) (35)
Periodic symmetric functions, serial addition, and multiplication with neural networks (1998) (34)
Variation tolerant on-chip degradation sensors for dynamic reliability management systems (2012) (28)
A full adder implementation using SET based linear threshold gates (2002) (28)
Bitstream compression techniques for Virtex 4 FPGAs (2008) (27)
An Analysis of Internal Parameter Variations Effects on Nanoscaled Gates (2008) (27)
Future Directions of (Programmable and Reconfigurable) Embedded Processors (2004) (26)
A composable, energy-managed, real-time MPSOC platform (2010) (26)
A Hierarchical sparse matrix storage format for vector processors (2003) (25)
An 8x8 IDCT Implementation on an FPGA-Augmented TriMedia (2001) (25)
An O(n) Residue Number System to Mixed Radix Conversion technique (2009) (24)
Microcode Processing: Positioning and Directions (2003) (24)
Alternatives in FPGA-based SAD implementations (2002) (23)
An improved RNS reverse converter for the {22n+1−1, 2n, 2n−1} moduli set (2010) (23)
Embedded Processors: Characteristics and Trends (2004) (22)
A low-power threshold logic family (2002) (22)
On the design complexity of the issue logic of superscalar machines (1998) (21)
Color space conversion for MPEG decoding on FPGA-augmented TriMedia processor (2003) (21)
Residue Number System operands to decimal conversion for 3-moduli sets (2008) (21)
Flexible, Cost-Efficient, High-Throughput Architecture for Layered LDPC Decoders with Fully-Parallel Processing Units (2016) (21)
A Novel Flit Serialization Strategy to Utilize Partially Faulty Links in Networks-on-Chip (2012) (21)
Graphene Nanoribbon Based Complementary Logic Gates and Circuits (2019) (21)
Computing Division Using Single-Electron Tunneling Technology (2007) (20)
Block Based Compression Storage Expected Performance (2002) (19)
A new latch-based threshold logic family (2001) (19)
MPEG macroblock parsing and pel reconstruction on an FPGA-augmented TriMedia processor (2001) (19)
Digital to analog conversion performed in single electron technology (2001) (19)
CONAN - a design exploration framework for reliable nano-electronics architectures (2005) (18)
Analog-to-digital converter based on single-electron tunneling transistors (2004) (17)
Coarse reconfigurable multimedia unit extension (2001) (17)
Single-electron tunneling transistor implementation of periodic symmetric functions (2004) (16)
MPEG-compliant entropy decoding on FPGA-augmented TriMedia/CPU64 (2002) (16)
Binary addition based on single electron tunneling devices (2004) (16)
Compositional memory systems for multimedia communicating tasks (2005) (15)
Signed Digit Addition and Related Operations with Threshold Logic (2000) (15)
Fan-out enabled spin wave majority gate (2020) (15)
Fault tolerant structures for nanoscale gates (2007) (15)
Ultra low power NEMFET based logic (2013) (15)
An Efficient FPGA Design of Residue-to-Binary Converter for the Moduli Set $\{2n+1,2n,2n-1\}$ (2011) (15)
High-Level Energy Estimation for ARM-Based SOCs (2004) (15)
Brownian Circuits: Designs (2016) (15)
Achieving fanout capabilities in single electron encoded logic networks (2001) (14)
General-purpose processor Huffman encoding extension (2000) (14)
Evaluation Methodology for Single Electron Encoded Threshold Logic Gates (2003) (14)
Low cost and energy, thermal noise driven, probability modulated random number generator (2015) (13)
A nonlinear degradation path dependent end-of-life estimation framework from noisy observations (2013) (13)
State of the art in CMOS threshold logic VLSI gate implementations and systems (2003) (13)
Capacitive threshold logic: a designer perspective (1999) (12)
Decoupled inter- and intra-application scheduling for composable and robust embedded MPSoC platforms (2012) (12)
High-speed hybrid threshold-Boolean logic counters and compressors (2002) (12)
On computing addition related arithmetic operations via controlled transport of charge (2003) (12)
GRAAL - a development framework for embedded graphics accelerators (2004) (12)
Addition related arithmetic operations with threshold logic (1998) (12)
Emerging non-CMOS nanoelectronic devices - What are they? (2009) (12)
A residue to binary converter for the {2n + 2, 2n + 1, 2n} moduli set (2008) (12)
Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits (2014) (12)
Throughput optimization via cache partitioning for embedded multiprocessors (2006) (12)
IDCT Implementation on an FPGA-Augmented TriMedia (2001) (12)
Memory-Efficient Dataflow Inference for Deep CNNs on FPGA (2020) (12)
Efficient Computation Reduction in Bayesian Neural Networks Through Feature Decomposition and Memorization (2020) (11)
GRAAL: A Framework for Low-Power 3D Graphics Accelerators (2008) (11)
Energy-Efficient Computation of L1 and L2 Norms on a FPGA SIMD Accelerator, with Applications to Visual Search (2014) (11)
Design and experimental results of a CMOS flip-flop featuring embedded threshold logic (2003) (11)
A versatile threshold logic gate (1998) (11)
An Efficient RNS to Binary Converter Using the Moduli Set (2008) (10)
Block save addition with threshold logic (1995) (10)
Residue-to-binary converters for the moduli set {22n+1-1,22n,2n-1} (2009) (10)
Digital to analogue converter based on single-electron tunnelling transistor (2004) (10)
Analysis of the impact of spatial and temporal variations on the stability of SRAM arrays and the mitigation technique using independent-gate devices (2014) (10)
Building Blocks for Fluctuation Based Calculation in Single Electron Tunneling Technology (2008) (10)
Generalized matrix method for efficient residue to decimal conversion (2008) (9)
A Self-Matching Complementary-Reference Sensing Scheme for High-Speed and Reliable Toggle Spin Torque MRAM (2020) (9)
Spin Wave Normalization Toward All Magnonic Circuits (2020) (9)
On Carving Basic Boolean Functions on Graphene Nanoribbons Conduction Maps (2018) (9)
Block Save Addition with Telescopic SumsS (1995) (9)
Multimedia enhanced general-purpose processors (2000) (9)
Ultra-low leakage SRAM design with sub-32 nm tunnel FETs for low standby power applications (2016) (9)
An effective New CRT based reverse converter for a novel moduli set {22n+1 − 1, 22n+1, 22n − 1} (2013) (9)
Towards “zero-energy” using NEMFET-based power management for 3D hybrid stacked ICs (2011) (9)
Logical effort based design exploration of 64-bit adders using a mixed dynamic-CMOS/threshold-logic approach (2004) (9)
Sparse Matrix Vector Multiplication Evaluation Using the BBCS Scheme (2001) (8)
Composable local memory organisation for streaming applications on embedded MPSoCs (2011) (8)
Is 3D integration the way to future dependable computing platforms? (2012) (8)
The future of computing : essays in memory of Stamatis Vassiliadis (2007) (8)
Adaptive Fault-Tolerant Architecture for Unreliable Technologies With Heterogeneous Variability (2012) (8)
Compositional, efficient caches for a chip multi-processor (2006) (8)
δ-Bit serial binary addition with linear threshold networks (1996) (8)
Inverse Gaussian distribution based timing analysis of Sub-threshold CMOS circuits (2015) (8)
Pel reconstruction on FPGA-augmented TriMedia (2004) (8)
FSM non-minimal state encoding for low power (2002) (8)
Static cache partitioning robustness analysis for embedded on-chip multi-processors (2006) (7)
VASILE: A reconfigurable vector architecture for instruction level frequency scaling (2013) (7)
Can SG-FET Replace FET in Sleep Mode Circuits? (2009) (7)
Binary multiplication based on single electron tunneling (2004) (7)
Enabling vertical wormhole switching in 3D NoC-Bus hybrid systems (2015) (7)
A novel virtual age reliability model for Time-to-Failure prediction (2010) (7)
A unified addition structure for moduli set {2n−1, 2n, 2n+1} based on a novel RNS representation (2010) (7)
Low-Leakage 3D Stacked Hybrid NEMFET-CMOS Dual Port Memory (2018) (7)
7|2 counters and multiplication with threshold logic (1996) (7)
4-output Programmable Spin Wave Logic Gate (2020) (7)
Single electron encoded logic memory elements (2003) (7)
Periodic Symmetric Functions with Feed-Forward Neural Networks (1995) (7)
SAD implementation in FPGA hardware (2001) (7)
Efficient Method for Designing Modulo {2n ± k} Multipliers (2014) (7)
A direct measurement scheme of amalgamated aging effects with novel on-chip sensor (2013) (7)
SPICE implementation of a compact single electron tunneling transistor model (2004) (7)
On Basic Boolean Function Graphene Nanoribbon Conductance Mapping (2019) (7)
Implementable building blocks for fluctuation based calculation in single electron tunneling technology (2009) (6)
n-bit Data Parallel Spin Wave Logic Gate (2020) (6)
CMOS Implementation of Generalized Threshold Functions (2009) (6)
Atomistic-Level Hysteresis-Aware Graphene Structures Electron Transport Model (2019) (6)
Residue-to-decimal converters for moduli sets with common factors (2009) (6)
Stigmergic search with Single Electron Tunneling technology based Memory Enhanced Hubs (2012) (6)
Low Weight and Fan-In Neural Networks for Basic Arithmetic Operations (2007) (6)
2-Output Spin Wave Programmable Logic Gate (2020) (6)
Memristive Oscillatory Circuits for Resolution of NP-Complete Logic Puzzles: Sudoku Case (2020) (6)
A Hardware / Software Co-Simulation Environment for Graphics Accelerator Development in ARM-Based SOCs (2002) (6)
Building blocks for delay-insensitive circuits using single electron tunneling devices (2007) (6)
Memoryless RNS-to-binary converters for the {2n+1 - 1, 2n, 2n - 1} moduli set (2010) (6)
A low cost method to tolerate soft errors in the NoC router control plane (2013) (6)
Is TSV-based 3D integration suitable for inter-die memory repair? (2013) (6)
Embedded computer architecture laboratory: a hands-on experience programming embedded systems with resource and energy constraints (2012) (6)
Link Bandwidth Aware Backtracking Based Dynamic Task Mapping in NoC based MPSoCs (2014) (5)
Complementary Arranged Graphene Nanoribbon-based Boolean Gates (2018) (5)
Buffer design trade-offs for single electron logic gates (2005) (5)
Functional unit sharing between stacked processors in 3D integrated systems (2011) (5)
Towards Maximum Utilization of Remained Bandwidth in Defected NoC Links (2017) (5)
Error Correction Code protected Data Processing Units (2016) (5)
Analysis of analog to digital converter based on single-electron tunnelling transistors (2004) (5)
An Investigation on FPGA based SAD Hardware Implementations (2002) (5)
Is the road towards “Zero-Energy” paved with NEMFET-based power management? (2012) (5)
Vector ISA Extension for Sparse Matrix-Vector Multiplication (1999) (5)
An Input Weights Aware Synthesis Tool for Threshold Logic Networks (2005) (5)
An Effective Routing Algorithm to Avoid Unnecessary Link Abandon in 2D Mesh NoCs (2013) (5)
Design methodology for single electron based building blocks (2005) (5)
Low cost and latency embedded 3D graphics reciprocation (2004) (5)
D-SAB: A Sparse Matrix Benchmark Suite (2003) (5)
BBCS Based Sparse Matrix-Vector Multiplication: Initial Evaluation (2000) (5)
A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder (2009) (4)
An Energy-Aware Architectural Exploration Tool for ARM-Based SOCs (2001) (4)
Microcoded Reconfigurable Embedded Processors: Current Developments (2002) (4)
Area efficient, high speed parallel counter circuits using charge recycling threshold logic (2003) (4)
On Teaching Embedded Systems Design to Electrical Engineering Students (2002) (4)
Hybrid adaptive clock management for FPGA processor acceleration (2015) (4)
On effective computation with nanodevices: a single electron tunnelling technology case study (2004) (4)
Spin Wave Based Approximate Computing (2021) (4)
2 Counters and Multiplication with Linear Threshold Logic (1996) (4)
Compact current and current noise models for single-electron tunneling transistors (2004) (4)
Fast Computation of Compound Expressions in Two's Complement Notation (2007) (4)
ROST-C: Reliability driven optimisation and synthesis techniques for combinational circuits (2015) (4)
Energy effective 3D stacked hybrid NEMFET-CMOS caches (2014) (4)
Compositional, Dynamic Cache Management for Embedded Chip Multiprocessors (2008) (4)
Context aware slope based transistor-level aging model (2012) (4)
3D stacked wide-operand adders: A case study (2013) (4)
A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study (2002) (4)
A Mixed-Size Monolithic 3D Placer with 2D Layout Inheritance (2017) (4)
Compositional memory systems for data intensive applications (2004) (4)
A reverse converter for the new 4-moduli set {2n + 3, 2n + 2, 2n + 1, 2n} (2009) (4)
Basic Building Blocks for Effective Single Electron Tunneling Technology Based Computation (2006) (4)
Leakage-enhanced 3D-Stacked NEMFET-based power management architecture for autonomous sensors systems (2011) (4)
Timing error analysis of flooded LDPC decoders (2015) (4)
Zero-performance-overhead online fault detection and diagnosis in 3D stacked integrated circuits (2012) (3)
A Pragmatic Gaze on Stochastic Resonance Based Variability Tolerant Memristance Enhancement (2019) (3)
A supply voltage-dependent variation aware reliability evaluation model (2016) (3)
Block Save Addition with Threshold Gates (1995) (3)
Casta DIVA - a design for variability platform (2008) (3)
Towards an Effective Utilization of Partially Defected Interconnections in 2D Mesh NoCs (2014) (3)
GARBAGE COLLECTION FOR THE DELFT JAVA PROCESSOR (2003) (3)
High radix addition via conditional charge transport in single electron tunneling technology (2005) (3)
A Method to Analyze the Fault Tolerance of Molecular Quantum-Dot Cellular Automata Systems (2006) (3)
Evolutionary bin packing for memory-efficient dataflow inference acceleration on FPGA (2020) (3)
Design Tradeoffs for an Embedded OpenGL-Compliant Hardware Rasterizer (2003) (3)
Robust sub-powered asynchronous logic (2014) (3)
NBTI stress delay sensitivity analysis of reliability enhanced Schmitt trigger based circuits (2019) (3)
Roadmap for Unconventional Computing with Nanotechnology (2023) (3)
Direct and Transposed Sparse Matrix-Vector Multiplication (2002) (3)
Multifrequency Data Parallel Spin Wave Logic Gates (2020) (3)
A shared polyhedral cache for 3D wide-I/O multi-core computing platforms (2015) (3)
Efficient Hardware for Tile-Based Rasterization (2004) (3)
Counter based superscalar instruction issuing (2000) (3)
Single Electron Tunneling Delay Insensitive and fluctuation based computation paradigms and circuits (2008) (3)
Asynchronous Charge Sharing Power Consistent Montgomery Multiplier (2015) (3)
A master equation model of multi-island single-electron transistors based on stability diagram (2010) (3)
Hashed Addressed Caches for Embedded Pointer Based Codes (Research Note) (2000) (3)
Electron counting based high-radix multiplication in single electron tunneling technology (2006) (3)
IEEE-Compliant IDCT on FPGA-Augmented TriMedia (2005) (3)
Ultra-Compact, Entirely Graphene-Based Nonlinear Leaky Integrate-and-Fire Spiking Neuron (2020) (3)
Controlled Degradation Stochastic Resonance in Adaptive Averaging Cell-Based Architectures (2013) (3)
Non-Equilibrium Green Function-based Verilog-A Graphene Nanoribbon Model (2018) (3)
Degradation Stochastic Resonance (DSR) in AD-AVG architectures (2012) (3)
High-speed Hybrid Threshold-Boolean Logic (2002) (3)
An Efficient FPGA Design of Reverse Converter for the Moduli Set { 2 n + 2 , 2 n + 1 , 2 n } (2010) (3)
Emerging Phenomena-dependent Non-CMOS Nanoelectronic Devices-What Are They ? (2008) (3)
A Re verse Converter for the New 4-Moduli Set (2009) (3)
Hierarchical interfaces for hardware software systems (2000) (2)
TFET NDR skewed inverter based sensing method (2016) (2)
Efficient hardware for antialiasing coverage mask generation (2004) (2)
An efficient residue-to-binary converter for the new moduli set {2n/2 ± 1, 22n+1,2n + 1} (2014) (2)
HIERARCHICAL INTELLIGENT SIMULATION (2003) (2)
Would Magnonic Circuits Outperform CMOS Counterparts? (2022) (2)
A Reverse Converter for the New 4-Moduli Set { 2 n + 3 , 2 n + 2 , 2 n + 1 , 2 n } (2009) (2)
Suspended Gate Field Effect Transistor based power management - a 32-bit adder case study (2009) (2)
Achieving Wave Pipelining in Spin Wave Technology (2021) (2)
Towards energy effective LDPC decoding by exploiting channel noise variability (2014) (2)
Computing Division in the Electron Counting Paradigm using Single Electron Tunneling Technology (2006) (2)
2-1 Addition and Related Arithmetic perations with Threshold Logic (1996) (2)
A Spin Wave-Based Approximate 4:2 Compressor: Seeking the most energy-efficient digital computing paradigm (2022) (2)
Entropy Decoding on TriMedia / CPU 64 (2002) (2)
A Markovian, variation-aware circuit-level aging model (2012) (2)
Logic-enhanced memory for 3D graphics tile-based rasterizers (2004) (2)
Critical transistors nexus based circuit-level aging assessment and prediction (2014) (2)
Low cost multi-error correction for 3D polyhedral memories (2017) (2)
Adaptive Clock Scheduling for pipelined structures (2009) (2)
A Family of Single Electron Static Buffered Boolean Logic (2002) (2)
Spin Wave Based Full Adder (2021) (2)
Fan-out of 2 Triangle Shape Spin Wave Logic Gates (2020) (2)
3D graphics tile-based systolic scan-conversion (2004) (2)
Towards heterogenous 3D-stacked reliable computing with von Neumann multiplexing (2013) (2)
Graphene Nanoribbon-based Synapses with Versatile Plasticity (2019) (2)
Sub-5.5 FO4 delay CMOS 64-bit domino/threshold logic adder design (2004) (2)
MRC Technique for RNS to Decimal Conversion Using the Moduli Set { 2 n + 2 , 2 n + 1 , 2 n } (2008) (2)
Spin Wave Based 4-2 Compressor (2021) (2)
An approach for digital Circuit Error/Reliability Propagation Analysis based on Conditional Probability (2016) (2)
A CMOS flip-flop featuring embedded Threshold logic functions (2002) (2)
Lifetime reliability assessment with aging information from low-level sensors (2013) (2)
Compact Graphene-Based Spiking Neural Network With Unsupervised Learning Capabilities (2020) (1)
Hierarchical Intellignet Mixed Simulation (2002) (1)
Compact delay modeling of latch-based threshold logic gates (2002) (1)
Graphene-Based Artificial Synapses with Tunable Plasticity (2021) (1)
A 3D stacked high performance scalable architecture for 3D Fourier Transform (2012) (1)
Probability density function based reliability evaluation of large-scale ICs (2014) (1)
Periodic Symmetric Functions and Addition Related Arithmetic Operations in Single Electron Tunneling Technology (2005) (1)
Serial Binary Addition with Polynominally Bounded Weights (1996) (1)
Energy-Managed , Real-Time MPSOC Platform (2010) (1)
Single Electron Encoded Logic Circuits (2001) (1)
Adaptive fault-tolerant architecture for unreliable device technologies (2011) (1)
Heuristic Algorithms for Primitive Traversal Acceleration in Tile-Based Rasterization (2004) (1)
Array Based Structure Loop Transformations For Cache Miss Reduction (2000) (1)
From Computability to Simulability (2006) (1)
Design Considerations of a Multiple Inner Product and Accumulate Vector Functional Unit (2002) (1)
MULTI-HIERARCHICAL LEARNING-BASED COSIMULATION (2003) (1)
High-Performance, Cost-Effective 3D Stacked Wide-Operand Adders (2017) (1)
Color Space Conversion on FPGA-augmented TriMedia-32 Processor (2002) (1)
Threshold logic parallel counters for 32-bit multipliers (2002) (1)
2-1 redundant addition with threshold logic (1996) (1)
Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic (2004) (1)
On Effective Graphene Based Computing (2018) (1)
An Analysis of Basic Structures for Effective Computation in Single Electron Tunneling Technology (2007) (1)
Dynamic Bitstream Length Scaling Energy Effective Stochastic LDPC Decoding (2015) (1)
Transmission Channel Noise Aware Energy Effective LDPC Decoding (2014) (1)
Single Electron Tunneling based computation (2010) (1)
Signed Digit Counters with Neural Networks (2007) (1)
Consciousness for modeling intelligence - simulating the evolution by closure to the inverse (2006) (1)
. FURTHERMORE, THEY PRESENT A MICROCODED MACHINE AUGMENTED WITH FIELD -PROGRAMMABLE GATE ARRAYS (FPGAS) AND PROVIDE EXPERIMENTAL EVIDENCE THAT IT CAN SUBSTANTIALLY INCREASE THE PERFORMANCE OF SOME MEDIA BENCHMARKS . MICROCODE PROCESSING: POSITIONING AND DIRECTIONS (2003) (1)
Counters Implemented in Single Electron Technology (2002) (1)
A CMOS Semi-Custom Chip for Mixed Signal Designs (2004) (0)
1 Integrated magnonic half-adder (2019) (0)
Multi-level probabilistic timing error reliability analysis using a circuit dependent fault map generation (2015) (0)
Asynchronous Charge Sharing Power Consistent (2015) (0)
Concurrent engineering for intelligent simulation (2003) (0)
Methodology for Automated Design of Quantum-Dot Cellular Automata Circuits (2022) (0)
2-input 4-output Programmable Spin Wave Logic Gate. (2020) (0)
Single Electron Encoded SET Memory Elements (2000) (0)
2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), Copenhagen, Denmark, 9-11 May, 2012 (2012) (0)
Inverse Quantization on FPGA-augmented TriMedia (2003) (0)
Variable Length Decoder Implemented on a TriMedia/CPU64 Reconfigurable Functional Unit (2001) (0)
HIERARCHICAL INTELLIGENT MIXED SIMULATION (2003) (0)
An 8-Point IDCT computing resource implemented on a TriMedia/CPU64 reconfigurable functional unit (2001) (0)
A Reconfigurable Graphene-Based Spiking Neural Network Architecture (2021) (0)
Transposition Mechanism for Sparse Matrices on Vector Processors (2001) (0)
Topic 15+20: Multimedia and Embedded Systems (2001) (0)
Block Based Compression Storage (2000) (0)
LDPC-Based Adaptive Multi-Error Correction for 3D Memories (2017) (0)
Haar-based interconnect coding for energy effective medium/long range data transport (2017) (0)
Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale Architectures (2014) (0)
Logical Effort Delay Modeling of Sense Amplifier Based Charge Recycling Threshold Logic Gates (2003) (0)
A Study of Graphene Nanoribbon-based Gate Performance Robustness under Temperature Variations (2020) (0)
Low Energy, Non-Cortical, Graphene Nanoribbon-Based STDP Plastic Synapses (2022) (0)
A Taxonomy of Field-Programmable Custom Computing Machines (2007) (0)
Hierarchical approach for hardware/software systems (2000) (0)
Analysis of delay mismatching of digital circuits caused by common environmental fluctuations (2011) (0)
Hierarchical Testability Assisted Intelligent Simulation (2004) (0)
Session details: Reliability, Resiliency, Robustness II (2015) (0)
Spin Wave Based Approximate 4:2 Compressor (2021) (0)
IEEE Nanotechnology Council Executive Committee (2006) (0)
On Effective Computation with Single Electron Tunnelling Devices (2007) (0)
On Effective Computation with Single Electron Tunnelling Devices (2007) (0)
Building Blocks for Electron Counting Arithmetic (2003) (0)
Implementation of a Dual Analog Decoder (2004) (0)
DAMP-Delft Altera-based Multimedia Platform (2002) (0)
Non-Binary Spin Wave Based Circuit Design (2022) (0)
(Invited) Magnetoelectrics at Nanometer and Gigahertz Scales for Advanced Spintronic Computing Applications (2021) (0)
Fast and accurate workload-level neural network based IC energy consumption estimation (2017) (0)
LOOKING FOR INTELLIGENT RECONFIGURABLE SIMULATION (2004) (0)
Associate Editor-in-Chief (also Editor) (2015) (0)
Manufacturability Issues of Redundant Nanogates (2007) (0)
Nanotechnology-Enabled Unconventional Computing [Guest Editorial] (2022) (0)
Serial binary multiplication with feed-forward neural networks (1999) (0)
High-Radix Addition and Multiplication in the Electron Counting Paradigm Using Single Electron Tunneling Technology (2006) (0)
A Turnstile Based Single Electron Memory Element (2007) (0)
On Serial Multiplication with Neural Networks (2007) (0)
An Energy-Efficient Bayesian Neural Network Implementation Using Stochastic Computing Method. (2023) (0)

This paper list is powered by the following services:

Other Resources About Sorin Coțofană

en.wikipedia.org

What Schools Are Affiliated With Sorin Coțofană?

Sorin Coțofană is affiliated with the following schools:

Sorin Coțofană's Academic­Influence.com Rankings

Sorin Coțofană's Degrees

Why Is Sorin Coțofană Influential?

Sorin Coțofană's Published Works

Published Works

Other Resources About Sorin Coțofană

What Schools Are Affiliated With Sorin Coțofană?

Sorin Coțofană's AcademicInfluence.com Rankings