Steve Furber

Q: What Schools Are Affiliated With Steve Furber

Steve Furber is affiliated with the following schools: University of Manchester, University of Cambridge

Steve Furber's AcademicInfluence.com Rankings

Steve Furber

Computer Science

#284

World Rank

#296

Historical Rank

Database

#3457

World Rank

#3602

Historical Rank

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Computer Science

Why Is Steve Furber Influential?

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According to Wikipedia, Stephen Byram Furber is a British computer scientist, mathematician and hardware engineer, and Emeritus ICL Professor of Computer Engineering in the Department of Computer Science at the University of Manchester, UK. After completing his education at the University of Cambridge , he spent the 1980s at Acorn Computers, where he was a principal designer of the BBC Micro and the ARM 32-bit RISC microprocessor. , over 250 billion arm chips have been manufactured, powering much of the world's mobile computing and embedded systems, everything from sensors to smartphones to servers.

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Steve Furber's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

The SpiNNaker Project (2014) (893)
Principles of Asynchronous Circuit Design: A Systems Perspective (2010) (668)
Principles of Asynchronous Circuit Design (2001) (574)
Overview of the SpiNNaker System Architecture (2013) (558)
SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation (2013) (330)
ARM System-on-Chip Architecture (2000) (291)
SpiNNaker: Mapping neural networks onto a massively-parallel chip multiprocessor (2008) (284)
ARM System Architecture (1996) (272)
Chain: A Delay-Insensitive Chip Area Interconnect (2002) (260)
Four-phase micropipeline latch control circuits (1996) (255)
Large-scale neuromorphic computing systems (2016) (192)
AMULET2e: an asynchronous embedded controller (1997) (182)
Neural systems engineering (2007) (159)
A GALS Infrastructure for a Massively Parallel Multiprocessor (2007) (146)
To build a brain (2012) (145)
Introducing SLAMBench, a performance and accuracy benchmarking methodology for SLAM (2014) (138)
Delay insensitive system-on-chip interconnect using 1-of-4 data encoding (2001) (124)
Delay-insensitive, point-to-point interconnect using m-of-n codes (2003) (115)
Efficient modelling of spiking neural networks on a scalable chip multiprocessor (2008) (103)
Modeling Spiking Neural Networks on SpiNNaker (2010) (103)
Performance Comparison of the Digital Neuromorphic Hardware SpiNNaker and the Neural Network Simulation Software NEST for a Full-Scale Cortical Microcircuit Model (2018) (101)
A micropipelined ARM (1993) (100)
High-performance computing for systems of spiking neurons (2006) (95)
An asynchronous on-chip network router with quality-of-service (QoS) support (2004) (94)
Robustness of spiking Deep Belief Networks to noise and reduced bit precision of neuro-inspired hardware platforms (2015) (94)
2022 roadmap on neuromorphic computing and engineering (2021) (82)
Power analysis of large-scale, real-time neural networks on SpiNNaker (2013) (81)
AMULET3: a 100 MIPS asynchronous embedded processor (2000) (79)
AMULET3i-an asynchronous system-on-chip (2000) (76)
Scalable energy-efficient, low-latency implementations of trained spiking Deep Belief Networks on SpiNNaker (2015) (75)
Dynamic logic in four-phase micropipelines (1996) (75)
AMULET1: A Asynchronous ARM Microprocessor (1997) (73)
AMULET1: a micropipelined ARM (1994) (72)
Computing without Clocks: Micropipelining the ARM Processor (1995) (69)
Biologically-Inspired Massively-Parallel Architectures - Computing Beyond a Million Processors (2009) (69)
A hierachical configuration system for a massively parallel neural hardware platform (2012) (65)
Implementing spike-timing-dependent plasticity on SpiNNaker neuromorphic hardware (2010) (65)
Understanding the interconnection network of SpiNNaker (2009) (65)
Power-efficient simulation of detailed cortical microcircuits on SpiNNaker (2012) (64)
An investigation into the security of self-timed circuits (2003) (61)
SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation (2012) (61)
SpiNNaker 2: A 10 Million Core Processor System for Brain Simulation and Machine Learning (2019) (60)
VLSI Risc Architecture and Organization (1989) (58)
Future trends in SoC interconnect (2005) (54)
On-chip and inter-chip networks for modeling large-scale neural systems (2006) (54)
SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip (2011) (52)
sPyNNaker: A Software Package for Running PyNN Simulations on SpiNNaker (2018) (52)
An efficient SpiNNaker implementation of the Neural Engineering Framework (2015) (52)
SLAMBench2: Multi-Objective Head-to-Head Benchmarking for Visual SLAM (2018) (50)
Memory-Efficient Deep Learning on a SpiNNaker 2 Prototype (2018) (48)
AMULET3 revealed (1999) (47)
Scalable event-driven native parallel processing: the SpiNNaker neuromimetic system (2010) (46)
Asynchronous macrocell interconnect using MARBLE (1998) (45)
Comparison of Artificial and Spiking Neural Networks on Digital Hardware (2021) (45)
Using Stochastic Spiking Neural Networks on SpiNNaker to Solve Constraint Satisfaction Problems (2017) (44)
Sparse distributed memory using N-of-M codes (2004) (44)
A framework for plasticity implementation on the SpiNNaker neural architecture (2015) (44)
The design and evaluation of an asynchronous microprocessor (1994) (43)
AMULET3: a high-performance self-timed ARM microprocessor (1998) (43)
The Leaky Integrate-and-Fire neuron: A platform for synaptic model exploration on the SpiNNaker chip (2010) (41)
Scan testing of micropipelines (1995) (40)
Stochastic rounding and reduced-precision fixed-point arithmetic for solving neural ordinary differential equations (2019) (40)
This is the pre-peer-reviewed version of the following article: (2012) (39)
Virtual synaptic interconnect using an asynchronous network-on-chip (2008) (39)
Built-in self-testing of micropipelines (1997) (39)
Accuracy and Efficiency in Fixed-Point Neural ODE Solvers (2015) (37)
Event-based neural computing on an autonomous mobile platform (2014) (37)
Living with Failure: Lessons from Nature? (2006) (36)
Register locking in an asynchronous microprocessor (1992) (36)
Fault Tolerant Delay Insensitive Inter-chip Communication (2009) (36)
Deep Spiking Neural Network model for time-variant signals classification: a real-time speech recognition approach (2018) (35)
Real-time cortical simulation on neuromorphic hardware (2019) (35)
ConvNets experiments on SpiNNaker (2015) (34)
A Novel Programmable Parallel CRC Circuit (2011) (33)
An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator (2008) (32)
Navigating the Landscape for Real-Time Localization and Mapping for Robotics and Virtual and Augmented Reality (2018) (32)
Real time on-chip implementation of dynamical systems with spiking neurons (2012) (31)
A Multicast Routing Scheme for a Universal Spiking Neural Network Architecture (2010) (31)
Spiking neural networks for computer vision (2018) (31)
“Serial” effects in parallel models of reading (2012) (31)
A forecast-based STDP rule suitable for neuromorphic implementation (2012) (31)
Is the Weis-Fogh principle exploitable in turbomachinery? (1979) (31)
Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware (2011) (31)
Real-Time Interface Board for Closed-Loop Robotic Tasks on the SpiNNaker Neural Computing System (2013) (29)
SLAMBench 3.0: Systematic Automated Reproducible Evaluation of SLAM Systems for Robot Vision Challenges and Scene Understanding (2019) (29)
A General-Purpose Model Translation System for a Universal Neural Chip (2010) (29)
Modelling and Simulation of Asynchronous Systems Using the LARD Hardware Description Language (1998) (29)
The design of a low power asynchronous multiplier (2004) (29)
Benchmarking Spike-Based Visual Recognition: A Dataset and Evaluation (2016) (29)
SpiNNTools: The Execution Engine for the SpiNNaker Platform (2018) (27)
A fixed point exponential function accelerator for a neuromorphic many-core system (2017) (27)
An asynchronous ternary logic signaling system (2003) (27)
Breaking the millisecond barrier on SpiNNaker: implementing asynchronous event-based plastic models with microsecond resolution (2015) (27)
Real-time event-driven spiking neural network object recognition on the SpiNNaker platform (2015) (26)
On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems (2017) (25)
Neuromodulated Synaptic Plasticity on the SpiNNaker Neuromorphic System (2018) (25)
Correctness and performance of the SpiNNaker architecture (2013) (25)
Sparse Distributed Memory Using Rank-Order Neural Codes (2007) (25)
Dynamic voltage and frequency scaling for neuromorphic many-core systems (2017) (24)
SpiNNaker—Programming Model (2015) (24)
Event-Driven Simulation of Arbitrary Spiking Neural Networks on SpiNNaker (2011) (24)
Algorithm and software for simulation of spiking neural networks on the multi-chip SpiNNaker system (2010) (24)
Noisy Softplus: A Biology Inspired Activation Function (2016) (24)
pyDVS: An extensible, real-time Dynamic Vision Sensor emulator using off-the-shelf hardware (2016) (24)
Efficient Reward-Based Structural Plasticity on a SpiNNaker 2 Prototype (2019) (24)
A Real-Time, Event-Driven Neuromorphic System for Goal-Directed Attentional Selection (2012) (24)
Population-based routing in the SpiNNaker neuromorphic architecture (2012) (23)
SpiNNaker: Enhanced multicast routing (2015) (23)
An asynchronous low latency arbiter for Quality of Service (QoS) applications (2003) (23)
Classification and regression of spatio-temporal signals using NeuCube and its realization on SpiNNaker neuromorphic hardware (2019) (23)
Scan testing of asynchronous sequential circuits (1995) (22)
Large-Scale Simulations of Plastic Neural Networks on Neuromorphic Hardware (2016) (22)
Real-time million-synapse simulation of rat barrel cortex (2014) (22)
High performance computing on SpiNNaker neuromorphic platform: A case study for energy efficient image processing (2016) (21)
SpiNNaker: A Spiking Neural Network Architecture (2020) (21)
Interfacing Real-Time Spiking I/O with the SpiNNaker Neuromimetic Architecture (2010) (21)
The design and test of a smartcard chip using a CHAIN self-timed network-on-chip (2004) (21)
Beyond Moore's law (2014) (20)
Synapse-Centric Mapping of Cortical Models to the SpiNNaker Neuromorphic Architecture (2016) (20)
Efficient SpiNNaker simulation of a heteroassociative memory using the Neural Engineering Framework (2016) (19)
A location-independent direct link neuromorphic interface (2013) (19)
Meeting the design challenges of nanoCMOS electronics (2007) (19)
Biologically Inspired Means for Rank-Order Encoding Images: A Quantitative Analysis (2010) (19)
Modelling normal and impaired letter recognition: Implications for understanding pure alexic reading (2012) (19)
The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing (2021) (18)
Implementing Learning on the SpiNNaker Universal Neural Chip Multiprocessor (2009) (17)
Creating, documenting and sharing network models (2012) (17)
Design and analysis of a self-timed duplex communication system (2004) (17)
A Power-Efficient Duplex Communication System (2000) (17)
A Programmable Adaptive Router for a GALS Parallel System (2009) (16)
Scalable communications for a million-core neural processing architecture (2012) (16)
Breaking step: the return of asynchronous logic (1993) (16)
Nanoscale Room-Temperature Multilayer Skyrmionic Synapse for Deep Spiking Neural Networks (2020) (16)
Structural Plasticity on the SpiNNaker Many-Core Neuromorphic System (2018) (16)
Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis (2011) (15)
The Deferred Event Model for Hardware-Oriented Spiking Neural Networks (2009) (15)
Distributed configuration of massively-parallel simulation on SpiNNaker neuromorphic hardware (2011) (15)
Noisy Softplus: an activation function that enables SNNs to be trained as ANNs (2017) (15)
Power Management in the Amulet Microprocessors (2001) (15)
Maximising information recovery from rank-order codes (2007) (15)
A low-power self-timed Viterbi decoder (2001) (15)
The Future of Computer Technology and its Implications for the Computer Industry (2008) (14)
SpiNNaker: impact of traffic locality, causality and burstiness on the performance of the interconnection network (2010) (14)
Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric (2009) (14)
Comparing Loihi with a SpiNNaker 2 prototype on low-latency keyword spotting and adaptive robotic control (2021) (14)
Building a Spiking Neural Network Model of the Basal Ganglia on SpiNNaker (2018) (13)
A universal abstract-time platform for real-time neural networks (2009) (13)
SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture (2013) (13)
Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System (2012) (13)
Designing robust asynchronous circuit components (2003) (13)
The Acorn RISC Machine ߞ an architectural view (1987) (13)
Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip (2018) (13)
The return of asynchronous logic (1996) (12)
An associative memory for the on-line recognition and prediction of temporal sequences (2005) (12)
Linking Brain Structure, Activity, and Cognitive Function through Computation (2022) (12)
Live Demo: Spiking ratSLAM: Rat hippocampus cells in spiking neural hardware (2012) (12)
The design of an asynchronous VHDL synthesizer (1998) (12)
Identifying Energy Holes in Randomly Deployed Hierarchical Wireless Sensor Networks (2017) (11)
Visual attention and object naming in humanoid robots using a bio-inspired spiking neural network (2018) (11)
MARBLE: an asynchronous on-chip macrocell bus (2000) (11)
Microprocessors: the engines of the digital age (2017) (10)
Towards Real-World Neurorobotics: Integrated Neuromorphic Visual Attention (2014) (10)
Brain-inspired computing (2016) (10)
Markov Chain Monte Carlo inference on graphical models using event-based processing on the SpiNNaker neuromorphic architecture (2015) (10)
Engineering a thalamo-cortico-thalamic circuit on SpiNNaker: a preliminary study toward modeling sleep and wakefulness (2014) (10)
Analytical Assessment of the Suitability of Multicast Communications for the SpiNNaker Neuromimetic System (2012) (9)
Efficient parallel implementation of multilayer backpropagation networks on SpiNNaker (2010) (9)
A Spiking Neural Sparse Distributed Memory Implementation for Learning and Predicting Temporal Sequences (2005) (9)
Full-scale simulation of a cortical microcircuit on SpiNNaker (2016) (9)
Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multisymbol Chip Links: Application to SpiNNaker 2-of-7 Links (2016) (9)
SpiNNaker: The Design Automation Problem (2009) (9)
The coming decade of digital brain research A vision for neuroscience at the intersection of technology and computing (2022) (9)
Information recovery from rank-order encoded images (2006) (9)
Optimal connectivity in hardware-targetted MLP networks (2009) (9)
A GPS-Less Localization and Mobility Modelling (LMM) System for Wildlife Tracking (2020) (9)
Dynamic Power Management for Neuromorphic Many-Core Systems (2019) (9)
Behavioral Learning in a Cognitive Neuromorphic Robot: An Integrative Approach (2018) (9)
Asynchronous design (1997) (8)
Live demonstration: Handwritten digit recognition using spiking deep belief networks on SpiNNaker (2015) (8)
Quality of Service ( QoS ) for Asynchronous On-Chip Networks (2004) (8)
The Design of an Asynchronous Carry-Lookahead Adder Based on Data Characteristics (2005) (8)
A Spiking Neural Network Model of the Lateral Geniculate Nucleus on the SpiNNaker Machine (2017) (8)
Future Trends in SoC Interconnect (2005) (7)
System-level Modelling for SpiNNaker CMP System (2008) (7)
Design for testability of an asynchronous adder (1996) (7)
An event-driven model for the SpiNNaker virtual synaptic channel (2011) (7)
Stochastic rounding and reduced-precision fixed-point arithmetic for solving neural ODEs. (2019) (7)
The Amulet chips: Architectural development for asynchronous microprocessors (2009) (6)
Meeting the design challenges of nano-CMOS electronics: an introduction to an upcoming EPSRC pilot project (2006) (6)
Visualising large-scale neural network models in real-time (2012) (6)
Evaluating rank-order code performance using a biologically-derived retinal model (2009) (6)
Representing and decoding rank order codes using polychronization in a network of spiking neurons (2011) (6)
A low power embedded dataflow coprocessor (2005) (6)
Algorithm for Mapping Multilayer BP Networks onto the SpiNNaker Neuromorphic Hardware (2010) (6)
Real-Time Recognition of Dynamic Hand Postures on a Neuromorphic System (2015) (6)
26th Annual Computational Neuroscience Meeting (CNS*2017): Part 2 (2017) (6)
Modeling populations of spiking neurons for fine timing sound localization (2013) (6)
spiNNlink: FPGA-Based Interconnect for the Million-Core SpiNNaker System (2020) (6)
Low-Power Low-Latency Keyword Spotting and Adaptive Control with a SpiNNaker 2 Prototype and Comparison with Loihi (2020) (6)
Spike-based learning of transfer functions with the SpiNNaker neuromimetic simulator (2013) (5)
Transport-Independent Protocols for Universal AER Communications (2015) (5)
On-chip timing reference for self-timed microprocessor (2000) (5)
Notes On Pulse Signaling (2007) (5)
Neuromorphic sampling on the SpiNNaker and parallella chip multiprocessors (2016) (5)
Quantization Framework for Fast Spiking Neural Networks (2022) (5)
An admission control system for QoS provision on a best-effort GALS interconnect (2008) (5)
An FPGA Implementation of Convolutional Spiking Neural Networks for Radioisotope Identification (2021) (5)
Optimized task graph mapping on a many-core neuromorphic supercomputer (2017) (5)
SpiNNaker: Event-Based Simulation—Quantitative Behavior (2018) (5)
Asynchronous Embedded Control (1998) (4)
Modelling Graded Semantic Effects in Lexical Decision (2013) (4)
Asynchronous Logic (4)
A novel area-efficient binary adder (2000) (4)
Robustness to Noisy Synaptic Weights in Spiking Neural Networks (2020) (4)
STDP pattern onset learning depends on background activity. (2011) (4)
On generating multicast routes for SpiNNaker (2014) (4)
Adaptive admission control on the SpiNNaker MPSoC (2009) (4)
Asynchronous interface FIFO design on FPGA for high-throughput NRZ synchronisation (2017) (4)
A forecast-based biologically-plausible STDP learning rule (2011) (4)
An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery (2012) (4)
Embodied tactile perception and learning (2020) (4)
Scalable Energy-Efficient, Low-Latency Implementations of Spiking Deep Belief Networks on SpiNNaker (2015) (4)
Event-driven MLP implementation on neuromimetic hardware (2012) (4)
Network traffic exploration on a many-core computing platform: SpiNNaker real-time traffic visualiser (2015) (4)
Validating the AMULET Microprocessors (2002) (4)
Behavioural Modelling of Asynchronous Systems for Power and Performance Analysis (1998) (3)
A Conversation with Steve Furber (2010) (3)
An asynchronous victim cache (2002) (3)
Reliable computation with unreliable computers (2015) (3)
Designing C-elements for Testability (2007) (3)
A communication infrastructure for a million processor machine (2010) (3)
Event-based computation: unsupervised elementary motion decomposition (2019) (3)
Applying asynchronous techniques to a viterbi decoder design (2001) (3)
Live demonstration: Ethernet communication linking two large-scale neuromorphic systems (2013) (3)
Network-on-chip evaluation for a novel neural architecture (2018) (3)
Interconnection system for the spiNNaker biologically inspired multi-computer (2012) (3)
Real-time Application Support for a Novel SoC Architecture (2008) (3)
Spiking Neural Network Based Low-Power Radioisotope Identification using FPGA (2020) (3)
Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems (2017) (3)
Event driven bio-inspired attentive system for the iCub humanoid robot on SpiNNaker (2022) (3)
A System for Transmitting a Coherent Burst of Activity Through a Network of Spiking Neurons (2005) (3)
ATIS + SpiNNaker: a Fully Event-based Visual Tracking Demonstration (2019) (3)
The Design of a Dataflow Coprocessor for Low Power Embedded Hierarchical Processing (2006) (2)
Generating Realistic Semantic Codes for Use in Neural Network Models (2012) (2)
A real-time simulator of a biological visual system composed of a silicon retina and SpiNNaker chips (2014) (2)
Correction to ‘Microprocessors: the engines of the digital age’ (2017) (2)
Event-based Signal Processing for Radioisotope Identification (2020) (2)
Computing Beyond a Million Processors - bio-inspired massively-parallel architectures (2009) (2)
Building Brains (2021) (2)
The SpiNNaker Project This paper describes the design of a massively parallel computer that is suitable for computational neuroscience modeling of large-scale spiking neural networks in biological real time. (2014) (2)
An Introduction to Balsa (2001) (2)
Bio-Inspired Massively-Parallel Computation (2015) (2)
ARM3 - a study in design for compatibility (1990) (2)
Designing asynchronous sequential circuits for random pattern testability (1995) (2)
The Design of the Control Circuits for an Asynchronous Instruction Prefetch Unit Using Signal Transition Graphs (2000) (2)
Asynchronous and self-timed processor design (2007) (2)
A GALS Infrastructure for a Massively Parallel (2008) (2)
SpinNNaker: The world's biggest NoC (2014) (2)
Profiling a Many-core Neuromorphic Platform (2017) (2)
Performance Comparison of Time-Step-Driven versus Event-Driven Neural State Update Approaches in SpiNNaker (2018) (2)
Parallel distribution of an inner hair cell and auditory nerve model for real-time application (2017) (2)
Neural Engineering Framework (2015) (2)
Design, Analysis and Implementation of a Self-Timed Duplex Communication System (2002) (2)
Parallel Distribution of an Inner Hair Cell and Auditory Nerve Model for Real-Time Application (2018) (2)
A biologically inspired algorithm to deal with filter-overlap in retinal models (2009) (2)
The effect of very low axial clearances on the performance of an axial-flow compressor stage (1985) (1)
RISC architecture: D Tabak Research Studies Press, Letchworth, UK (1987) £19.95 pp 175 (1987) (1)
Task Graph Mapping of General Purpose Applications on a Neuromorphic Platform (2017) (1)
Maximising information recovery from rank-order codes - art. no. 65700C (2007) (1)
Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems (2017) (1)
Optimising the overall power usage on the SpiNNaker neuromimetic platform (2014) (1)
Stacks of Software Stacks (2020) (1)
Meeting the design challenges of nano-CMOS electronics, design automation and test in Europe (2008) (1)
Fine-grained or coarse-grained? Strategies for implementing parallel genetic algorithms in a programmable neuromorphic platform (2021) (1)
The Impact of Technology Scaling in the SpiNNaker Chip Multiprocessor (2012) (1)
A 2nd Generation 32b RISC Processor with 4KByte Cache (1989) (1)
Handshake Circuit Implementations (2001) (1)
Evaluation of a Large-Scale SpiNNaker System (2008) (1)
SpiNNaker: Distributed Computer Engineering for Neuromorphics (2011) (1)
Algebraic approach to time borrowing (2013) (1)
Configuring a Large-Scale GALS System (2008) (1)
The advantages of RISC architectures (1988) (1)
Building SpiNNaker Machines (2020) (1)
Biologically-Inspired Massively-Parallel Computation - BIMPC - ERC, EPSRC (2018) (1)
Managing a Massively-Parallel Resource-Constrained Computing Architecture (2012) (1)
Minimizing the Power Consumption of an Asynchronous Multiplier (2004) (1)
A Computational Model of Normal and Impaired Lexical Decision: Graded Semantic Effects (2019) (1)
Spiking Associative Memory for Spatio-Temporal Patterns (2020) (1)
A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect (2009) (0)
Atomic computing - a different perspective on massively parallel problems (2013) (0)
Enabling Low-Power, Fault-Resilient Communications in a Million-Core Neural Processing Architecture (2016) (0)
Unleashing the Potential of Spiking Neural Networks by Dynamic Confidence (2023) (0)
Detecting Fabrication Faults in C-elements (2007) (0)
Large-scale network modelling of interactions between prefrontal cortex and dorsal raphe nucleus using SpiNNaker (2017) (0)
Editorial asynchronous architecture (1996) (0)
Discrete event-based neural simulation using the SpiNNaker system (2015) (0)
Neuromorphic technology in Europe : Brain-inspired technologies are advancing apace across Europe and are poised to help accelerate the AI revolution (2020) (0)
A Simple DMA Controller (2001) (0)
Error driven synapse augmented neurogenesis (2022) (0)
A Fascicle Impulse-Rate Encoded ( FIRE ) Neural Architecture (1998) (0)
The application of spike-timing dependent plasticity to competitive pattern learning. (2009) (0)
SpiNNaker: the design automation problem: the design automation problem (2009) (0)
Static Data-Flow Structures (2001) (0)
Data storage / processor (1994) (0)
Temporal Adaptation – Asynchronicity in Processor Design (2008) (0)
Spiking ratSLAM: Modelling Rat Hippocampus Place, Grid and Border Cells in Spiking Neural Hardware (Demo) (2012) (0)
Editorial (2003) (0)
An asynchronous copy-back cache architecture (2003) (0)
The use of psychometric tests for assessing Mild Cognitive Impairment ; 2 ) Technological aids for interventions in disabilities and learning disorders View project (2018) (0)
Live demonstration: Real-time event-driven object recognition on SpiNNaker (2015) (0)
The Story of the Amulet : A Brief History of Asynchronous Events in Manchester (2016) (0)
Britain Needs Manufacturing (1997) (0)
Realising Turing's Dream (2017) (0)
Generic Aspects of Digital Circuit Behaviour In the Presence of Statistical Variability (2010) (0)
Unsupervised STDP-based Radioisotope Identification Using Spiking Neural Networks Implemented on SpiNNaker (2022) (0)
Appareil de communication insensible aux retards (2000) (0)
Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March - 2 April, 1993 (1993) (0)
RISC architectures : Heudin, J C and Panetto, C Chapman & Hall, London, UK (1992) ISBN 0 412 45340 1, £19.95, pp 261 (1992) (0)
High-Level Languages and Tools (2001) (0)
Prototyping a digital neural network System-on-Chip using an Altera Excalibur device (2004) (0)
Proceedings of the Nineteenth UK Asynchronous Forum (2007) (0)
Design and Implementation of an Asynchronous Controller for FPGA Based Biosignal Processing (2020) (0)
Application-aware Retiming of Accelerators: A High-level Data-driven Approach (2016) (0)
Biologically-Inspired Massively-Parallel Architectures: A Reconfigurable Neural Modelling Platform (2011) (0)
Software-defined PMC for runtime power management of a many-core neuromorphic platform (2017) (0)
The machinations of the mind [brain models] (2008) (0)
Processing with a million cores (2012) (0)
Speed-Independent Control Circuits (2001) (0)
Implementing A New Learning Rule On Spinnaker -- Example: Brader/Fusi/Senn Rule (2018) (0)
Embedded system design (1997) (0)
Live demonstration: Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems (2017) (0)
The Balsa Language (2001) (0)
Microelectronics and Embedded Systems Workshop 2007 (2007) (0)
Edinburgh Research Explorer Navigating the Landscape for Real-time Localisation and Mapping for Robotics, Virtual and Augmented Reality (2018) (0)
A sequence machine built with an asynchronous spiking neural network (2005) (0)
The shroud of Turing (2015) (0)
Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System (2011) (0)
A large-scale computational modelling study to investigate serotonergic modulation of cortical columnar dynamics (2018) (0)
Advanced 4-Phase Bundled-Data Protocols and Circuits (2001) (0)
An Asynchronous Viterbi (0)
Modelling Word and Object Naming in Pure Alexia (2013) (0)
A computational model of typical and impaired reading: the role of visual processing (2021) (0)
Large-Scale On-Chip Dynamic Programming Network Inferences Using Moderated Inter-core Communication (2012) (0)
Instrumental Conditioning with Neuromodulated Plasticity on SpiNNaker (2022) (0)
Maintaining real-time synchrony on SpiNNaker (2011) (0)
Towards Biologically-Plausible Neuron Models and Firing Rates in High-Performance Deep Spiking Neural Networks (2021) (0)
Microprocessors and Microsystems: Editorial (2003) (0)
Supporting Data and Software for Event-based computation: Unsupervised elementary motion decomposition (2019) (0)
Building Library Components (2001) (0)
The First 50 Years Power Management in the Amulet Microprocessors (2001) (0)
! 2 ! Creating , documenting and sharing network models (2012) (0)
An asynchronous spiking neural network which can learn temporal sequences (2006) (0)
THE CALL TO ARMs (2009) (0)
From ARMS to brains - from the Acorn RISC machine to Spiking Neural Network Architecture (2018) (0)
Built-In Self Test Design of an Asynchronous Block Sorter (2007) (0)
Power Consumption and Testability of CMOS VLSI Circuits (2007) (0)
4. Stacks of Software Stacks (2020) (0)
Grounds maintenance at Worcester Polytechnic Institute. (2006) (0)
Origins (2020) (0)
Packet-switched brain models, and cognitive computing (2011) (0)
1. Origins (2020) (0)
Storm outage management. (2006) (0)
8. Creating the Future (2020) (0)
Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies (1993) (0)
BitBrain and Sparse Binary Coincidence (SBC) memories: Fast, robust learning and inference for neuromorphic architectures (2023) (0)
26th Annual Computational Neuroscience Meeting (CNS*2017): Part 2 (2017) (0)
Session details: Quantum computing (2010) (0)
3. Building SpiNNaker Machines (2020) (0)
Biologically-inspired massively-parallel computing (2019) (0)
Transforming Architectural Models Into High Performance Concurrent Implementations (2007) (0)
Chips off of the old block [Packet-Switched Brain Models, and Cognitive Computiing] (2012) (0)
Long- and short-range connectivity and neuronal types affect prefrontal dorsal raphe circuit dynamics differently (2020) (0)

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