Subhasish G. Mitra

Subhasish G. Mitra's AcademicInfluence.com Rankings

Subhasish G. Mitra

Engineering

#6395

World Rank

#7720

Historical Rank

Electrical Engineering

#1898

World Rank

#2000

Historical Rank

engineering Degrees

Subhasish G. Mitra

Computer Science

#8387

World Rank

#8818

Historical Rank

Computer Architecture

#53

World Rank

#55

Historical Rank

Database

#5402

World Rank

#5606

Historical Rank

computer-science Degrees

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Engineering
Computer Science

Subhasish G. Mitra's Degrees

PhD Electrical Engineering University of California, Berkeley
Masters Electrical Engineering University of California, Berkeley

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Subhasish G. Mitra's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Carbon nanotube computer (2013) (822)
Robust system design with built-in soft-error resilience (2005) (589)
The case for RAMClouds: scalable high-performance storage entirely in DRAM (2010) (544)
Circuit Failure Prediction and Its Application to Transistor Aging (2007) (472)
Three-dimensional integration of nanotechnologies for computing and data storage on a single chip (2017) (448)
Addressing failures in exascale computing (2014) (386)
ERSA: Error Resilient System Architecture for probabilistic applications (2010) (342)
Which concurrent error detection scheme to choose ? (2000) (296)
ED4I: Error Detection by Diverse Data and Duplicated Instructions (2002) (271)
Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Devices (2006) (218)
Sequential Element Design With Built-In Soft Error Resilience (2006) (216)
X-compact: an efficient response compaction technique for test cost reduction (2002) (209)
X-compact: an efficient response compaction technique (2004) (208)
Quantitative evaluation of soft error injection techniques for robust system design (2013) (204)
Wafer-Scale Growth and Transfer of Aligned Single-Walled Carbon Nanotubes (2009) (194)
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links (2008) (187)
The case for RAMCloud (2011) (176)
CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns (2008) (170)
Energy-Efficient Abundant-Data Computing: The N3XT 1,000x (2015) (165)
Combinational Logic Soft Error Correction (2006) (159)
Post-silicon validation opportunities, challenges and recent advances (2010) (154)
CMOS-analogous wafer-scale nanotube-on-insulator approach for submicrometer devices and integrated circuits using aligned nanotubes. (2009) (154)
Underdesigned and Opportunistic Computing in Presence of Hardware Variability (2013) (152)
Optimized Circuit Failure Prediction for Aging: Practicality and Promise (2008) (151)
Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections (2007) (134)
Circuit-Level Performance Benchmarking and Scalability Analysis of Carbon Nanotube Transistor Circuits (2009) (130)
Monolithic 3D integration of logic and memory: Carbon nanotube FETs, resistive RAM, and silicon FETs (2014) (128)
Reconfigurable architecture for autonomous self-repair (2004) (124)
Verification-Guided Soft Error Resilience (2007) (118)
Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits (2008) (117)
Word-voter: a new voter design for triple modular redundant systems (2000) (108)
Flexible Control of Block Copolymer Directed Self‐Assembly using Small, Topographical Templates: Potential Lithography Solution for Integrated Circuit Contact Hole Patterning (2012) (106)
Gate exhaustive testing (2005) (103)
IFRA: Instruction Footprint Recording and Analysis for post-silicon bug localization in processors (2008) (100)
Carbon Nanotube Robust Digital VLSI (2012) (100)
Common-mode failures in redundant VLSI systems: a survey (2000) (100)
XPAND: an efficient test stimulus compression technique (2006) (98)
Brain-inspired computing exploiting carbon nanotube FETs and resistive RAM: Hyperdimensional computing case study (2018) (97)
VMR: VLSI-compatible metallic carbon nanotube removal for imperfection-immune cascaded multi-stage digital logic circuits using Carbon Nanotube FETs (2009) (93)
Hyperdimensional computing with 3D VRRAM in-memory kernels: Device-architecture co-design for energy-efficient, error-resilient language recognition (2016) (92)
Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging (2011) (92)
Logic soft errors in sub-65nm technologies design and CAD challenges (2005) (91)
Delay defect characteristics and testing strategies (2003) (89)
Carbon Nanotube circuits in the presence of carbon nanotube density variations (2009) (88)
TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits (2015) (86)
Recent advances and new avenues in hardware-level reliability support (2005) (85)
Threshold Voltage and On–Off Ratio Tuning for Multiple-Tube Carbon Nanotube FETs (2009) (84)
QED: Quick Error Detection tests for effective post-silicon validation (2010) (84)
Solution assembly of organized carbon nanotube networks for thin-film transistors. (2009) (83)
Post-Silicon Bug Localization in Processors Using Instruction Footprint Recording and Analysis (IFRA) (2009) (83)
Efficient FPGAs using nanoelectromechanical relays (2010) (81)
Overcoming Early-Life Failure and Aging for Robust Systems (2009) (79)
Linear increases in carbon nanotube density through multiple transfer technique. (2011) (76)
Efficient seed utilization for reseeding based compression [logic testing] (2003) (76)
Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage (2009) (76)
Packet-based input test data compression techniques (2002) (73)
Soft Error Resilient System Design through Error Correction (2006) (72)
A Design Diversity Metric and Analysis of Redundant Systems (2002) (70)
Carbon nanotube circuit integration up to sub-20 nm channel lengths. (2014) (70)
Built-In Soft Error Resilience for Robust System Design (2007) (70)
Robust System Design to Overcome CMOS Reliability Challenges (2011) (69)
Delay defect screening using process monitor structures (2004) (68)
X-tolerant signature analysis (2004) (68)
CLEAR: Cross-layer exploration for architecting resilience: Combining hardware and software techniques to tolerate soft errors in processor cores (2016) (66)
A design diversity metric and reliability analysis for redundant systems (1999) (65)
Testing for Transistor Aging (2009) (65)
Scalable Carbon Nanotube Computational and Storage Circuits Immune to Metallic and Mispositioned Carbon Nanotubes (2011) (65)
Understanding Energy Efficiency Benefits of Carbon Nanotube Field-Effect Transistors for Digital VLSI (2018) (64)
Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits (2009) (63)
VAST: Virtualization-Assisted Concurrent Autonomous Self-Test (2008) (62)
The N3XT Approach to Energy-Efficient Abundant-Data Computing (2019) (62)
Resistive RAM-Centric Computing: Design and Modeling Methodology (2017) (62)
Dependable Computing and Online Testing in Adaptive and Configurable Systems (2000) (60)
ELF-Murphy data on defects and tests sets (2004) (60)
Device study, chemical doping, and logic circuits based on transferred aligned single-walled carbon nanotubes (2008) (60)
Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip (2011) (60)
Integrated wafer-scale growth and transfer of directional Carbon Nanotubes and misaligned-Carbon-Nanotube-immune logic structures (2008) (58)
Circuit aging prediction for low-power operation (2009) (58)
Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits (2007) (57)
VLSI architecture of a cellular automata machine (1997) (55)
Hysteresis in Carbon Nanotube Transistors: Measurement and Analysis of Trap Density, Energy Level, and Spatial Distribution. (2016) (55)
Sensor-to-Digital Interface Built Entirely With Carbon Nanotube FETs (2014) (55)
Carbon nanotube correlation: Promising opportunity for CNFET circuit yield enhancement (2010) (54)
Integration of nanoelectromechanical (NEM) relays with silicon CMOS with functional CMOS-NEM circuit (2011) (54)
Wafer-scale fabrication and characterization of thin-film transistors with polythiophene-sorted semiconducting carbon nanotube networks. (2012) (52)
Digital VLSI logic technology using Carbon Nanotube FETs: Frequently Asked Questions (2009) (51)
Logic soft errors: a major barrier to robust platform design (2005) (50)
Historical Perspective on Scan Compression (2008) (49)
Effective Post-Silicon Validation of System-on-Chips Using Quick Error Detection (2014) (49)
Test vector compression using EDA-ATE synergies (2002) (49)
Activation of ganglion cells and axon bundles using epiretinal electrical stimulation. (2017) (48)
Response compaction with any number of unknowns using a new LFSR architecture (2005) (48)
New Logic Synthesis as Nanotechnology Enabler (2015) (47)
Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and Their Monolithic 3D Integration (2018) (46)
Automatic configuration generation for FPGA interconnect testing (2003) (46)
BIST reseeding with very few seeds (2003) (46)
Hysteresis-Free Carbon Nanotube Field-Effect Transistors. (2017) (44)
XMAX: X-tolerant architecture for MAXimal test compression (2003) (44)
Cross-layer resilience challenges: Metrics and optimization (2010) (43)
BLoG: Post-Silicon bug localization in processors using bug localization graphs (2010) (42)
Monolithic 3D integration: A path from concept to reality (2015) (42)
Operating system scheduling for efficient online self-test in robust systems (2009) (42)
Evaluation of test metrics: stuck-at, bridge coverage estimate and gate exhaustive (2006) (41)
Overcoming carbon nanotube variations through co-optimized technology and circuit design (2011) (41)
ACCNT—A Metallic-CNT-Tolerant Design Methodology for Carbon-Nanotube VLSI: Concepts and Experimental Demonstration (2009) (41)
Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations (2015) (41)
Fault grading FPGA interconnect test configurations (2002) (41)
Contact-hole patterning for random logic circuits using block copolymer directed self-assembly (2012) (40)
Gate-Oxide Early Life Failure Prediction (2008) (40)
Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations (2011) (39)
The Search for Alternative Computational Paradigms (2008) (39)
Low-cost gate-oxide early-life failure detection in robust systems (2010) (38)
Optimized self-tuning for circuit aging (2010) (38)
X-tolerant test response compaction (2005) (38)
Combinational Logic Design Using Six-Terminal NEM Relays (2013) (37)
Carbon nanotube electronics - Materials, devices, circuits, design, modeling, and performance projection (2011) (37)
Application-independent testing of FPGA interconnects (2005) (37)
Laterally Actuated Platinum-Coated Polysilicon NEM Relays (2013) (37)
Fault Location in FPGA-Based Reconfigurable Systems (1998) (35)
High-performance carbon nanotube field-effect transistors (2014) (35)
Concurrent autonomous self-test for uncore components in system-on-chips (2010) (35)
Quick detection of difficult bugs for effective post-silicon validation (2012) (34)
Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits (2008) (34)
The Trojan-proof chip (2015) (34)
Monolithic three-dimensional integration of carbon nanotube FET complementary logic circuits (2013) (34)
Globally Optimized Robust Systems to Overcome Scaled CMOS Reliability Challenges (2008) (33)
Experimental demonstration of a fully digital capacitive sensor interface built entirely using carbon-nanotube FETs (2013) (33)
A metallic-CNT-tolerant carbon nanotube technology using Asymmetrically-Correlated CNTs (ACCNT) (2006) (32)
California scan architecture for high quality and low power testing (2007) (32)
Efficient metallic carbon nanotube removal readily scalable to wafer-level VLSI CNFET circuits (2010) (32)
Nano-Electro-Mechanical relays for FPGA routing: Experimental demonstration and a design technique (2012) (31)
Efficient metallic carbon nanotube removal for highly-scaled technologies (2015) (31)
Resistive RAM With Multiple Bits Per Cell: Array-Level Demonstration of 3 Bits Per Cell (2019) (31)
Carbon nanotube circuits: Living with imperfections and variations (2010) (30)
Optimized reseeding by seed ordering and encoding (2005) (30)
ACCNT: A Metallic-CNT-Tolerant Design Methodology for Carbon Nanotube VLSI: Analyses and Design Guidelines (2010) (30)
Cooling three-dimensional integrated circuits using power delivery networks (2012) (30)
Resistive RAM Endurance: Array-Level Characterization and Correction Techniques Targeting Deep Learning Applications (2019) (28)
The resilience wall: Cross-layer solution strategies (2014) (27)
Processor Hardware Security Vulnerabilities and their Detection by Unique Program Execution Checking (2018) (27)
Integration of Nanoelectromechanical Relays With Silicon nMOS (2012) (27)
COMPOSITE POLYSILICON-PLATINUM LATERAL NANOELECTROMECHANICAL RELAYS (2010) (26)
Monolithic three-dimensional integrated circuits using carbon nanotube FETs and interconnects (2009) (26)
Optimization of Electrical Stimulation for a High-Fidelity Artificial Retina (2019) (25)
Monolithic three-dimensional integration of carbon nanotube FETs with silicon CMOS (2014) (25)
14.3 A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques (2019) (25)
Soft Errors: Technology Trends, System Effects, and Protection Techniques (2007) (24)
Low-Temperature Side Contact to Carbon Nanotube Transistors: Resistance Distributions Down to 10 nm Contact Length. (2019) (24)
Self-repair of uncore components in robust system-on-chips: An OpenSPARC T2 case study (2013) (24)
Diversity techniques for concurrent error detection (2001) (23)
Future Logic Scaling : Towards Atomic Channels and Deconstructed Chips (2020) (22)
CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference (2021) (22)
High-Density Multiple Bits-per-Cell 1T4R RRAM Array with Gradual SET/RESET and its Effectiveness for Deep Learning (2019) (22)
Combinational logic synthesis for diversity in duplex systems (2000) (21)
X-Codes: Theory and Applications of Unknowable Inputs (2003) (20)
Monolithic 3D integration advances and challenges: From technology to system levels (2014) (20)
Hybrid Quick Error Detection (H-QED): Accelerator validation and debug using high-level synthesis principles (2015) (20)
Application-Dependent Delay Testing of FPGAs (2007) (20)
Design of redundant systems protected against common-mode failures (2001) (20)
A structured approach to post-silicon validation and debug using symbolic quick error detection (2015) (20)
Time-Based Sensor Interface Circuits in CMOS and Carbon Nanotube Technologies (2016) (19)
An evaluation of pseudo random testing for detecting real defects (2001) (19)
Efficient soft error vulnerability estimation of complex designs (2015) (19)
Experimental study of gate oxide early-life failures (2009) (19)
Error Resilient System Architecture ( ERSA ) For Probabilistic Applications (18)
Techniques and algorithms for fault grading of FPGA interconnect test configurations (2004) (18)
Cross-layer error resilience for robust systems (2010) (17)
Air-stable technique for fabricating n-type carbon nanotube FETs (2011) (17)
Architecture and performance evaluation of 3D CMOS-NEM FPGA (2011) (17)
Efficient multiplexer synthesis techniques (2000) (17)
Early-life-failure detection using SAT-based ATPG (2013) (17)
DECOY: DEflection-Driven HLS-Based Computation Partitioning for Obfuscating Intellectual PropertY (2020) (17)
Speed clustering of integrated circuits (2004) (17)
Fast run-time fault location in dependable FPGA-based applications (2001) (17)
Rapid exploration of processing and design guidelines to overcome carbon nanotube variations (2013) (16)
Post-silicon bug localization for processors using IFRA (2010) (16)
Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors (2009) (16)
Understanding soft errors in uncore components (2015) (16)
Carbon nanotube circuits: Opportunities and challenges (2013) (15)
Symbolic quick error detection using symbolic initial state for pre-silicon verification (2018) (15)
Enabling yield analysis with X-compact (2005) (15)
Quick error detection tests with fast runtimes for effective post-silicon validation and debug (2015) (15)
Fault escapes in duplex systems (2000) (15)
Defect and fault tolerance of reconfigurable molecular computing (2004) (14)
Efficient design diversity estimation for combinational circuits (2004) (14)
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience) (2017) (14)
A Formal Approach for Detecting Vulnerabilities to Transient Execution Attacks in Out-of-Order Processors (2020) (14)
NSF expedition on variability-aware software: Recent results and contributions (2015) (14)
System-Level Effects of Soft Errors in Uncore Components (2017) (13)
A Density Metric for Semiconductor Technology [Point of View] (2020) (13)
High-Density 3D Monolithically Integrated Multiple 1T1R Multi-Level-Cell for Neural Networks (2020) (13)
II-DFT: a hybrid dft architecture for low-cost high quality structural testing (2003) (13)
Logic Bug Detection and Localization Using Symbolic Quick Error Detection (2017) (13)
An output encoding problem and a solution technique (1997) (13)
Robust System Design (2010) (13)
A Data-Compressive Wired-OR Readout for Massively Parallel Neural Recording (2019) (13)
DESIGN DIVERSITY FOR REDUNDANT SYSTEMS (1999) (12)
Partitioning Electrostatic and Mechanical Domains in Nanoelectromechanical Relays (2015) (12)
Titanium nitride sidewall stringer process for lateral nanoelectromechanical relays (2010) (11)
Probabilistic analysis of Gallager B faulty decoder (2012) (11)
Gate-oxide early-life failure identification using delay shifts (2010) (11)
Interconnect delay testings of designs on programmable logic devices (2004) (11)
High performance, integrated 1T1R oxide-based oscillator: Stack engineering for low-power operation in neural network applications (2015) (11)
Carbon nanotubes for high-performance logic (2014) (11)
Monolithic 3-D Integration (2019) (11)
Circuit failure prediction to overcome scaled CMOS reliability challenges (2007) (11)
Sacha: The stanford carbon nanotube controlled handshaking robot (2013) (11)
Nano-engineered architectures for ultra-low power wireless body sensor nodes (2016) (10)
The effect of amine protonation on the electrical properties of spin-assembled single-walled carbon nanotube networks (2011) (10)
How To Safeguard Your Sensitive Data (2006) (10)
Design Methodology and Protection Strategy for ESD-CDM Robust Digital System Design in 90-nm and 130-nm Technologies (2009) (10)
S: Error Detection by Diverse Data and Duplicated Instructions (2002) (10)
Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updated (2011) (10)
Fault Detection and Diagnosis Techniques for Molecular Computing (2004) (10)
Design diversity for concurrent error detection in sequential logic circuits (2001) (10)
DUDES: a fault abstraction and collapsing framework for asynchronous circuits (2000) (10)
3D nanosystems enable embedded abundant-data computing: special session paper (2017) (10)
Dual sidewall lateral nanoelectromechanical relays with beam isolation (2011) (10)
System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits (2014) (10)
Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture (2019) (9)
Overcoming post-silicon validation challenges through Quick Error Detection (QED) (2013) (9)
Subhasish Mitra, Norbert Seifert, Ming Zhang, Quan Shi, Kee Sup Kim (2005) (9)
Computing with Carbon Nanotubes (2016) (9)
Imperfection-Immune Carbon Nanotube VLSI Circuits (2011) (9)
Review of Methodologies for Pre- and Post-Silicon Analog Verification in Mixed-Signal SOCs (2019) (9)
Statistical static timing analysis using Markov chain Monte Carlo (2010) (9)
Multiple Independent Gate FETs: How many gates do we need? (2015) (9)
Overcoming Early-Life Failure and Aging Challenges for Robust System Design (2013) (9)
Rethinking error injection for effective resilience (2014) (9)
Illusion of large on-chip memory by networked computing chips for neural network inference (2021) (8)
Device-architecture co-design for hyperdimensional computing with 3d vertical resistive switching random access memory (3D VRRAM) (2017) (8)
Circuit failure prediction for robust system design in scaled CMOS (2008) (8)
Low-power, high-performance S-NDR oscillators for stereo (3D) vision using directly-coupled oscillator networks (2016) (8)
Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study (2019) (8)
Gap-free Processor Verification by S2QED and Property Generation (2020) (8)
A 35.6 TOPS/W/mm² 3-Stage Pipelined Computational SRAM With Adjustable Form Factor for Highly Data-Centric Applications (2020) (8)
Very Low Voltage (VLV) Design (2017) (8)
ETISS-ML: A multi-level instruction set simulator with RTL-level fault injection support for the evaluation of cross-layer resiliency techniques (2018) (8)
Dependable Adaptive Computing Systems the Stanford Crc Roar Project (2001) (8)
E-QED: Electrical Bug Localization During Post-silicon Validation Enabled by Quick Error Detection and Formal Methods (2017) (8)
Scan synthesis for one-hot signals (1997) (8)
TRIG: Hardware Accelerator for Inference-Based Applications and Experimental Demonstration Using Carbon Nanotube FETs (2018) (7)
Spatially patterned bi-electrode epiretinal stimulation for axon avoidance at cellular resolution (2021) (7)
Laterally actuated nanoelectromechanical relays with compliant, low resistance contact (2013) (7)
Macro-Model for Post-Breakdown 90NM and 130NM Transistors and its Applications in Predicting Chip-Level Function Failure after ESD-CDM Events (2007) (6)
Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics (2013) (6)
Testing digital circuits with constraints (2002) (6)
Four-Bits-Per-Memory One-Transistor-and-Eight-Resistive-Random-Access-Memory (1T8R) Array (2021) (6)
Measurement-Based Analysis of Multiple Latent Errors and Near-coincident Fault Discovery in a Shared Memory Multiprocessor (1988) (5)
Automatic Identification of Axon Bundle Activation for Epiretinal Prosthesis (2021) (5)
Techniques for estimation of design diversity for combinational logic circuits (2001) (5)
Design for testability and testing of IEEE 1149.1 TAP controller (2002) (5)
Cross-Layer Resilience: Challenges, Insights, and the Road Ahead (2019) (5)
A Data-Compressive Wired-OR Readout for Massively Parallel Neural Recording (2019) (5)
A-QED Verification of Hardware Accelerators (2020) (5)
QED post-silicon validation and debug: Frequently asked questions (2014) (5)
Circuit Failure Prediction for Robust System Design (2008) (5)
Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization (2020) (4)
Robust design and experimental demonstrations of carbon nanotube digital circuits (2014) (4)
Automatic Identification and Avoidance of Axon Bundle Activation for Epiretinal Prosthesis (2021) (4)
CLEAR: Cross-Layer Exploration for Architecting Resilience (2017) (4)
Hyperdimensional Computing Nanosystem (2018) (4)
RADAR: A Fast and Energy-Efficient Programming Technique for Multiple Bits-Per-Cell RRAM Arrays (2021) (4)
Unlocking the Power of Formal Hardware Verification with CoSA and Symbolic QED: Invited Paper (2019) (4)
Sub-0.5 nm Interfacial Dielectric Enables Superior Electrostatics: 65 mV/dec Top-Gated Carbon Nanotube FETs at 15 nm Gate Length (2020) (4)
IFRA: Post-silicon bug localization in processors (2009) (4)
Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights (2017) (4)
Split-Chip Design to Prevent IP Reverse Engineering (2021) (4)
Fault-Tolerance Projects at Stanford CRC (1999) (4)
Reliable system design: Models, metrics and design techniques (2008) (4)
Fast Run-Time Fault Location in Dependable FPGAs (2001) (4)
Bandgap Extraction at 10 K to Enable Leakage Control in Carbon Nanotube MOSFETs (2022) (3)
Test Compression for FPGAs (2006) (3)
Circuit Failure Prediction Enables Robust System Design Resilient to Aging and Wearout (2007) (3)
An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors (2021) (3)
DFT assisted built-in soft error resilience (2005) (3)
The Future of Hardware Technologies for Computing: N3XT 3D MOSAIC, Illusion Scaleup, Co-Design (2021) (3)
Abundant-data computing: The N3XT 1, 000X (2018) (3)
Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis (2019) (3)
Erratic Bit Errors in Latches (2007) (3)
Effective Pre-Silicon Verification of Processor Cores by Breaking the Bounds of Symbolic Quick Error Detection (2021) (3)
Special session paper 3D nanosystems enable embedded abundant-data computing (2017) (3)
Molybdenum oxide on carbon nanotube: Doping stability and correlation with work function (2020) (3)
Efficient Multiplexer Synthesis (2000) (3)
Heterogeneous 3D Nano-systems: The N3XT Approach? (2020) (2)
AVOIDING ILLEGAL STATES IN PSEUDORANDOM TESTING OF DIGITAL CIRCUITS (2002) (2)
Time-based sensor interface circuits in carbon nanotube technology (2015) (2)
Template Patterning: Flexible Control of Block Copolymer Directed Self-Assembly using Small, Topographical Templates: Potential Lithography Solution for Integrated Circuit Contact Hole Patterning (Adv. Mater. 23/2012) (2012) (2)
Carbon Nanotubes for Monolithic 3D ICs (2017) (2)
Advancements with carbon nanotube digital systems (2014) (2)
Multi-spacer technique for low-voltage, high-aspect-ratio lateral electrostatic actuators (2011) (2)
Selective activation of ganglion cells without axon bundles using epiretinal electrical stimulation (2016) (2)
Coming Up N3XT, After 2D Scaling of Si CMOS (2018) (2)
Symbolic Quick Error Detection for Pre-Silicon and Post-Silicon Validation: Frequently Asked Questions (2016) (2)
Imperfection-immune Carbon Nanotube digital VLSI (2009) (2)
CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference (2022) (2)
BUILT-IN SOFT ERROR RESILIENCE STRUCTURES (2005) (2)
Automatic Problem Localization in Distributed Applications via Multi-dimensional Metric Profiling (2013) (2)
CVD HAFNIUM DIBORIDE AS A CONTACT MATERIAL FOR NANOELECTROMECHANICAL SWITCHES (2012) (2)
Three-Dimensional Stacked Neural Network Accelerator Architectures for AR/VR Applications (2022) (1)
Design and Validation of Robust Systems (2010) (1)
Dual-beam, six-terminal nanoelectromechanical relays (2013) (1)
A systems approach to computing in beyond CMOS fabrics (2017) (1)
Dependable reconfigurable computing design diversity and self repair (2002) (1)
Reliability of graphene interconnects and n-type doping of carbon nanotube transistors (2013) (1)
Variability Expeditions: A Retrospective (2019) (1)
From nanodevices to nanosystems: The N3XT information technology (2015) (1)
Hyperdimensional computing nanosystem: in-memory computing using monolithic 3D integration of RRAM and CNFET (2020) (1)
Bug localization techniques for effective post-silicon validation (2012) (1)
Single-Tube Characterization Methodology for Experimental and Analytical Evaluation of Carbon Nanotube Synthesis (2011) (1)
Transforming nanodevices to next generation nanosystems (2016) (1)
A Theoretical Framework for Symbolic Quick Error Detection (2020) (1)
Four-mask process based on spacer technology for scaled-down lateral NEM electrostatic actuators (2010) (1)
Edward J. McCluskey 1929-2016 (2017) (1)
Carbon electronics — From material synthesis to circuit demonstration (2011) (1)
Sensory Particles with Optical Telemetry (2020) (1)
Nano-Electro-Mechanical (NEM) relays and their application to FPGA routing (2012) (1)
Precise control of neural activity using temporally dithered and spatially multiplexed electrical stimulation (2022) (1)
QED post-silicon validation and debug: Invited abstract (2014) (1)
Designing Circuits with Carbon Nanotubes Open Questions and Some Possible Directions (2006) (1)
Robust platform design in advanced VLSI technologies (2005) (1)
Future Interconnect Materials and System Integration Strategies for Data-Intensive Applications (2018) (1)
NON-SELF-TESTABLE FAULTS IN DUPLEX SYSTEMS (1999) (1)
A new era of computing: Are you "ready now" to build a smarter and secured enterprise? (2014) (1)
Test chip experiments at stanford CRC (2009) (0)
SIGNATUREANALYZER DESIGNFOR YIELDLEARNINGSUPPORT (2006) (0)
Cross layer resiliency in real world (2014) (0)
Extended Scale Length Theory for Low-Dimensional Field-Effect Transistors (2022) (0)
Innovating at Speed and at Scale: A Next Generation Infrastructure for Accelerating Semiconductor Technologies (2022) (0)
Center for Reliable Computing TECHNICAL REPORT Fault Escapes In Duplex Systems (2000) (0)
Dependable embedded systems special day panel: issues and challenges in dependable embedded systems (2008) (0)
Hybrid Quick Error Detection (H-QED) (2015) (0)
Message from the Technical Program Co-Chairs (2020) (0)
Analysis of Practical X-compact Designs (2004) (0)
A Multiplexer (mux) Is a Standard (0)
Soft Errors: System Effects, Protection Techniques and Case Studies (2008) (0)
Debating the Future of Burn-In (2002) (0)
Tutorial T6: Variability-resistant Software and Hardware for Nano-Scale Computing (2012) (0)
58.4: Invited Paper: Solution Assembly of Transistor Arrays Based on Sorted Nanotube Networks for Large‐Scale Flexible Electronic Applications (2009) (0)
1 OUTPUT ENCODING FOR HAZARD-FREE ROBUST PATH DELAY FAULT TESTABILITY (0)
Introduction to the January Special Issue on the 2016 IEEE International Solid-State Circuits Conference (2017) (0)
Session details: Soft error in scaled CMOS design (2008) (0)
Cross-Layer Resilience Challenges: Metrics and Optimization (Invited Paper) (2010) (0)
Carbon nanotube imperfection-immune digital VLSI (2013) (0)
Session details: Design automation and defect tolerance techniques for emerging technologies (2007) (0)
Editorial (2012) (0)
Tutorial 4: Robust System Design in Scaled CMOS (2008) (0)
Session 24 overview: Ultra-efficient computing: Application-inspired and analog-assisted digital (2016) (0)
Carbon-Based Nanomaterial for Nanoelectronics (2011) (0)
Soft Error Protection Techniques (2008) (0)
TRIG (2018) (0)
2010 International Symposium on Electronic System Design ISED 2010 (2010) (0)
ASP-DAC 2017 keynote speech I: In memory of Edward J. McCluskey: The next wave of pioneering innovations (2017) (0)
Beyond-Silicon Devices: Considerations for Circuits and Architectures (2018) (0)
Abundant-data computing: The N3XT 1,000X (2018) (0)
Welcome message (2022) (0)
Invited Lecture by Edward J. McCluskey, the 2008 SIGDA: Pioneering Achievement Award Recipient (2008) (0)
Hot Chips 28 (2017) (0)
Illusion of large on-chip memory by networked computing chips for neural network inference (2021) (0)
Carbon nanotube computer: transforming scientific discoveries into working systems (2014) (0)
Carbon Nanotube FETs for Robust Digital Logic Systems (2014) (0)
Cross-Layer Resilience Exploration (2015) (0)
Bug Detection and Localization Using Symbolic Quick Error Detection 1 (2018) (0)
Resilience in next-generation embedded systems (2017) (0)
Built-In SoftError Resilience forRobustSystemDesign (2007) (0)
Center for Reliable Computing TECHNICAL REPORT Diversity Techniques for Concurrent Error Detection (2000) (0)
[Plenary talks - 11 abstracts] (2014) (0)
(Invited) Cross-Layer Resilience: Challenges, Insights, and the Road Ahead (2019) (0)
Testers don ' t always work when you need them ! ) Defects vs . Faults Some Data from the ELF 35 and Murphy Chips (2002) (0)
Gap-free Processor Verification by S<sup>2</sup>QED and Property Generation (2020) (0)
Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition (2021) (0)
Contact Properties of Titanium Nitride Sidewall Coating for Nanoelectromechanical Electronics (2013) (0)
EVALUATION AND DESIGN OF DEPENDABLE SYSTEMS WITH DESIGN DIVERSITY (0)
Transforming nanodevices into nanosystems: The N3XT 1,000X (2016) (0)
System-level Trade-offs and Optimization for Data-Driven Applications (2018) (0)
Signature Analyzer Design for Yield Learning Support (2006) (0)
Cross-Layer Modeling Framework for Energy-Efficient Resilience (2014) (0)
Statistical Information Processing Extending the Limits of Approximate Computing ∗ (2015) (0)
Testing nanometer digital integrated circuits: myths, reality and the road ahead (2005) (0)
Introduction to the Special Section on Functionality-Enhanced Devices (2014) (0)
TECHNIQUES FOR TESTING DIGITAL CIRCUITS WITH ILLEGAL STATES (2001) (0)
Should Logic SER be Solved at the Circuit Level? (2006) (0)
Cross-Layer Resilience Against Soft Errors: Key Insights (2020) (0)
Exploratory logic synthesis for multiple independent gate FETs (2018) (0)
Robust System Design: Overcoming Complexity and Reliability Challenges (2012) (0)
We hope that the readers will enjoy this special issue and that the contributions presented here will stimulate their interests in the forthcoming technologies for circuits and systems. (2012) (0)
Guest Editorial: Robust and energy-secure systems (2014) (0)
Pseudorandom BIST: Theory, Simulation and Tester Data (2003) (0)
Session details: Targeted test and diagnosis (2009) (0)
Cross-layer resilience (2016) (0)
Session details: Mechanisms for surviving uncertainty: opportunities and prospects (2009) (0)

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