Subramanian Iyer
#117,299
Most Influential Person Now
American engineer of Indian origin
Subramanian Iyer's AcademicInfluence.com Rankings
Subramanian Iyerengineering Degrees
Engineering
#7135
World Rank
#8498
Historical Rank
Electrical Engineering
#2887
World Rank
#3040
Historical Rank
Applied Physics
#3513
World Rank
#3617
Historical Rank
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Engineering
Subramanian Iyer's Degrees
- PhD Electrical Engineering Stanford University
- Masters Electrical Engineering Stanford University
Why Is Subramanian Iyer Influential?
(Suggest an Edit or Addition)According to Wikipedia, Subramanian S. Iyer is an American engineer of Indian origin. He is a Distinguished Professor at the Henry Samueli School of Engineering at UCLA and holds the Charles P. Reames Endowed Chair in the Electrical and Computer Engineering, and a joint appointment in the Department of Material Science and engineering. He is also Director of the Center for Heterogeneous Integration and Performance Scaling at UCLA. Prior to joining UCLA in 2015, he was an IBM Fellow and Director of Packaging Development. He is a fellow of the American Physical Society, The International Microelectronics Assembly and Packaging Society and National Academy of Inventors.
Subramanian Iyer's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- Heterogeneous Integration for Performance and Scaling (2016) (74)
- Heterogeneous Integration at Fine Pitch (≤ 10 µm) Using Thermal Compression Bonding (2017) (54)
- Three-dimensional integration: An industry perspective (2015) (46)
- Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme (2017) (30)
- Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High- $k$ -Metal-Gate CMOS Technologies (2017) (26)
- Electrical Characterization of High Performance Fine Pitch Interconnects in Silicon-Interconnect Fabric (2018) (23)
- The Impact of Self-Heating on Charge Trapping in High- $k$ -Metal-Gate nFETs (2016) (21)
- An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT) (2017) (21)
- A deep learning approach to spine segmentation using a feed-forward chain of pixel-wise convolutional networks (2018) (21)
- Architecting Waferscale Processors - A GPU Case Study (2019) (18)
- Unsupervised Learning Using Charge-Trap Transistors (2017) (14)
- Charge-Trap Transistors for CMOS-Only Analog Memory (2019) (13)
- A Case for Packageless Processors (2018) (13)
- Flexible Hybrid Electronics Technology Using Die-First FOWLP for High-Performance and Scalable Heterogeneous System Integration (2018) (13)
- Fine-Pitch (≤10 µm) Direct Cu-Cu Interconnects Using In-Situ Formic Acid Vapor Treatment (2019) (12)
- Extremely Flexible (1mm Bending Radius) Biocompatible Heterogeneous Fan-Out Wafer-Level Platform with the Lowest Reported Die-Shift (<6 µm) and Reliable Flexible Cu-Based Interconnects (2018) (11)
- Toward Human-Scale Brain Computing Using 3D Wafer Scale Integration (2017) (10)
- Silicon-Interconnect Fabric for Fine-Pitch (≤10 μm) Heterogeneous Integration (2021) (9)
- Demonstration of a Heterogeneously Integrated System-on-Wafer (SoW) Assembly (2018) (9)
- Goodbye, motherboard. Bare chiplets bonded to silicon will make computers smaller and more powerful: Hello, silicon-interconnect fabric (2019) (9)
- Silicon interconnect fabric: A versatile heterogeneous integration platform for AI systems (2019) (8)
- “FlexTrate ^TM” — Scaled Heterogeneous Integration on Flexible Biocompatible Substrates Using FOWLP (2017) (8)
- A Flexible, Heterogeneously Integrated Wireless Powered System for Bio-Implantable Applications using Fan-Out Wafer-Level Packaging (2018) (6)
- Deep learning for medical image segmentation – using the IBM TrueNorth neurosynaptic system (2018) (6)
- Assessing Benefits of a Buried Interconnect Layer in Digital Designs (2017) (6)
- Dynamic Thermal Management Of Silicon Interconnect Fabric Using Flash Cooling (2019) (5)
- Total Ionizing Dose Responses of 22-nm FDSOI and 14-nm Bulk FinFET Charge-Trap Transistors (2021) (5)
- Process Development of Power Delivery Through Wafer Vias for Silicon Interconnect Fabric (2019) (5)
- End-to-End Integration of a Multi-die Glass Interposer for System Scaling Applications (2016) (5)
- Integrated neural interfaces (2017) (4)
- Design Optimization and Modeling of Charge Trap Transistors (CTTs) in 14 nm FinFET Technologies (2019) (4)
- A 16nm 785GMACs/J 784-Core Digital Signal Processor Array With a Multilayer Switch Box Interconnect, Assembled as a 2×2 Dielet with 10μm-Pitch Inter-Dielet I/O for Runtime Multi-Program Reconfiguration (2022) (4)
- Network on interconnect fabric (2018) (4)
- Process development and material characterization of Cu-Cu thermo-compression bonding (TCB) for high-conductivity electrical interconnects. (2016) (3)
- Nb-based superconducting silicon interconnect fabric for cryogenic electronics (2021) (3)
- Optimized Power Delivery for 3D IC Technology Using Grind Side Redistribution Layers (2016) (3)
- Demonstration of a Low Latency (<20 ps) Fine-pitch (≤10 μm) Assembly on the Silicon Interconnect Fabric (2020) (3)
- High Yield Precision Transfer and Assembly of GaN µLEDs Using Laser Assisted Micro Transfer Printing (2019) (3)
- Monolithic three-dimensional integration for memory scaling and neuromorphic computing (2015) (3)
- Three-dimensional wafer scale integration for ultra-large-scale cognitive systems (2017) (3)
- The Impact of Proton-Induced Single Events on Image Classification in a Neuromorphic Computing Architecture (2020) (3)
- Heterogeneous Integration of a Fan-Out Wafer-Level Packaging Based Foldable Display on Elastomeric Substrate (2019) (3)
- Deep Trench Capacitors in Silicon Interconnect Fabric (2020) (3)
- Recess Effect Study and Process Optimization of Sub-10 μm Pitch Die-to-wafer Hybrid Bonding (2022) (2)
- Atomic Layer Deposited Al2O3 Encapsulation for the Silicon Interconnect Fabric (2020) (2)
- Integration and Characterization of InP Die on Silicon Interconnect Fabric (2019) (2)
- On-Chip ESD Monitor (2019) (2)
- Electromigration Studies on 6 µm Solid Cu TSV (Via last) in 32 nm SOI Technology (2016) (2)
- A Flexible Power Module for Wearable Medical Devices with Wireless Recharging using Corrugated Flexible Coils (2021) (2)
- PowerTherm Attach Process for Power Delivery and Heat Extraction in the Silicon-Interconnect Fabric Using Thermocompression Bonding (2019) (2)
- A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping (2019) (2)
- A Heterogeneously Integrated, High Resolution and Flexible Inorganic μLED Display using Fan-Out Wafer-Level Packaging (2020) (2)
- A Signaling Figure of Merit (s-FoM) for Advanced Packaging (2020) (2)
- A High Spatial Resolution Surface Electromyography (sEMG) System Using Fan-Out Wafer-Level Packaging on FlexTrate™ (2020) (1)
- Advanced Packaging and Heterogeneous Integration to Reboot Computing (2017) (1)
- Self-Assembly Technologies for FlexTrate™ (2018) (1)
- 3Di DC-DC Buck Micro Converter with TSVs, Grind Side Inductors, and Deep Trench Decoupling Capacitors in 32nm SOI CMOS (2016) (1)
- Copper to gold thermal compression bonding in heterogenous wafer-scale systems (2021) (1)
- Accuracy and Resiliency of Analog Compute-in-Memory Inference Engines (2020) (1)
- Silicon stress: technical perspective (2014) (1)
- Nanowire Impregnated Poly-dimethyl Siloxane for Flexible, Thermally Conductive Fan-Out Wafer-Level Packaging (2020) (1)
- Global and semi-global communication on Si-IF (2019) (1)
- Flexible Connectors and PCB Segmentation for Signaling and Power Delivery in Wafer-Scale Systems (2021) (1)
- Heterogeneous Integration using the Silicon Interconnect Fabric (2018) (1)
- Functional Demonstration of < 0.4-pJ/bit, 9.8 μm Fine-Pitch Dielet-to-Dielet Links for Advanced Packaging using Silicon Interconnect Fabric (2022) (1)
- Process Integration for FlexTrateTM (2018) (1)
- Low-Temperature Wafer Bonding for Three-Dimensional Wafer-Scale Integration (2018) (1)
- Method and software platform for electronic COTS parts reliability estimation in space applications (2021) (1)
- Heterogenous Integration of MEMS Gas Sensor using FOWLP : Personal Environment Monitors (2020) (1)
- Fabrication of Flexible Ionic-Liquid Thin Film Battery Matrix on FlexTrate™ for Powering Wearable Devices (2021) (1)
- Communication Considerations for Silicon Interconnect Fabric (2019) (1)
- An On-Chip ESD Sensor for Use in Advanced Packaging (2022) (1)
- Fabrication of Flexible Li-ion Battery Electrodes Using "Battlets" Approach with Ionic Liquid Electrolyte for Powering Wearable Devices (2022) (1)
- UNIVERSITY OF CALIFORNIA Los Angeles Process Development of Power Delivery Through Wafer Vias for Silicon Interconnect Fabric A thesis submitted in partial satisfaction of the requirements for the degree Master of Science in Materials Science and Engineering by (2019) (0)
- Split-Fabric: A Novel Wafer-Scale Hardware Obfuscation Methodology using Silicon Interconnect Fabric (2022) (0)
- Low-Frequency and Random Telegraph Noise in 14-nm Bulk Si Charge-Trap Transistors (2023) (0)
- Fine-Pitch (≤ 10 µm) Nb-based Superconducting Silicon Interconnect Fabric for Large-Scale Quantum System Application (2021) (0)
- TSV-less Power Delivery for Wafer-scale Assemblies and Interposers (2022) (0)
- Reliability Studies of Silicon Interconnect Fabric (2019) (0)
- Comprehensive Investigation of In-Plane and Out-of-Plane Die Shift in Flexible Fan-Out Wafer-Level Packaging Using Polydimethylsiloxane (2022) (0)
- A thin film and high roughness flexible current collector for high charging/discharging rate flexible Li-ion battery (2022) (0)
- Smartphone App-Enabled Flex sEMG Patch using FOWLP (2022) (0)
- Non-Volatile Wideband Frequency Tuning of a Ring-Oscillator by Charge Trapping in High-k Gate Dielectric in 22nm CMOS (2020) (0)
- Chips, Dies, Chiplets and Dielets and Heterogeneous Integration (2022) (0)
- Novel high-power delivery architecture for heterogeneous Integration systems (2021) (0)
- A Study on Warpage and Reflow Profile for Extreme Extension of Mass Reflow Bonding (2022) (0)
- Experimental Demonstration of Pressure-Driven Flash Boiling for Transient Two-Phase Cooling (2021) (0)
- "FlexTrate^TM” - Scaled Heterogeneous Integrationon Flexible Biocompatible Substrates using FOWLP - eScholarship (2017) (0)
- Characterization and Design Improvement of a High Bandwidth, High Frequency Flexible Connector for Signal Delivery (2022) (0)
- Nb-Based Superconducting Silicon Interconnect Fabric for Cryogenic Computing Applications (2021) (0)
- Co-optimizing signaling protocol with semiconductor and packaging technology (2021) (0)
- Bilayer Passivation Film for Cu Interconnects on Si Interconnect Fabric (2019) (0)
- RF Characterization on Nb-based Superconducting Silicon Interconnect Fabric for Future Large Scale Quantum Applications (2022) (0)
- Reliability Evaluation of Silicon Interconnect Fabric Technology (2019) (0)
- I/O Architecture, Substrate Design, and Bonding Process for a Heterogeneous Dielet-Assembly based Waferscale Processor (2021) (0)
- Heterogeneous SoCs (2017) (0)
- A Study of the Charge Trap Transistor (CTT) for Post-Fab Modification of Wafers (2018) (0)
- Fine-Pitch Integration Technology for Cognitive System Scaling (2018) (0)
- A Heterogeneously Integrated and Flexible Inorganic Micro-display on FlexTrate™ using Fan-Out Wafer-Level Packaging (2022) (0)
- Development of a technology platform using advanced die-first FOWLP for highly integrated flexible hybrid electronics (2017) (0)
- Performance-based metrology of critical device performance parameters for in-line non-contact high-density intra-die monitor/control on a 32nm SOI advanced logic product platform (2013) (0)
- An 8T eNVSRAM Macro in 22nm FDSOI Standard Logic with Simultaneous Full-Array Data Restore for Secure IoT Devices (2023) (0)
- Antenna on Silicon Interconnect Fabric (2020) (0)
- Fine Pitch(40μm) Integration Platform for Flexible Hybrid Electronics using Fan-Out Wafer-level Packaging (2018) (0)
- Characterization of Fine-Pitch Interconnections (≤ 10 μm) on Silicon Interconnect Fabric for Heterogeneous Integration (2018) (0)
- A 16-nm 784-Core Digital Signal Processor Array, Assembled as a 2 × 2 Dielet With 10-μm Pitch Interdielet I/O for Runtime Multiprogram Reconfiguration (2023) (0)
- Segmented Thermal Management with Flash Cooling for Heterogeneous Wafer-Scale Systems (2021) (0)
- Flexible heterogeneously integrated low form factor wireless multi-channel surface electromyography (sEMG) device (2021) (0)
- Ultra-High Conductivity Interconnects for 77K CMOS Using Heterogeneous Integration (2022) (0)
- DESIGN OF ANALOG MIXED SIGNAL NEURON FOR NEUROMORPHIC COMPUTATION (2019) (0)
- Reliability Considerations for Wafer Scale Systems (2021) (0)
- Demonstration of Analog Compute-In-Memory Using the Charge-Trap Transistor in 22 FDX Technology (2022) (0)
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